| stats.txt (11336:b318499f676c) | stats.txt (11388:bd4125134e77) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.056961 # Number of seconds simulated 4sim_ticks 56960656500 # Number of ticks simulated 5final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.056966 # Number of seconds simulated 4sim_ticks 56966152500 # Number of ticks simulated 5final_tick 56966152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 189048 # Simulator instruction rate (inst/s) 8host_op_rate 241764 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 151847358 # Simulator tick rate (ticks/s) 10host_mem_usage 327812 # Number of bytes of host memory used 11host_seconds 375.12 # Real time elapsed on the host 12sim_insts 70915128 # Number of instructions simulated 13sim_ops 90690084 # Number of ops (including micro ops) simulated | 7host_inst_rate 83103 # Simulator instruction rate (inst/s) 8host_op_rate 106277 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 66756773 # Simulator tick rate (ticks/s) 10host_mem_usage 309512 # Number of bytes of host memory used 11host_seconds 853.34 # Real time elapsed on the host 12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 285184 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 285184 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 7924608 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8209792 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8209856 # Number of bytes read from this memory |
| 19system.physmem.bytes_inst_read::cpu.inst 285184 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 285184 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5517504 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5517504 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4456 # Number of read requests responded to by this memory | 19system.physmem.bytes_inst_read::cpu.inst 285184 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 285184 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5517504 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5517504 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4456 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::cpu.data 123822 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128278 # Number of read requests responded to by this memory | 24system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128279 # Number of read requests responded to by this memory |
| 26system.physmem.num_writes::writebacks 86211 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 86211 # Number of write requests responded to by this memory | 26system.physmem.num_writes::writebacks 86211 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 86211 # Number of write requests responded to by this memory |
| 28system.physmem.bw_read::cpu.inst 5006684 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 139124239 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 144130923 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 5006684 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 5006684 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 96865176 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 96865176 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 96865176 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 5006684 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 139124239 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 240996099 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 128278 # Number of read requests accepted | 28system.physmem.bw_read::cpu.inst 5006201 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 139111940 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 144118141 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 5006201 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 5006201 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 96855830 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 96855830 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 96855830 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 5006201 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 139111940 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 240973971 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 128279 # Number of read requests accepted |
| 40system.physmem.writeReqs 86211 # Number of write requests accepted | 40system.physmem.writeReqs 86211 # Number of write requests accepted |
| 41system.physmem.readBursts 128278 # Number of DRAM read bursts, including those serviced by the write queue | 41system.physmem.readBursts 128279 # Number of DRAM read bursts, including those serviced by the write queue |
| 42system.physmem.writeBursts 86211 # Number of DRAM write bursts, including those merged in the write queue | 42system.physmem.writeBursts 86211 # Number of DRAM write bursts, including those merged in the write queue |
| 43system.physmem.bytesReadDRAM 8209408 # Total number of bytes read from DRAM | 43system.physmem.bytesReadDRAM 8209472 # Total number of bytes read from DRAM |
| 44system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue | 44system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue |
| 45system.physmem.bytesWritten 5515712 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 8209792 # Total read bytes from the system interface side | 45system.physmem.bytesWritten 5515584 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 8209856 # Total read bytes from the system interface side |
| 47system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8061 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8314 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8233 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8140 # Per bank write bursts 55system.physmem.perBankRdBursts::4 8284 # Per bank write bursts | 47system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8061 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8314 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8233 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8140 # Per bank write bursts 55system.physmem.perBankRdBursts::4 8284 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::5 8402 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8056 # Per bank write bursts | 56system.physmem.perBankRdBursts::5 8403 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8055 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::7 7915 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8035 # Per bank write bursts | 58system.physmem.perBankRdBursts::7 7915 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8035 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::9 7586 # Per bank write bursts | 60system.physmem.perBankRdBursts::9 7587 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::10 7763 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7815 # Per bank write bursts 63system.physmem.perBankRdBursts::12 7871 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7867 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7968 # Per bank write bursts 66system.physmem.perBankRdBursts::15 7962 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5394 # Per bank write bursts 68system.physmem.perBankWrBursts::1 5541 # Per bank write bursts | 61system.physmem.perBankRdBursts::10 7763 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7815 # Per bank write bursts 63system.physmem.perBankRdBursts::12 7871 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7867 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7968 # Per bank write bursts 66system.physmem.perBankRdBursts::15 7962 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5394 # Per bank write bursts 68system.physmem.perBankWrBursts::1 5541 # Per bank write bursts |
| 69system.physmem.perBankWrBursts::2 5465 # Per bank write bursts | 69system.physmem.perBankWrBursts::2 5468 # Per bank write bursts |
| 70system.physmem.perBankWrBursts::3 5335 # Per bank write bursts | 70system.physmem.perBankWrBursts::3 5335 # Per bank write bursts |
| 71system.physmem.perBankWrBursts::4 5367 # Per bank write bursts 72system.physmem.perBankWrBursts::5 5560 # Per bank write bursts 73system.physmem.perBankWrBursts::6 5259 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5181 # Per bank write bursts | 71system.physmem.perBankWrBursts::4 5366 # Per bank write bursts 72system.physmem.perBankWrBursts::5 5559 # Per bank write bursts 73system.physmem.perBankWrBursts::6 5257 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5180 # Per bank write bursts |
| 75system.physmem.perBankWrBursts::8 5155 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5101 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5292 # Per bank write bursts 78system.physmem.perBankWrBursts::11 5270 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5531 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5597 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5703 # Per bank write bursts 82system.physmem.perBankWrBursts::15 5432 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 75system.physmem.perBankWrBursts::8 5155 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5101 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5292 # Per bank write bursts 78system.physmem.perBankWrBursts::11 5270 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5531 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5597 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5703 # Per bank write bursts 82system.physmem.perBankWrBursts::15 5432 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 56960624500 # Total gap between requests | 85system.physmem.totGap 56966120500 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 128278 # Read request sizes (log2) | 92system.physmem.readPktSize::6 128279 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 86211 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 86211 # Write request sizes (log2) |
| 100system.physmem.rdQLenPdf::0 116041 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 12210 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::0 116084 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 12167 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 661 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 668 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4041 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5199 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5309 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5322 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 648 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 663 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4078 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5185 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5288 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5314 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5318 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::22 5319 # What write queue length does an incoming req see | 154system.physmem.wrQLenPdf::22 5319 # What write queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::23 5319 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5345 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5368 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5411 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5463 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5462 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5352 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5466 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5451 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5471 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5868 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5446 # What write queue length does an incoming req see |
| 164system.physmem.wrQLenPdf::32 5300 # What write queue length does an incoming req see | 164system.physmem.wrQLenPdf::32 5300 # What write queue length does an incoming req see |
| 165system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see | 165system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see |
| 167system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see | 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see |
| 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 38843 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 353.305769 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 214.370646 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 335.820424 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12327 31.74% 31.74% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 8308 21.39% 53.12% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 4009 10.32% 63.45% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2908 7.49% 70.93% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2579 6.64% 77.57% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1645 4.23% 81.81% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1295 3.33% 85.14% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1183 3.05% 88.19% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 4589 11.81% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 38843 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 24.231438 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 352.038332 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 353.679870 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 214.740030 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 335.847890 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12299 31.70% 31.70% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 8268 21.31% 53.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 4108 10.59% 63.59% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2801 7.22% 70.81% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2598 6.70% 77.50% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1655 4.27% 81.77% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1337 3.45% 85.22% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1145 2.95% 88.17% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 4592 11.83% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5292 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 24.235639 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 352.487123 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5289 99.94% 99.94% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes | 215system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 16.282449 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 16.265601 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.771117 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 4623 87.34% 87.34% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 6 0.11% 87.46% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 534 10.09% 97.54% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 111 2.10% 99.64% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 13 0.25% 99.89% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads 230system.physmem.totQLat 1678352000 # Total ticks spent queuing 231system.physmem.totMemAccLat 4083452000 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 641360000 # Total ticks spent in databus transfers 233system.physmem.avgQLat 13084.32 # Average queueing delay per DRAM burst | 217system.physmem.rdPerTurnAround::total 5292 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 5292 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::mean 16.285147 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 16.266957 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 0.809216 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::16 4635 87.59% 87.59% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::17 6 0.11% 87.70% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 507 9.58% 97.28% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::19 117 2.21% 99.49% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::20 17 0.32% 99.81% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::21 4 0.08% 99.89% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 3 0.06% 99.94% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::24 1 0.02% 99.96% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::25 1 0.02% 99.98% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::total 5292 # Writes before turning the bus around for reads 233system.physmem.totQLat 1670425750 # Total ticks spent queuing 234system.physmem.totMemAccLat 4075544500 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 641365000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 13022.43 # Average queueing delay per DRAM burst |
| 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 235system.physmem.avgMemAccLat 31834.32 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 144.12 # Average DRAM read bandwidth in MiByte/s 237system.physmem.avgWrBW 96.83 # Average achieved write bandwidth in MiByte/s 238system.physmem.avgRdBWSys 144.13 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 96.87 # Average system write bandwidth in MiByte/s | 238system.physmem.avgMemAccLat 31772.43 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 144.11 # Average DRAM read bandwidth in MiByte/s 240system.physmem.avgWrBW 96.82 # Average achieved write bandwidth in MiByte/s 241system.physmem.avgRdBWSys 144.12 # Average system read bandwidth in MiByte/s 242system.physmem.avgWrBWSys 96.86 # Average system write bandwidth in MiByte/s |
| 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 241system.physmem.busUtil 1.88 # Data bus utilization in percentage 242system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes 244system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 244system.physmem.busUtil 1.88 # Data bus utilization in percentage 245system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads 246system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes 247system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 245system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing 246system.physmem.readRowHits 111810 # Number of row buffer hits during reads 247system.physmem.writeRowHits 63793 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes 250system.physmem.avgGap 265564.32 # Average gap between requests 251system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined 252system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ) 253system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ) 254system.physmem_0.readEnergy 509862600 # Energy for read commands per rank (pJ) 255system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ) 256system.physmem_0.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) 257system.physmem_0.actBackEnergy 11565367830 # Energy for active background per rank (pJ) 258system.physmem_0.preBackEnergy 24028947750 # Energy for precharge background per rank (pJ) 259system.physmem_0.totalEnergy 40340244195 # Total energy per rank (pJ) 260system.physmem_0.averagePower 708.261877 # Core power per rank (mW) 261system.physmem_0.memoryStateTime::IDLE 39847901500 # Time in different power states 262system.physmem_0.memoryStateTime::REF 1901900000 # Time in different power states | 248system.physmem.avgWrQLen 23.35 # Average write queue length when enqueuing 249system.physmem.readRowHits 111858 # Number of row buffer hits during reads 250system.physmem.writeRowHits 63787 # Number of row buffer hits during writes 251system.physmem.readRowHitRate 87.20 # Row buffer hit rate for reads 252system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes 253system.physmem.avgGap 265588.70 # Average gap between requests 254system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined 255system.physmem_0.actEnergy 152953920 # Energy for activate commands per rank (pJ) 256system.physmem_0.preEnergy 83457000 # Energy for precharge commands per rank (pJ) 257system.physmem_0.readEnergy 510065400 # Energy for read commands per rank (pJ) 258system.physmem_0.writeEnergy 279210240 # Energy for write commands per rank (pJ) 259system.physmem_0.refreshEnergy 3720624960 # Energy for refresh commands per rank (pJ) 260system.physmem_0.actBackEnergy 11616680655 # Energy for active background per rank (pJ) 261system.physmem_0.preBackEnergy 23988608250 # Energy for precharge background per rank (pJ) 262system.physmem_0.totalEnergy 40351600425 # Total energy per rank (pJ) 263system.physmem_0.averagePower 708.364424 # Core power per rank (mW) 264system.physmem_0.memoryStateTime::IDLE 39782190750 # Time in different power states 265system.physmem_0.memoryStateTime::REF 1902160000 # Time in different power states |
| 263system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 266system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 264system.physmem_0.memoryStateTime::ACT 15206891000 # Time in different power states | 267system.physmem_0.memoryStateTime::ACT 15280128000 # Time in different power states |
| 265system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 268system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 266system.physmem_1.actEnergy 140419440 # Energy for activate commands per rank (pJ) 267system.physmem_1.preEnergy 76617750 # Energy for precharge commands per rank (pJ) 268system.physmem_1.readEnergy 490214400 # Energy for read commands per rank (pJ) | 269system.physmem_1.actEnergy 140358960 # Energy for activate commands per rank (pJ) 270system.physmem_1.preEnergy 76584750 # Energy for precharge commands per rank (pJ) 271system.physmem_1.readEnergy 490315800 # Energy for read commands per rank (pJ) |
| 269system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) | 272system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) |
| 270system.physmem_1.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) 271system.physmem_1.actBackEnergy 10938128715 # Energy for active background per rank (pJ) 272system.physmem_1.preBackEnergy 24579157500 # Energy for precharge background per rank (pJ) 273system.physmem_1.totalEnergy 40223793165 # Total energy per rank (pJ) 274system.physmem_1.averagePower 706.217322 # Core power per rank (mW) 275system.physmem_1.memoryStateTime::IDLE 40763292250 # Time in different power states 276system.physmem_1.memoryStateTime::REF 1901900000 # Time in different power states | 273system.physmem_1.refreshEnergy 3720624960 # Energy for refresh commands per rank (pJ) 274system.physmem_1.actBackEnergy 10974085740 # Energy for active background per rank (pJ) 275system.physmem_1.preBackEnergy 24552288000 # Energy for precharge background per rank (pJ) 276system.physmem_1.totalEnergy 40233397170 # Total energy per rank (pJ) 277system.physmem_1.averagePower 706.289389 # Core power per rank (mW) 278system.physmem_1.memoryStateTime::IDLE 40717988750 # Time in different power states 279system.physmem_1.memoryStateTime::REF 1902160000 # Time in different power states |
| 277system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 278system.physmem_1.memoryStateTime::ACT 14291603250 # Time in different power states | 281system.physmem_1.memoryStateTime::ACT 14344414250 # Time in different power states |
| 279system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 280system.cpu.branchPred.lookups 14800638 # Number of BP lookups 281system.cpu.branchPred.condPredicted 9905777 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 381686 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 9438449 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 6732187 # Number of BTB hits | 283system.cpu.branchPred.lookups 14806373 # Number of BP lookups 284system.cpu.branchPred.condPredicted 9910083 # Number of conditional branches predicted 285system.cpu.branchPred.condIncorrect 383814 # Number of conditional branches incorrect 286system.cpu.branchPred.BTBLookups 9538678 # Number of BTB lookups 287system.cpu.branchPred.BTBHits 6734058 # Number of BTB hits |
| 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 288system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 286system.cpu.branchPred.BTBHitPct 71.327259 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 1714133 # Number of times the RAS was used to get a target. | 289system.cpu.branchPred.BTBHitPct 70.597393 # BTB Hit Percentage 290system.cpu.branchPred.usedRAS 1715002 # Number of times the RAS was used to get a target. |
| 288system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. 289system.cpu_clk_domain.clock 500 # Clock period in ticks 290system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 399system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.itb.read_accesses 0 # DTB read accesses 401system.cpu.itb.write_accesses 0 # DTB write accesses 402system.cpu.itb.inst_accesses 0 # ITB inst accesses 403system.cpu.itb.hits 0 # DTB hits 404system.cpu.itb.misses 0 # DTB misses 405system.cpu.itb.accesses 0 # DTB accesses 406system.cpu.workload.num_syscalls 1946 # Number of system calls | 291system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. 292system.cpu_clk_domain.clock 500 # Clock period in ticks 293system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 402system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 403system.cpu.itb.read_accesses 0 # DTB read accesses 404system.cpu.itb.write_accesses 0 # DTB write accesses 405system.cpu.itb.inst_accesses 0 # ITB inst accesses 406system.cpu.itb.hits 0 # DTB hits 407system.cpu.itb.misses 0 # DTB misses 408system.cpu.itb.accesses 0 # DTB accesses 409system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 407system.cpu.numCycles 113921313 # number of cpu cycles simulated | 410system.cpu.numCycles 113932305 # number of cpu cycles simulated |
| 408system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 409system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 411system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 412system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 410system.cpu.committedInsts 70915128 # Number of instructions committed 411system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed 412system.cpu.discardedOps 1144928 # Number of ops (including micro ops) which were discarded before commit | 413system.cpu.committedInsts 70915150 # Number of instructions committed 414system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed 415system.cpu.discardedOps 1148486 # Number of ops (including micro ops) which were discarded before commit |
| 413system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 416system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 414system.cpu.cpi 1.606446 # CPI: cycles per instruction 415system.cpu.ipc 0.622492 # IPC: instructions per cycle 416system.cpu.tickCycles 95595424 # Number of cycles that the object actually ticked 417system.cpu.idleCycles 18325889 # Total number of cycles that the object has spent stopped 418system.cpu.dcache.tags.replacements 156436 # number of replacements 419system.cpu.dcache.tags.tagsinuse 4067.127430 # Cycle average of tags in use 420system.cpu.dcache.tags.total_refs 42624259 # Total number of references to valid blocks. 421system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks. 422system.cpu.dcache.tags.avg_refs 265.518769 # Average number of references to valid blocks. | 417system.cpu.cpi 1.606600 # CPI: cycles per instruction 418system.cpu.ipc 0.622432 # IPC: instructions per cycle 419system.cpu.tickCycles 95622082 # Number of cycles that the object actually ticked 420system.cpu.idleCycles 18310223 # Total number of cycles that the object has spent stopped 421system.cpu.dcache.tags.replacements 156441 # number of replacements 422system.cpu.dcache.tags.tagsinuse 4067.130215 # Cycle average of tags in use 423system.cpu.dcache.tags.total_refs 42625643 # Total number of references to valid blocks. 424system.cpu.dcache.tags.sampled_refs 160537 # Sample count of references to valid blocks. 425system.cpu.dcache.tags.avg_refs 265.519120 # Average number of references to valid blocks. |
| 423system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. | 426system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. |
| 424system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127430 # Average occupied blocks per requestor 425system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy 426system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy | 427system.cpu.dcache.tags.occ_blocks::cpu.data 4067.130215 # Average occupied blocks per requestor 428system.cpu.dcache.tags.occ_percent::cpu.data 0.992952 # Average percentage of cache occupancy 429system.cpu.dcache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy |
| 427system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 428system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id | 430system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 431system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id |
| 429system.cpu.dcache.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id 430system.cpu.dcache.tags.age_task_id_blocks_1024::2 2947 # Occupied blocks per task id | 432system.cpu.dcache.tags.age_task_id_blocks_1024::1 1097 # Occupied blocks per task id 433system.cpu.dcache.tags.age_task_id_blocks_1024::2 2955 # Occupied blocks per task id |
| 431system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 434system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 432system.cpu.dcache.tags.tag_accesses 86016734 # Number of tag accesses 433system.cpu.dcache.tags.data_accesses 86016734 # Number of data accesses 434system.cpu.dcache.ReadReq_hits::cpu.data 22866824 # number of ReadReq hits 435system.cpu.dcache.ReadReq_hits::total 22866824 # number of ReadReq hits 436system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits 437system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits 438system.cpu.dcache.SoftPFReq_hits::cpu.data 83418 # number of SoftPFReq hits 439system.cpu.dcache.SoftPFReq_hits::total 83418 # number of SoftPFReq hits | 435system.cpu.dcache.tags.tag_accesses 86019473 # Number of tag accesses 436system.cpu.dcache.tags.data_accesses 86019473 # Number of data accesses 437system.cpu.dcache.ReadReq_hits::cpu.data 22868200 # number of ReadReq hits 438system.cpu.dcache.ReadReq_hits::total 22868200 # number of ReadReq hits 439system.cpu.dcache.WriteReq_hits::cpu.data 19642188 # number of WriteReq hits 440system.cpu.dcache.WriteReq_hits::total 19642188 # number of WriteReq hits 441system.cpu.dcache.SoftPFReq_hits::cpu.data 83417 # number of SoftPFReq hits 442system.cpu.dcache.SoftPFReq_hits::total 83417 # number of SoftPFReq hits |
| 440system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 441system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 442system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 443system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 443system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 444system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 445system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 446system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 444system.cpu.dcache.demand_hits::cpu.data 42509003 # number of demand (read+write) hits 445system.cpu.dcache.demand_hits::total 42509003 # number of demand (read+write) hits 446system.cpu.dcache.overall_hits::cpu.data 42592421 # number of overall hits 447system.cpu.dcache.overall_hits::total 42592421 # number of overall hits 448system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses 449system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses 450system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses 451system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses 452system.cpu.dcache.SoftPFReq_misses::cpu.data 44587 # number of SoftPFReq misses 453system.cpu.dcache.SoftPFReq_misses::total 44587 # number of SoftPFReq misses 454system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses 455system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses 456system.cpu.dcache.overall_misses::cpu.data 303842 # number of overall misses 457system.cpu.dcache.overall_misses::total 303842 # number of overall misses 458system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489955500 # number of ReadReq miss cycles 459system.cpu.dcache.ReadReq_miss_latency::total 1489955500 # number of ReadReq miss cycles 460system.cpu.dcache.WriteReq_miss_latency::cpu.data 16807631000 # number of WriteReq miss cycles 461system.cpu.dcache.WriteReq_miss_latency::total 16807631000 # number of WriteReq miss cycles 462system.cpu.dcache.demand_miss_latency::cpu.data 18297586500 # number of demand (read+write) miss cycles 463system.cpu.dcache.demand_miss_latency::total 18297586500 # number of demand (read+write) miss cycles 464system.cpu.dcache.overall_miss_latency::cpu.data 18297586500 # number of overall miss cycles 465system.cpu.dcache.overall_miss_latency::total 18297586500 # number of overall miss cycles 466system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) 467system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) | 447system.cpu.dcache.demand_hits::cpu.data 42510388 # number of demand (read+write) hits 448system.cpu.dcache.demand_hits::total 42510388 # number of demand (read+write) hits 449system.cpu.dcache.overall_hits::cpu.data 42593805 # number of overall hits 450system.cpu.dcache.overall_hits::total 42593805 # number of overall hits 451system.cpu.dcache.ReadReq_misses::cpu.data 51522 # number of ReadReq misses 452system.cpu.dcache.ReadReq_misses::total 51522 # number of ReadReq misses 453system.cpu.dcache.WriteReq_misses::cpu.data 207713 # number of WriteReq misses 454system.cpu.dcache.WriteReq_misses::total 207713 # number of WriteReq misses 455system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses 456system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses 457system.cpu.dcache.demand_misses::cpu.data 259235 # number of demand (read+write) misses 458system.cpu.dcache.demand_misses::total 259235 # number of demand (read+write) misses 459system.cpu.dcache.overall_misses::cpu.data 303825 # number of overall misses 460system.cpu.dcache.overall_misses::total 303825 # number of overall misses 461system.cpu.dcache.ReadReq_miss_latency::cpu.data 1488627000 # number of ReadReq miss cycles 462system.cpu.dcache.ReadReq_miss_latency::total 1488627000 # number of ReadReq miss cycles 463system.cpu.dcache.WriteReq_miss_latency::cpu.data 16793358000 # number of WriteReq miss cycles 464system.cpu.dcache.WriteReq_miss_latency::total 16793358000 # number of WriteReq miss cycles 465system.cpu.dcache.demand_miss_latency::cpu.data 18281985000 # number of demand (read+write) miss cycles 466system.cpu.dcache.demand_miss_latency::total 18281985000 # number of demand (read+write) miss cycles 467system.cpu.dcache.overall_miss_latency::cpu.data 18281985000 # number of overall miss cycles 468system.cpu.dcache.overall_miss_latency::total 18281985000 # number of overall miss cycles 469system.cpu.dcache.ReadReq_accesses::cpu.data 22919722 # number of ReadReq accesses(hits+misses) 470system.cpu.dcache.ReadReq_accesses::total 22919722 # number of ReadReq accesses(hits+misses) |
| 468system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 469system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 471system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 472system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 470system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) 471system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses) | 473system.cpu.dcache.SoftPFReq_accesses::cpu.data 128007 # number of SoftPFReq accesses(hits+misses) 474system.cpu.dcache.SoftPFReq_accesses::total 128007 # number of SoftPFReq accesses(hits+misses) |
| 472system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 475system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 476system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 477system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 478system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 476system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses 477system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses 478system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses 479system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses 480system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses 481system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses 482system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses 483system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses 484system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348322 # miss rate for SoftPFReq accesses 485system.cpu.dcache.SoftPFReq_miss_rate::total 0.348322 # miss rate for SoftPFReq accesses 486system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses 487system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses | 479system.cpu.dcache.demand_accesses::cpu.data 42769623 # number of demand (read+write) accesses 480system.cpu.dcache.demand_accesses::total 42769623 # number of demand (read+write) accesses 481system.cpu.dcache.overall_accesses::cpu.data 42897630 # number of overall (read+write) accesses 482system.cpu.dcache.overall_accesses::total 42897630 # number of overall (read+write) accesses 483system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002248 # miss rate for ReadReq accesses 484system.cpu.dcache.ReadReq_miss_rate::total 0.002248 # miss rate for ReadReq accesses 485system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses 486system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses 487system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348340 # miss rate for SoftPFReq accesses 488system.cpu.dcache.SoftPFReq_miss_rate::total 0.348340 # miss rate for SoftPFReq accesses 489system.cpu.dcache.demand_miss_rate::cpu.data 0.006061 # miss rate for demand accesses 490system.cpu.dcache.demand_miss_rate::total 0.006061 # miss rate for demand accesses |
| 488system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses 489system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses | 491system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses 492system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses |
| 490system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28912.648206 # average ReadReq miss latency 491system.cpu.dcache.ReadReq_avg_miss_latency::total 28912.648206 # average ReadReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80914.063027 # average WriteReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::total 80914.063027 # average WriteReq miss latency 494system.cpu.dcache.demand_avg_miss_latency::cpu.data 70577.564560 # average overall miss latency 495system.cpu.dcache.demand_avg_miss_latency::total 70577.564560 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::cpu.data 60220.728207 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::total 60220.728207 # average overall miss latency | 493system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28893.035985 # average ReadReq miss latency 494system.cpu.dcache.ReadReq_avg_miss_latency::total 28893.035985 # average ReadReq miss latency 495system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80848.853948 # average WriteReq miss latency 496system.cpu.dcache.WriteReq_avg_miss_latency::total 80848.853948 # average WriteReq miss latency 497system.cpu.dcache.demand_avg_miss_latency::cpu.data 70522.826779 # average overall miss latency 498system.cpu.dcache.demand_avg_miss_latency::total 70522.826779 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::cpu.data 60172.747470 # average overall miss latency 500system.cpu.dcache.overall_avg_miss_latency::total 60172.747470 # average overall miss latency |
| 498system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.dcache.fast_writes 0 # number of fast writes performed 505system.cpu.dcache.cache_copies 0 # number of cache copies performed | 501system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 502system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 504system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 506system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 507system.cpu.dcache.fast_writes 0 # number of fast writes performed 508system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 506system.cpu.dcache.writebacks::writebacks 128377 # number of writebacks 507system.cpu.dcache.writebacks::total 128377 # number of writebacks 508system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22014 # number of ReadReq MSHR hits 509system.cpu.dcache.ReadReq_mshr_hits::total 22014 # number of ReadReq MSHR hits 510system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100694 # number of WriteReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::total 100694 # number of WriteReq MSHR hits 512system.cpu.dcache.demand_mshr_hits::cpu.data 122708 # number of demand (read+write) MSHR hits 513system.cpu.dcache.demand_mshr_hits::total 122708 # number of demand (read+write) MSHR hits 514system.cpu.dcache.overall_mshr_hits::cpu.data 122708 # number of overall MSHR hits 515system.cpu.dcache.overall_mshr_hits::total 122708 # number of overall MSHR hits 516system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29519 # number of ReadReq MSHR misses 517system.cpu.dcache.ReadReq_mshr_misses::total 29519 # number of ReadReq MSHR misses | 509system.cpu.dcache.writebacks::writebacks 128384 # number of writebacks 510system.cpu.dcache.writebacks::total 128384 # number of writebacks 511system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22002 # number of ReadReq MSHR hits 512system.cpu.dcache.ReadReq_mshr_hits::total 22002 # number of ReadReq MSHR hits 513system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100685 # number of WriteReq MSHR hits 514system.cpu.dcache.WriteReq_mshr_hits::total 100685 # number of WriteReq MSHR hits 515system.cpu.dcache.demand_mshr_hits::cpu.data 122687 # number of demand (read+write) MSHR hits 516system.cpu.dcache.demand_mshr_hits::total 122687 # number of demand (read+write) MSHR hits 517system.cpu.dcache.overall_mshr_hits::cpu.data 122687 # number of overall MSHR hits 518system.cpu.dcache.overall_mshr_hits::total 122687 # number of overall MSHR hits 519system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29520 # number of ReadReq MSHR misses 520system.cpu.dcache.ReadReq_mshr_misses::total 29520 # number of ReadReq MSHR misses |
| 518system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses 519system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses | 521system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses 522system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses |
| 520system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses 521system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses 522system.cpu.dcache.demand_mshr_misses::cpu.data 136547 # number of demand (read+write) MSHR misses 523system.cpu.dcache.demand_mshr_misses::total 136547 # number of demand (read+write) MSHR misses 524system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses 525system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses 526system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 577658500 # number of ReadReq MSHR miss cycles 527system.cpu.dcache.ReadReq_mshr_miss_latency::total 577658500 # number of ReadReq MSHR miss cycles 528system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488450500 # number of WriteReq MSHR miss cycles 529system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488450500 # number of WriteReq MSHR miss cycles 530system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1712416500 # number of SoftPFReq MSHR miss cycles 531system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1712416500 # number of SoftPFReq MSHR miss cycles 532system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066109000 # number of demand (read+write) MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::total 9066109000 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10778525500 # number of overall MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::total 10778525500 # number of overall MSHR miss cycles | 523system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23989 # number of SoftPFReq MSHR misses 524system.cpu.dcache.SoftPFReq_mshr_misses::total 23989 # number of SoftPFReq MSHR misses 525system.cpu.dcache.demand_mshr_misses::cpu.data 136548 # number of demand (read+write) MSHR misses 526system.cpu.dcache.demand_mshr_misses::total 136548 # number of demand (read+write) MSHR misses 527system.cpu.dcache.overall_mshr_misses::cpu.data 160537 # number of overall MSHR misses 528system.cpu.dcache.overall_mshr_misses::total 160537 # number of overall MSHR misses 529system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 575604000 # number of ReadReq MSHR miss cycles 530system.cpu.dcache.ReadReq_mshr_miss_latency::total 575604000 # number of ReadReq MSHR miss cycles 531system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8480832000 # number of WriteReq MSHR miss cycles 532system.cpu.dcache.WriteReq_mshr_miss_latency::total 8480832000 # number of WriteReq MSHR miss cycles 533system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713530500 # number of SoftPFReq MSHR miss cycles 534system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713530500 # number of SoftPFReq MSHR miss cycles 535system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9056436000 # number of demand (read+write) MSHR miss cycles 536system.cpu.dcache.demand_mshr_miss_latency::total 9056436000 # number of demand (read+write) MSHR miss cycles 537system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10769966500 # number of overall MSHR miss cycles 538system.cpu.dcache.overall_mshr_miss_latency::total 10769966500 # number of overall MSHR miss cycles |
| 536system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses 537system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses 538system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 539system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses | 539system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses 540system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses 541system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 542system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses |
| 540system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses 541system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses | 543system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187404 # mshr miss rate for SoftPFReq accesses 544system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187404 # mshr miss rate for SoftPFReq accesses |
| 542system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses 543system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses 544system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 545system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses | 545system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses 546system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses 547system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 548system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses |
| 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19569.040279 # average ReadReq mshr miss latency 547system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19569.040279 # average ReadReq mshr miss latency 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79310.558919 # average WriteReq mshr miss latency 549system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79310.558919 # average WriteReq mshr miss latency 550system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71395.309568 # average SoftPFReq mshr miss latency 551system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71395.309568 # average SoftPFReq mshr miss latency 552system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66395.519491 # average overall mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::total 66395.519491 # average overall mshr miss latency 554system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67142.535445 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::total 67142.535445 # average overall mshr miss latency | 549system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19498.780488 # average ReadReq mshr miss latency 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19498.780488 # average ReadReq mshr miss latency 551system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79239.376612 # average WriteReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79239.376612 # average WriteReq mshr miss latency 553system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71429.842845 # average SoftPFReq mshr miss latency 554system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71429.842845 # average SoftPFReq mshr miss latency 555system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66324.193690 # average overall mshr miss latency 556system.cpu.dcache.demand_avg_mshr_miss_latency::total 66324.193690 # average overall mshr miss latency 557system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67087.129447 # average overall mshr miss latency 558system.cpu.dcache.overall_avg_mshr_miss_latency::total 67087.129447 # average overall mshr miss latency |
| 556system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 559system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 557system.cpu.icache.tags.replacements 42868 # number of replacements 558system.cpu.icache.tags.tagsinuse 1852.481887 # Cycle average of tags in use 559system.cpu.icache.tags.total_refs 24941232 # Total number of references to valid blocks. 560system.cpu.icache.tags.sampled_refs 44910 # Sample count of references to valid blocks. 561system.cpu.icache.tags.avg_refs 555.360321 # Average number of references to valid blocks. | 560system.cpu.icache.tags.replacements 42871 # number of replacements 561system.cpu.icache.tags.tagsinuse 1852.494475 # Cycle average of tags in use 562system.cpu.icache.tags.total_refs 24951243 # Total number of references to valid blocks. 563system.cpu.icache.tags.sampled_refs 44913 # Sample count of references to valid blocks. 564system.cpu.icache.tags.avg_refs 555.546123 # Average number of references to valid blocks. |
| 562system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 565system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 563system.cpu.icache.tags.occ_blocks::cpu.inst 1852.481887 # Average occupied blocks per requestor 564system.cpu.icache.tags.occ_percent::cpu.inst 0.904532 # Average percentage of cache occupancy 565system.cpu.icache.tags.occ_percent::total 0.904532 # Average percentage of cache occupancy | 566system.cpu.icache.tags.occ_blocks::cpu.inst 1852.494475 # Average occupied blocks per requestor 567system.cpu.icache.tags.occ_percent::cpu.inst 0.904538 # Average percentage of cache occupancy 568system.cpu.icache.tags.occ_percent::total 0.904538 # Average percentage of cache occupancy |
| 566system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id | 569system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id |
| 567system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 568system.cpu.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id 569system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id 570system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id | 570system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 571system.cpu.icache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id 572system.cpu.icache.tags.age_task_id_blocks_1024::3 917 # Occupied blocks per task id 573system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id |
| 571system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id | 574system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id |
| 572system.cpu.icache.tags.tag_accesses 50017196 # Number of tag accesses 573system.cpu.icache.tags.data_accesses 50017196 # Number of data accesses 574system.cpu.icache.ReadReq_hits::cpu.inst 24941232 # number of ReadReq hits 575system.cpu.icache.ReadReq_hits::total 24941232 # number of ReadReq hits 576system.cpu.icache.demand_hits::cpu.inst 24941232 # number of demand (read+write) hits 577system.cpu.icache.demand_hits::total 24941232 # number of demand (read+write) hits 578system.cpu.icache.overall_hits::cpu.inst 24941232 # number of overall hits 579system.cpu.icache.overall_hits::total 24941232 # number of overall hits 580system.cpu.icache.ReadReq_misses::cpu.inst 44911 # number of ReadReq misses 581system.cpu.icache.ReadReq_misses::total 44911 # number of ReadReq misses 582system.cpu.icache.demand_misses::cpu.inst 44911 # number of demand (read+write) misses 583system.cpu.icache.demand_misses::total 44911 # number of demand (read+write) misses 584system.cpu.icache.overall_misses::cpu.inst 44911 # number of overall misses 585system.cpu.icache.overall_misses::total 44911 # number of overall misses 586system.cpu.icache.ReadReq_miss_latency::cpu.inst 896725000 # number of ReadReq miss cycles 587system.cpu.icache.ReadReq_miss_latency::total 896725000 # number of ReadReq miss cycles 588system.cpu.icache.demand_miss_latency::cpu.inst 896725000 # number of demand (read+write) miss cycles 589system.cpu.icache.demand_miss_latency::total 896725000 # number of demand (read+write) miss cycles 590system.cpu.icache.overall_miss_latency::cpu.inst 896725000 # number of overall miss cycles 591system.cpu.icache.overall_miss_latency::total 896725000 # number of overall miss cycles 592system.cpu.icache.ReadReq_accesses::cpu.inst 24986143 # number of ReadReq accesses(hits+misses) 593system.cpu.icache.ReadReq_accesses::total 24986143 # number of ReadReq accesses(hits+misses) 594system.cpu.icache.demand_accesses::cpu.inst 24986143 # number of demand (read+write) accesses 595system.cpu.icache.demand_accesses::total 24986143 # number of demand (read+write) accesses 596system.cpu.icache.overall_accesses::cpu.inst 24986143 # number of overall (read+write) accesses 597system.cpu.icache.overall_accesses::total 24986143 # number of overall (read+write) accesses | 575system.cpu.icache.tags.tag_accesses 50037227 # Number of tag accesses 576system.cpu.icache.tags.data_accesses 50037227 # Number of data accesses 577system.cpu.icache.ReadReq_hits::cpu.inst 24951243 # number of ReadReq hits 578system.cpu.icache.ReadReq_hits::total 24951243 # number of ReadReq hits 579system.cpu.icache.demand_hits::cpu.inst 24951243 # number of demand (read+write) hits 580system.cpu.icache.demand_hits::total 24951243 # number of demand (read+write) hits 581system.cpu.icache.overall_hits::cpu.inst 24951243 # number of overall hits 582system.cpu.icache.overall_hits::total 24951243 # number of overall hits 583system.cpu.icache.ReadReq_misses::cpu.inst 44914 # number of ReadReq misses 584system.cpu.icache.ReadReq_misses::total 44914 # number of ReadReq misses 585system.cpu.icache.demand_misses::cpu.inst 44914 # number of demand (read+write) misses 586system.cpu.icache.demand_misses::total 44914 # number of demand (read+write) misses 587system.cpu.icache.overall_misses::cpu.inst 44914 # number of overall misses 588system.cpu.icache.overall_misses::total 44914 # number of overall misses 589system.cpu.icache.ReadReq_miss_latency::cpu.inst 896931500 # number of ReadReq miss cycles 590system.cpu.icache.ReadReq_miss_latency::total 896931500 # number of ReadReq miss cycles 591system.cpu.icache.demand_miss_latency::cpu.inst 896931500 # number of demand (read+write) miss cycles 592system.cpu.icache.demand_miss_latency::total 896931500 # number of demand (read+write) miss cycles 593system.cpu.icache.overall_miss_latency::cpu.inst 896931500 # number of overall miss cycles 594system.cpu.icache.overall_miss_latency::total 896931500 # number of overall miss cycles 595system.cpu.icache.ReadReq_accesses::cpu.inst 24996157 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.ReadReq_accesses::total 24996157 # number of ReadReq accesses(hits+misses) 597system.cpu.icache.demand_accesses::cpu.inst 24996157 # number of demand (read+write) accesses 598system.cpu.icache.demand_accesses::total 24996157 # number of demand (read+write) accesses 599system.cpu.icache.overall_accesses::cpu.inst 24996157 # number of overall (read+write) accesses 600system.cpu.icache.overall_accesses::total 24996157 # number of overall (read+write) accesses |
| 598system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses 599system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses 600system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses 601system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses 602system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses 603system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses | 601system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses 602system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses 603system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses 604system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses 605system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses 606system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses |
| 604system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19966.711941 # average ReadReq miss latency 605system.cpu.icache.ReadReq_avg_miss_latency::total 19966.711941 # average ReadReq miss latency 606system.cpu.icache.demand_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency 607system.cpu.icache.demand_avg_miss_latency::total 19966.711941 # average overall miss latency 608system.cpu.icache.overall_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency 609system.cpu.icache.overall_avg_miss_latency::total 19966.711941 # average overall miss latency | 607system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19969.975954 # average ReadReq miss latency 608system.cpu.icache.ReadReq_avg_miss_latency::total 19969.975954 # average ReadReq miss latency 609system.cpu.icache.demand_avg_miss_latency::cpu.inst 19969.975954 # average overall miss latency 610system.cpu.icache.demand_avg_miss_latency::total 19969.975954 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::cpu.inst 19969.975954 # average overall miss latency 612system.cpu.icache.overall_avg_miss_latency::total 19969.975954 # average overall miss latency |
| 610system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu.icache.fast_writes 0 # number of fast writes performed 617system.cpu.icache.cache_copies 0 # number of cache copies performed | 613system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 614system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 615system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 616system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 617system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 618system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 619system.cpu.icache.fast_writes 0 # number of fast writes performed 620system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 618system.cpu.icache.writebacks::writebacks 42868 # number of writebacks 619system.cpu.icache.writebacks::total 42868 # number of writebacks 620system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44911 # number of ReadReq MSHR misses 621system.cpu.icache.ReadReq_mshr_misses::total 44911 # number of ReadReq MSHR misses 622system.cpu.icache.demand_mshr_misses::cpu.inst 44911 # number of demand (read+write) MSHR misses 623system.cpu.icache.demand_mshr_misses::total 44911 # number of demand (read+write) MSHR misses 624system.cpu.icache.overall_mshr_misses::cpu.inst 44911 # number of overall MSHR misses 625system.cpu.icache.overall_mshr_misses::total 44911 # number of overall MSHR misses 626system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 851815000 # number of ReadReq MSHR miss cycles 627system.cpu.icache.ReadReq_mshr_miss_latency::total 851815000 # number of ReadReq MSHR miss cycles 628system.cpu.icache.demand_mshr_miss_latency::cpu.inst 851815000 # number of demand (read+write) MSHR miss cycles 629system.cpu.icache.demand_mshr_miss_latency::total 851815000 # number of demand (read+write) MSHR miss cycles 630system.cpu.icache.overall_mshr_miss_latency::cpu.inst 851815000 # number of overall MSHR miss cycles 631system.cpu.icache.overall_mshr_miss_latency::total 851815000 # number of overall MSHR miss cycles | 621system.cpu.icache.writebacks::writebacks 42871 # number of writebacks 622system.cpu.icache.writebacks::total 42871 # number of writebacks 623system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44914 # number of ReadReq MSHR misses 624system.cpu.icache.ReadReq_mshr_misses::total 44914 # number of ReadReq MSHR misses 625system.cpu.icache.demand_mshr_misses::cpu.inst 44914 # number of demand (read+write) MSHR misses 626system.cpu.icache.demand_mshr_misses::total 44914 # number of demand (read+write) MSHR misses 627system.cpu.icache.overall_mshr_misses::cpu.inst 44914 # number of overall MSHR misses 628system.cpu.icache.overall_mshr_misses::total 44914 # number of overall MSHR misses 629system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 852018500 # number of ReadReq MSHR miss cycles 630system.cpu.icache.ReadReq_mshr_miss_latency::total 852018500 # number of ReadReq MSHR miss cycles 631system.cpu.icache.demand_mshr_miss_latency::cpu.inst 852018500 # number of demand (read+write) MSHR miss cycles 632system.cpu.icache.demand_mshr_miss_latency::total 852018500 # number of demand (read+write) MSHR miss cycles 633system.cpu.icache.overall_mshr_miss_latency::cpu.inst 852018500 # number of overall MSHR miss cycles 634system.cpu.icache.overall_mshr_miss_latency::total 852018500 # number of overall MSHR miss cycles |
| 632system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses 633system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses 634system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses 635system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses 636system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses 637system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses | 635system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses 636system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses 637system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses 638system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses 639system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses 640system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses |
| 638system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18966.734208 # average ReadReq mshr miss latency 639system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18966.734208 # average ReadReq mshr miss latency 640system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency 641system.cpu.icache.demand_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency 642system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency 643system.cpu.icache.overall_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency | 641system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18969.998219 # average ReadReq mshr miss latency 642system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18969.998219 # average ReadReq mshr miss latency 643system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18969.998219 # average overall mshr miss latency 644system.cpu.icache.demand_avg_mshr_miss_latency::total 18969.998219 # average overall mshr miss latency 645system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18969.998219 # average overall mshr miss latency 646system.cpu.icache.overall_avg_mshr_miss_latency::total 18969.998219 # average overall mshr miss latency |
| 644system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 647system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 645system.cpu.l2cache.tags.replacements 96386 # number of replacements 646system.cpu.l2cache.tags.tagsinuse 29871.418055 # Cycle average of tags in use 647system.cpu.l2cache.tags.total_refs 162162 # Total number of references to valid blocks. 648system.cpu.l2cache.tags.sampled_refs 127539 # Sample count of references to valid blocks. 649system.cpu.l2cache.tags.avg_refs 1.271470 # Average number of references to valid blocks. | 648system.cpu.l2cache.tags.replacements 96387 # number of replacements 649system.cpu.l2cache.tags.tagsinuse 29871.556792 # Cycle average of tags in use 650system.cpu.l2cache.tags.total_refs 162176 # Total number of references to valid blocks. 651system.cpu.l2cache.tags.sampled_refs 127540 # Sample count of references to valid blocks. 652system.cpu.l2cache.tags.avg_refs 1.271570 # Average number of references to valid blocks. |
| 650system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 653system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 651system.cpu.l2cache.tags.occ_blocks::writebacks 26782.423909 # Average occupied blocks per requestor 652system.cpu.l2cache.tags.occ_blocks::cpu.inst 1431.670582 # Average occupied blocks per requestor 653system.cpu.l2cache.tags.occ_blocks::cpu.data 1657.323564 # Average occupied blocks per requestor 654system.cpu.l2cache.tags.occ_percent::writebacks 0.817335 # Average percentage of cache occupancy 655system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043691 # Average percentage of cache occupancy 656system.cpu.l2cache.tags.occ_percent::cpu.data 0.050578 # Average percentage of cache occupancy 657system.cpu.l2cache.tags.occ_percent::total 0.911603 # Average percentage of cache occupancy | 654system.cpu.l2cache.tags.occ_blocks::writebacks 26781.739932 # Average occupied blocks per requestor 655system.cpu.l2cache.tags.occ_blocks::cpu.inst 1431.627084 # Average occupied blocks per requestor 656system.cpu.l2cache.tags.occ_blocks::cpu.data 1658.189777 # Average occupied blocks per requestor 657system.cpu.l2cache.tags.occ_percent::writebacks 0.817314 # Average percentage of cache occupancy 658system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043690 # Average percentage of cache occupancy 659system.cpu.l2cache.tags.occ_percent::cpu.data 0.050604 # Average percentage of cache occupancy 660system.cpu.l2cache.tags.occ_percent::total 0.911608 # Average percentage of cache occupancy |
| 658system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id | 661system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id |
| 659system.cpu.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 660system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1851 # Occupied blocks per task id 661system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12724 # Occupied blocks per task id 662system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15788 # Occupied blocks per task id 663system.cpu.l2cache.tags.age_task_id_blocks_1024::4 593 # Occupied blocks per task id | 662system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 663system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1857 # Occupied blocks per task id 664system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12727 # Occupied blocks per task id 665system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15784 # Occupied blocks per task id 666system.cpu.l2cache.tags.age_task_id_blocks_1024::4 594 # Occupied blocks per task id |
| 664system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id | 667system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id |
| 665system.cpu.l2cache.tags.tag_accesses 3410031 # Number of tag accesses 666system.cpu.l2cache.tags.data_accesses 3410031 # Number of data accesses 667system.cpu.l2cache.WritebackDirty_hits::writebacks 128377 # number of WritebackDirty hits 668system.cpu.l2cache.WritebackDirty_hits::total 128377 # number of WritebackDirty hits 669system.cpu.l2cache.WritebackClean_hits::writebacks 39288 # number of WritebackClean hits 670system.cpu.l2cache.WritebackClean_hits::total 39288 # number of WritebackClean hits 671system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits 672system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits 673system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 40441 # number of ReadCleanReq hits 674system.cpu.l2cache.ReadCleanReq_hits::total 40441 # number of ReadCleanReq hits 675system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31897 # number of ReadSharedReq hits 676system.cpu.l2cache.ReadSharedReq_hits::total 31897 # number of ReadSharedReq hits 677system.cpu.l2cache.demand_hits::cpu.inst 40441 # number of demand (read+write) hits 678system.cpu.l2cache.demand_hits::cpu.data 36648 # number of demand (read+write) hits 679system.cpu.l2cache.demand_hits::total 77089 # number of demand (read+write) hits 680system.cpu.l2cache.overall_hits::cpu.inst 40441 # number of overall hits 681system.cpu.l2cache.overall_hits::cpu.data 36648 # number of overall hits 682system.cpu.l2cache.overall_hits::total 77089 # number of overall hits 683system.cpu.l2cache.ReadExReq_misses::cpu.data 102277 # number of ReadExReq misses 684system.cpu.l2cache.ReadExReq_misses::total 102277 # number of ReadExReq misses | 668system.cpu.l2cache.tags.tag_accesses 3410152 # Number of tag accesses 669system.cpu.l2cache.tags.data_accesses 3410152 # Number of data accesses 670system.cpu.l2cache.WritebackDirty_hits::writebacks 128384 # number of WritebackDirty hits 671system.cpu.l2cache.WritebackDirty_hits::total 128384 # number of WritebackDirty hits 672system.cpu.l2cache.WritebackClean_hits::writebacks 39291 # number of WritebackClean hits 673system.cpu.l2cache.WritebackClean_hits::total 39291 # number of WritebackClean hits 674system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits 675system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits 676system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 40444 # number of ReadCleanReq hits 677system.cpu.l2cache.ReadCleanReq_hits::total 40444 # number of ReadCleanReq hits 678system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31900 # number of ReadSharedReq hits 679system.cpu.l2cache.ReadSharedReq_hits::total 31900 # number of ReadSharedReq hits 680system.cpu.l2cache.demand_hits::cpu.inst 40444 # number of demand (read+write) hits 681system.cpu.l2cache.demand_hits::cpu.data 36652 # number of demand (read+write) hits 682system.cpu.l2cache.demand_hits::total 77096 # number of demand (read+write) hits 683system.cpu.l2cache.overall_hits::cpu.inst 40444 # number of overall hits 684system.cpu.l2cache.overall_hits::cpu.data 36652 # number of overall hits 685system.cpu.l2cache.overall_hits::total 77096 # number of overall hits 686system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses 687system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses |
| 685system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4470 # number of ReadCleanReq misses 686system.cpu.l2cache.ReadCleanReq_misses::total 4470 # number of ReadCleanReq misses | 688system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4470 # number of ReadCleanReq misses 689system.cpu.l2cache.ReadCleanReq_misses::total 4470 # number of ReadCleanReq misses |
| 687system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21607 # number of ReadSharedReq misses 688system.cpu.l2cache.ReadSharedReq_misses::total 21607 # number of ReadSharedReq misses | 690system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21609 # number of ReadSharedReq misses 691system.cpu.l2cache.ReadSharedReq_misses::total 21609 # number of ReadSharedReq misses |
| 689system.cpu.l2cache.demand_misses::cpu.inst 4470 # number of demand (read+write) misses | 692system.cpu.l2cache.demand_misses::cpu.inst 4470 # number of demand (read+write) misses |
| 690system.cpu.l2cache.demand_misses::cpu.data 123884 # number of demand (read+write) misses 691system.cpu.l2cache.demand_misses::total 128354 # number of demand (read+write) misses | 693system.cpu.l2cache.demand_misses::cpu.data 123885 # number of demand (read+write) misses 694system.cpu.l2cache.demand_misses::total 128355 # number of demand (read+write) misses |
| 692system.cpu.l2cache.overall_misses::cpu.inst 4470 # number of overall misses | 695system.cpu.l2cache.overall_misses::cpu.inst 4470 # number of overall misses |
| 693system.cpu.l2cache.overall_misses::cpu.data 123884 # number of overall misses 694system.cpu.l2cache.overall_misses::total 128354 # number of overall misses 695system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8277973500 # number of ReadExReq miss cycles 696system.cpu.l2cache.ReadExReq_miss_latency::total 8277973500 # number of ReadExReq miss cycles 697system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 355961000 # number of ReadCleanReq miss cycles 698system.cpu.l2cache.ReadCleanReq_miss_latency::total 355961000 # number of ReadCleanReq miss cycles 699system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1870485000 # number of ReadSharedReq miss cycles 700system.cpu.l2cache.ReadSharedReq_miss_latency::total 1870485000 # number of ReadSharedReq miss cycles 701system.cpu.l2cache.demand_miss_latency::cpu.inst 355961000 # number of demand (read+write) miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.data 10148458500 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::total 10504419500 # number of demand (read+write) miss cycles 704system.cpu.l2cache.overall_miss_latency::cpu.inst 355961000 # number of overall miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.data 10148458500 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::total 10504419500 # number of overall miss cycles 707system.cpu.l2cache.WritebackDirty_accesses::writebacks 128377 # number of WritebackDirty accesses(hits+misses) 708system.cpu.l2cache.WritebackDirty_accesses::total 128377 # number of WritebackDirty accesses(hits+misses) 709system.cpu.l2cache.WritebackClean_accesses::writebacks 39288 # number of WritebackClean accesses(hits+misses) 710system.cpu.l2cache.WritebackClean_accesses::total 39288 # number of WritebackClean accesses(hits+misses) | 696system.cpu.l2cache.overall_misses::cpu.data 123885 # number of overall misses 697system.cpu.l2cache.overall_misses::total 128355 # number of overall misses 698system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8270346500 # number of ReadExReq miss cycles 699system.cpu.l2cache.ReadExReq_miss_latency::total 8270346500 # number of ReadExReq miss cycles 700system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356128000 # number of ReadCleanReq miss cycles 701system.cpu.l2cache.ReadCleanReq_miss_latency::total 356128000 # number of ReadCleanReq miss cycles 702system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1869505500 # number of ReadSharedReq miss cycles 703system.cpu.l2cache.ReadSharedReq_miss_latency::total 1869505500 # number of ReadSharedReq miss cycles 704system.cpu.l2cache.demand_miss_latency::cpu.inst 356128000 # number of demand (read+write) miss cycles 705system.cpu.l2cache.demand_miss_latency::cpu.data 10139852000 # number of demand (read+write) miss cycles 706system.cpu.l2cache.demand_miss_latency::total 10495980000 # number of demand (read+write) miss cycles 707system.cpu.l2cache.overall_miss_latency::cpu.inst 356128000 # number of overall miss cycles 708system.cpu.l2cache.overall_miss_latency::cpu.data 10139852000 # number of overall miss cycles 709system.cpu.l2cache.overall_miss_latency::total 10495980000 # number of overall miss cycles 710system.cpu.l2cache.WritebackDirty_accesses::writebacks 128384 # number of WritebackDirty accesses(hits+misses) 711system.cpu.l2cache.WritebackDirty_accesses::total 128384 # number of WritebackDirty accesses(hits+misses) 712system.cpu.l2cache.WritebackClean_accesses::writebacks 39291 # number of WritebackClean accesses(hits+misses) 713system.cpu.l2cache.WritebackClean_accesses::total 39291 # number of WritebackClean accesses(hits+misses) |
| 711system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) 712system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) | 714system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) 715system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) |
| 713system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44911 # number of ReadCleanReq accesses(hits+misses) 714system.cpu.l2cache.ReadCleanReq_accesses::total 44911 # number of ReadCleanReq accesses(hits+misses) 715system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53504 # number of ReadSharedReq accesses(hits+misses) 716system.cpu.l2cache.ReadSharedReq_accesses::total 53504 # number of ReadSharedReq accesses(hits+misses) 717system.cpu.l2cache.demand_accesses::cpu.inst 44911 # number of demand (read+write) accesses 718system.cpu.l2cache.demand_accesses::cpu.data 160532 # number of demand (read+write) accesses 719system.cpu.l2cache.demand_accesses::total 205443 # number of demand (read+write) accesses 720system.cpu.l2cache.overall_accesses::cpu.inst 44911 # number of overall (read+write) accesses 721system.cpu.l2cache.overall_accesses::cpu.data 160532 # number of overall (read+write) accesses 722system.cpu.l2cache.overall_accesses::total 205443 # number of overall (read+write) accesses 723system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955610 # miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_miss_rate::total 0.955610 # miss rate for ReadExReq accesses 725system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.099530 # miss rate for ReadCleanReq accesses 726system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.099530 # miss rate for ReadCleanReq accesses | 716system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44914 # number of ReadCleanReq accesses(hits+misses) 717system.cpu.l2cache.ReadCleanReq_accesses::total 44914 # number of ReadCleanReq accesses(hits+misses) 718system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53509 # number of ReadSharedReq accesses(hits+misses) 719system.cpu.l2cache.ReadSharedReq_accesses::total 53509 # number of ReadSharedReq accesses(hits+misses) 720system.cpu.l2cache.demand_accesses::cpu.inst 44914 # number of demand (read+write) accesses 721system.cpu.l2cache.demand_accesses::cpu.data 160537 # number of demand (read+write) accesses 722system.cpu.l2cache.demand_accesses::total 205451 # number of demand (read+write) accesses 723system.cpu.l2cache.overall_accesses::cpu.inst 44914 # number of overall (read+write) accesses 724system.cpu.l2cache.overall_accesses::cpu.data 160537 # number of overall (read+write) accesses 725system.cpu.l2cache.overall_accesses::total 205451 # number of overall (read+write) accesses 726system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses 727system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses 728system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.099524 # miss rate for ReadCleanReq accesses 729system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.099524 # miss rate for ReadCleanReq accesses |
| 727system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403839 # miss rate for ReadSharedReq accesses 728system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403839 # miss rate for ReadSharedReq accesses | 730system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403839 # miss rate for ReadSharedReq accesses 731system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403839 # miss rate for ReadSharedReq accesses |
| 729system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099530 # miss rate for demand accesses 730system.cpu.l2cache.demand_miss_rate::cpu.data 0.771709 # miss rate for demand accesses 731system.cpu.l2cache.demand_miss_rate::total 0.624767 # miss rate for demand accesses 732system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099530 # miss rate for overall accesses 733system.cpu.l2cache.overall_miss_rate::cpu.data 0.771709 # miss rate for overall accesses 734system.cpu.l2cache.overall_miss_rate::total 0.624767 # miss rate for overall accesses 735system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80936.803974 # average ReadExReq miss latency 736system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80936.803974 # average ReadExReq miss latency 737system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79633.333333 # average ReadCleanReq miss latency 738system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79633.333333 # average ReadCleanReq miss latency 739system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86568.473180 # average ReadSharedReq miss latency 740system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86568.473180 # average ReadSharedReq miss latency 741system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency 742system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency 743system.cpu.l2cache.demand_avg_miss_latency::total 81839.440142 # average overall miss latency 744system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency 745system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency 746system.cpu.l2cache.overall_avg_miss_latency::total 81839.440142 # average overall miss latency | 732system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099524 # miss rate for demand accesses 733system.cpu.l2cache.demand_miss_rate::cpu.data 0.771691 # miss rate for demand accesses 734system.cpu.l2cache.demand_miss_rate::total 0.624748 # miss rate for demand accesses 735system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099524 # miss rate for overall accesses 736system.cpu.l2cache.overall_miss_rate::cpu.data 0.771691 # miss rate for overall accesses 737system.cpu.l2cache.overall_miss_rate::total 0.624748 # miss rate for overall accesses 738system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80863.022605 # average ReadExReq miss latency 739system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80863.022605 # average ReadExReq miss latency 740system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79670.693512 # average ReadCleanReq miss latency 741system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79670.693512 # average ReadCleanReq miss latency 742system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86515.132584 # average ReadSharedReq miss latency 743system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86515.132584 # average ReadSharedReq miss latency 744system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79670.693512 # average overall miss latency 745system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81848.908262 # average overall miss latency 746system.cpu.l2cache.demand_avg_miss_latency::total 81773.051303 # average overall miss latency 747system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79670.693512 # average overall miss latency 748system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81848.908262 # average overall miss latency 749system.cpu.l2cache.overall_avg_miss_latency::total 81773.051303 # average overall miss latency |
| 747system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 748system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 749system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 750system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 751system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 752system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 753system.cpu.l2cache.fast_writes 0 # number of fast writes performed 754system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 761system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits 762system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits 763system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits 764system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits 765system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits 766system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits 767system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 768system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses | 750system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu.l2cache.fast_writes 0 # number of fast writes performed 757system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 764system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits 765system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits 766system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits 767system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits 768system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits 769system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits 770system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 771system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses |
| 769system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102277 # number of ReadExReq MSHR misses 770system.cpu.l2cache.ReadExReq_mshr_misses::total 102277 # number of ReadExReq MSHR misses | 772system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102276 # number of ReadExReq MSHR misses 773system.cpu.l2cache.ReadExReq_mshr_misses::total 102276 # number of ReadExReq MSHR misses |
| 771system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4457 # number of ReadCleanReq MSHR misses 772system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4457 # number of ReadCleanReq MSHR misses | 774system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4457 # number of ReadCleanReq MSHR misses 775system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4457 # number of ReadCleanReq MSHR misses |
| 773system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21545 # number of ReadSharedReq MSHR misses 774system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21545 # number of ReadSharedReq MSHR misses | 776system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21547 # number of ReadSharedReq MSHR misses 777system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21547 # number of ReadSharedReq MSHR misses |
| 775system.cpu.l2cache.demand_mshr_misses::cpu.inst 4457 # number of demand (read+write) MSHR misses | 778system.cpu.l2cache.demand_mshr_misses::cpu.inst 4457 # number of demand (read+write) MSHR misses |
| 776system.cpu.l2cache.demand_mshr_misses::cpu.data 123822 # number of demand (read+write) MSHR misses 777system.cpu.l2cache.demand_mshr_misses::total 128279 # number of demand (read+write) MSHR misses | 779system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses 780system.cpu.l2cache.demand_mshr_misses::total 128280 # number of demand (read+write) MSHR misses |
| 778system.cpu.l2cache.overall_mshr_misses::cpu.inst 4457 # number of overall MSHR misses | 781system.cpu.l2cache.overall_mshr_misses::cpu.inst 4457 # number of overall MSHR misses |
| 779system.cpu.l2cache.overall_mshr_misses::cpu.data 123822 # number of overall MSHR misses 780system.cpu.l2cache.overall_mshr_misses::total 128279 # number of overall MSHR misses 781system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7255203500 # number of ReadExReq MSHR miss cycles 782system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7255203500 # number of ReadExReq MSHR miss cycles 783system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310493500 # number of ReadCleanReq MSHR miss cycles 784system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310493500 # number of ReadCleanReq MSHR miss cycles 785system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649955000 # number of ReadSharedReq MSHR miss cycles 786system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649955000 # number of ReadSharedReq MSHR miss cycles 787system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310493500 # number of demand (read+write) MSHR miss cycles 788system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8905158500 # number of demand (read+write) MSHR miss cycles 789system.cpu.l2cache.demand_mshr_miss_latency::total 9215652000 # number of demand (read+write) MSHR miss cycles 790system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310493500 # number of overall MSHR miss cycles 791system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8905158500 # number of overall MSHR miss cycles 792system.cpu.l2cache.overall_mshr_miss_latency::total 9215652000 # number of overall MSHR miss cycles | 782system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses 783system.cpu.l2cache.overall_mshr_misses::total 128280 # number of overall MSHR misses 784system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7247586500 # number of ReadExReq MSHR miss cycles 785system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7247586500 # number of ReadExReq MSHR miss cycles 786system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310540000 # number of ReadCleanReq MSHR miss cycles 787system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310540000 # number of ReadCleanReq MSHR miss cycles 788system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649696000 # number of ReadSharedReq MSHR miss cycles 789system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649696000 # number of ReadSharedReq MSHR miss cycles 790system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310540000 # number of demand (read+write) MSHR miss cycles 791system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8897282500 # number of demand (read+write) MSHR miss cycles 792system.cpu.l2cache.demand_mshr_miss_latency::total 9207822500 # number of demand (read+write) MSHR miss cycles 793system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310540000 # number of overall MSHR miss cycles 794system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8897282500 # number of overall MSHR miss cycles 795system.cpu.l2cache.overall_mshr_miss_latency::total 9207822500 # number of overall MSHR miss cycles |
| 793system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 794system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 796system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 797system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 795system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955610 # mshr miss rate for ReadExReq accesses 796system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955610 # mshr miss rate for ReadExReq accesses 797system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for ReadCleanReq accesses 798system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099241 # mshr miss rate for ReadCleanReq accesses | 798system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses 799system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses 800system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for ReadCleanReq accesses 801system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099234 # mshr miss rate for ReadCleanReq accesses |
| 799system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402680 # mshr miss rate for ReadSharedReq accesses 800system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402680 # mshr miss rate for ReadSharedReq accesses | 802system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402680 # mshr miss rate for ReadSharedReq accesses 803system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402680 # mshr miss rate for ReadSharedReq accesses |
| 801system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for demand accesses 802system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for demand accesses 803system.cpu.l2cache.demand_mshr_miss_rate::total 0.624402 # mshr miss rate for demand accesses 804system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for overall accesses 805system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for overall accesses 806system.cpu.l2cache.overall_mshr_miss_rate::total 0.624402 # mshr miss rate for overall accesses 807system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70936.803974 # average ReadExReq mshr miss latency 808system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70936.803974 # average ReadExReq mshr miss latency 809system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69664.236033 # average ReadCleanReq mshr miss latency 810system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69664.236033 # average ReadCleanReq mshr miss latency 811system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76581.805523 # average ReadSharedReq mshr miss latency 812system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76581.805523 # average ReadSharedReq mshr miss latency 813system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency 814system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency 815system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency 816system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency 817system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency 818system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency | 804system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for demand accesses 805system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771305 # mshr miss rate for demand accesses 806system.cpu.l2cache.demand_mshr_miss_rate::total 0.624382 # mshr miss rate for demand accesses 807system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for overall accesses 808system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771305 # mshr miss rate for overall accesses 809system.cpu.l2cache.overall_mshr_miss_rate::total 0.624382 # mshr miss rate for overall accesses 810system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70863.022605 # average ReadExReq mshr miss latency 811system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70863.022605 # average ReadExReq mshr miss latency 812system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69674.669060 # average ReadCleanReq mshr miss latency 813system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69674.669060 # average ReadCleanReq mshr miss latency 814system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76562.676939 # average ReadSharedReq mshr miss latency 815system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76562.676939 # average ReadSharedReq mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69674.669060 # average overall mshr miss latency 817system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71854.845223 # average overall mshr miss latency 818system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71779.096508 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69674.669060 # average overall mshr miss latency 820system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71854.845223 # average overall mshr miss latency 821system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71779.096508 # average overall mshr miss latency |
| 819system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 822system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 820system.cpu.toL2Bus.snoop_filter.tot_requests 404747 # Total number of requests made to the snoop filter. 821system.cpu.toL2Bus.snoop_filter.hit_single_requests 199340 # Number of requests hitting in the snoop filter with a single holder of the requested data. 822system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 823system.cpu.toL2Bus.snoop_filter.tot_requests 404763 # Total number of requests made to the snoop filter. 824system.cpu.toL2Bus.snoop_filter.hit_single_requests 199348 # Number of requests hitting in the snoop filter with a single holder of the requested data. 825system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7815 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 823system.cpu.toL2Bus.snoop_filter.tot_snoops 3362 # Total number of snoops made to the snoop filter. 824system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 825system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 826system.cpu.toL2Bus.snoop_filter.tot_snoops 3362 # Total number of snoops made to the snoop filter. 827system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 828system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 826system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution 827system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution 828system.cpu.toL2Bus.trans_dist::WritebackClean 42868 # Transaction distribution 829system.cpu.toL2Bus.trans_dist::CleanEvict 38234 # Transaction distribution | 829system.cpu.toL2Bus.trans_dist::ReadResp 98422 # Transaction distribution 830system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution 831system.cpu.toL2Bus.trans_dist::WritebackClean 42871 # Transaction distribution 832system.cpu.toL2Bus.trans_dist::CleanEvict 38233 # Transaction distribution |
| 830system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution 831system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution | 833system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution 834system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution |
| 832system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution 833system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution 834system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132689 # Packet count per connected master and slave (bytes) 835system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477500 # Packet count per connected master and slave (bytes) 836system.cpu.toL2Bus.pkt_count::total 610189 # Packet count per connected master and slave (bytes) 837system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5617792 # Cumulative packet size per connected master and slave (bytes) 838system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes) 839system.cpu.toL2Bus.pkt_size::total 24107968 # Cumulative packet size per connected master and slave (bytes) 840system.cpu.toL2Bus.snoops 96386 # Total snoops (count) 841system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram 842system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram 843system.cpu.toL2Bus.snoop_fanout::stdev 0.189864 # Request fanout histogram | 835system.cpu.toL2Bus.trans_dist::ReadCleanReq 44914 # Transaction distribution 836system.cpu.toL2Bus.trans_dist::ReadSharedReq 53509 # Transaction distribution 837system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132698 # Packet count per connected master and slave (bytes) 838system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477515 # Packet count per connected master and slave (bytes) 839system.cpu.toL2Bus.pkt_count::total 610213 # Packet count per connected master and slave (bytes) 840system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5618176 # Cumulative packet size per connected master and slave (bytes) 841system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490944 # Cumulative packet size per connected master and slave (bytes) 842system.cpu.toL2Bus.pkt_size::total 24109120 # Cumulative packet size per connected master and slave (bytes) 843system.cpu.toL2Bus.snoops 96387 # Total snoops (count) 844system.cpu.toL2Bus.snoop_fanout::samples 301838 # Request fanout histogram 845system.cpu.toL2Bus.snoop_fanout::mean 0.037245 # Request fanout histogram 846system.cpu.toL2Bus.snoop_fanout::stdev 0.189869 # Request fanout histogram |
| 844system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 847system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 845system.cpu.toL2Bus.snoop_fanout::0 290617 96.29% 96.29% # Request fanout histogram 846system.cpu.toL2Bus.snoop_fanout::1 11183 3.71% 99.99% # Request fanout histogram | 848system.cpu.toL2Bus.snoop_fanout::0 290625 96.29% 96.29% # Request fanout histogram 849system.cpu.toL2Bus.snoop_fanout::1 11184 3.71% 99.99% # Request fanout histogram |
| 847system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram 848system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 849system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 850system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 850system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram 851system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 852system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 853system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 851system.cpu.toL2Bus.snoop_fanout::total 301829 # Request fanout histogram 852system.cpu.toL2Bus.reqLayer0.occupancy 373618500 # Layer occupancy (ticks) | 854system.cpu.toL2Bus.snoop_fanout::total 301838 # Request fanout histogram 855system.cpu.toL2Bus.reqLayer0.occupancy 373636500 # Layer occupancy (ticks) |
| 853system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) | 856system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| 854system.cpu.toL2Bus.respLayer0.occupancy 67384461 # Layer occupancy (ticks) | 857system.cpu.toL2Bus.respLayer0.occupancy 67388961 # Layer occupancy (ticks) |
| 855system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 858system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 856system.cpu.toL2Bus.respLayer1.occupancy 240832431 # Layer occupancy (ticks) | 859system.cpu.toL2Bus.respLayer1.occupancy 240839931 # Layer occupancy (ticks) |
| 857system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) | 860system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 858system.membus.trans_dist::ReadResp 26001 # Transaction distribution | 861system.membus.trans_dist::ReadResp 26003 # Transaction distribution |
| 859system.membus.trans_dist::WritebackDirty 86211 # Transaction distribution | 862system.membus.trans_dist::WritebackDirty 86211 # Transaction distribution |
| 860system.membus.trans_dist::CleanEvict 6908 # Transaction distribution 861system.membus.trans_dist::ReadExReq 102277 # Transaction distribution 862system.membus.trans_dist::ReadExResp 102277 # Transaction distribution 863system.membus.trans_dist::ReadSharedReq 26001 # Transaction distribution 864system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349675 # Packet count per connected master and slave (bytes) 865system.membus.pkt_count::total 349675 # Packet count per connected master and slave (bytes) 866system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727296 # Cumulative packet size per connected master and slave (bytes) 867system.membus.pkt_size::total 13727296 # Cumulative packet size per connected master and slave (bytes) | 863system.membus.trans_dist::CleanEvict 6909 # Transaction distribution 864system.membus.trans_dist::ReadExReq 102276 # Transaction distribution 865system.membus.trans_dist::ReadExResp 102276 # Transaction distribution 866system.membus.trans_dist::ReadSharedReq 26003 # Transaction distribution 867system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349678 # Packet count per connected master and slave (bytes) 868system.membus.pkt_count::total 349678 # Packet count per connected master and slave (bytes) 869system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727360 # Cumulative packet size per connected master and slave (bytes) 870system.membus.pkt_size::total 13727360 # Cumulative packet size per connected master and slave (bytes) |
| 868system.membus.snoops 0 # Total snoops (count) | 871system.membus.snoops 0 # Total snoops (count) |
| 869system.membus.snoop_fanout::samples 221397 # Request fanout histogram | 872system.membus.snoop_fanout::samples 221399 # Request fanout histogram |
| 870system.membus.snoop_fanout::mean 0 # Request fanout histogram 871system.membus.snoop_fanout::stdev 0 # Request fanout histogram 872system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 873system.membus.snoop_fanout::mean 0 # Request fanout histogram 874system.membus.snoop_fanout::stdev 0 # Request fanout histogram 875system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 873system.membus.snoop_fanout::0 221397 100.00% 100.00% # Request fanout histogram | 876system.membus.snoop_fanout::0 221399 100.00% 100.00% # Request fanout histogram |
| 874system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 875system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 876system.membus.snoop_fanout::min_value 0 # Request fanout histogram 877system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 877system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 878system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 879system.membus.snoop_fanout::min_value 0 # Request fanout histogram 880system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 878system.membus.snoop_fanout::total 221397 # Request fanout histogram 879system.membus.reqLayer0.occupancy 590585500 # Layer occupancy (ticks) | 881system.membus.snoop_fanout::total 221399 # Request fanout histogram 882system.membus.reqLayer0.occupancy 590619000 # Layer occupancy (ticks) |
| 880system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) | 883system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| 881system.membus.respLayer1.occupancy 676907000 # Layer occupancy (ticks) | 884system.membus.respLayer1.occupancy 676896750 # Layer occupancy (ticks) |
| 882system.membus.respLayer1.utilization 1.2 # Layer utilization (%) 883 884---------- End Simulation Statistics ---------- | 885system.membus.respLayer1.utilization 1.2 # Layer utilization (%) 886 887---------- End Simulation Statistics ---------- |