| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.056986 # Number of seconds simulated 4sim_ticks 56986224500 # Number of ticks simulated 5final_tick 56986224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.056991 # Number of seconds simulated 4sim_ticks 56991022500 # Number of ticks simulated 5final_tick 56991022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 135704 # Simulator instruction rate (inst/s) 8host_op_rate 173546 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 109049636 # Simulator tick rate (ticks/s) 10host_mem_usage 317176 # Number of bytes of host memory used 11host_seconds 522.57 # Real time elapsed on the host | 7host_inst_rate 186679 # Simulator instruction rate (inst/s) 8host_op_rate 238735 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 150024942 # Simulator tick rate (ticks/s) 10host_mem_usage 325676 # Number of bytes of host memory used 11host_seconds 379.88 # Real time elapsed on the host |
| 12sim_insts 70915128 # Number of instructions simulated 13sim_ops 90690084 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 318720 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7923904 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8242624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 318720 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 318720 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5514048 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5514048 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4980 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123811 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory | 12sim_insts 70915128 # Number of instructions simulated 13sim_ops 90690084 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 318720 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7923904 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8242624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 318720 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 318720 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5514048 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5514048 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4980 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123811 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory |
| 28system.physmem.bw_read::cpu.inst 5592931 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 139049464 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 144642395 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 5592931 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 5592931 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 96761069 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 96761069 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 96761069 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 5592931 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 139049464 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 241403464 # Total bandwidth to/from this memory (bytes/s) | 28system.physmem.bw_read::cpu.inst 5592460 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 139037758 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 144630218 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 5592460 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 5592460 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 96752923 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 96752923 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 96752923 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 5592460 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 139037758 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 241383141 # Total bandwidth to/from this memory (bytes/s) |
| 39system.physmem.readReqs 128791 # Number of read requests accepted 40system.physmem.writeReqs 86157 # Number of write requests accepted 41system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue | 39system.physmem.readReqs 128791 # Number of read requests accepted 40system.physmem.writeReqs 86157 # Number of write requests accepted 41system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue |
| 45system.physmem.bytesWritten 5512000 # Total number of bytes written to DRAM | 45system.physmem.bytesWritten 5512640 # Total number of bytes written to DRAM |
| 46system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8144 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8370 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8248 # Per bank write bursts --- 7 unchanged lines hidden (view full) --- 61system.physmem.perBankRdBursts::10 7815 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7829 # Per bank write bursts 63system.physmem.perBankRdBursts::12 7881 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7878 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7975 # Per bank write bursts 66system.physmem.perBankRdBursts::15 7995 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5393 # Per bank write bursts 68system.physmem.perBankWrBursts::1 5541 # Per bank write bursts | 46system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8144 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8370 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8248 # Per bank write bursts --- 7 unchanged lines hidden (view full) --- 61system.physmem.perBankRdBursts::10 7815 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7829 # Per bank write bursts 63system.physmem.perBankRdBursts::12 7881 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7878 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7975 # Per bank write bursts 66system.physmem.perBankRdBursts::15 7995 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5393 # Per bank write bursts 68system.physmem.perBankWrBursts::1 5541 # Per bank write bursts |
| 69system.physmem.perBankWrBursts::2 5463 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5328 # Per bank write bursts | 69system.physmem.perBankWrBursts::2 5464 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5326 # Per bank write bursts |
| 71system.physmem.perBankWrBursts::4 5352 # Per bank write bursts | 71system.physmem.perBankWrBursts::4 5352 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::5 5545 # Per bank write bursts 73system.physmem.perBankWrBursts::6 5246 # Per bank write bursts | 72system.physmem.perBankWrBursts::5 5547 # Per bank write bursts 73system.physmem.perBankWrBursts::6 5252 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::7 5180 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5155 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5101 # Per bank write bursts | 74system.physmem.perBankWrBursts::7 5180 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5155 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5101 # Per bank write bursts |
| 77system.physmem.perBankWrBursts::10 5289 # Per bank write bursts | 77system.physmem.perBankWrBursts::10 5292 # Per bank write bursts |
| 78system.physmem.perBankWrBursts::11 5270 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5531 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5597 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5703 # Per bank write bursts 82system.physmem.perBankWrBursts::15 5431 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 78system.physmem.perBankWrBursts::11 5270 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5531 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5597 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5703 # Per bank write bursts 82system.physmem.perBankWrBursts::15 5431 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 56986193500 # Total gap between requests | 85system.physmem.totGap 56990990500 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 128791 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 86157 # Write request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 128791 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 86157 # Write request sizes (log2) |
| 100system.physmem.rdQLenPdf::0 116559 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 12202 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::0 116650 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 12110 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 656 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4080 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5286 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5311 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5306 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5318 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5318 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5323 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5350 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5376 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5428 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5451 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5897 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5469 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 649 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4071 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5170 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5285 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5306 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5310 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5310 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5336 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5367 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5452 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5431 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5478 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5464 # What write queue length does an incoming req see |
| 164system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see | 164system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see |
| 165system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see | 165system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see |
| 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 38656 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 355.735099 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 216.399320 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 335.915140 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12161 31.46% 31.46% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 8166 21.12% 52.58% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 4096 10.60% 63.18% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2818 7.29% 70.47% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2687 6.95% 77.42% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1672 4.33% 81.75% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1300 3.36% 85.11% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1153 2.98% 88.09% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 4603 11.91% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 38656 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5291 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 24.313362 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 352.121472 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5289 99.96% 99.96% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 38662 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 355.683203 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 216.343519 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 336.125731 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12148 31.42% 31.42% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 8177 21.15% 52.57% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 4090 10.58% 63.15% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2852 7.38% 70.53% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2693 6.97% 77.49% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1623 4.20% 81.69% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1296 3.35% 85.04% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1161 3.00% 88.05% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 4622 11.95% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 38662 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 24.322124 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 352.056892 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes | 214system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::total 5291 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5291 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 16.277641 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 16.260577 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.779844 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 4640 87.70% 87.70% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 6 0.11% 87.81% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 513 9.70% 97.51% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 107 2.02% 99.53% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 18 0.34% 99.87% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 4 0.08% 99.94% # Writes before turning the bus around for reads | 216system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 16.273380 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 16.256688 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.768255 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 4654 87.93% 87.93% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 4 0.08% 88.00% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 500 9.45% 97.45% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 109 2.06% 99.51% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 18 0.34% 99.85% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 5 0.09% 99.94% # Writes before turning the bus around for reads |
| 227system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads | 227system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads |
| 228system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 5291 # Writes before turning the bus around for reads 230system.physmem.totQLat 1688662500 # Total ticks spent queuing 231system.physmem.totMemAccLat 4103362500 # Total ticks spent from burst creation until serviced by the DRAM | 228system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads 230system.physmem.totQLat 1683428000 # Total ticks spent queuing 231system.physmem.totMemAccLat 4098128000 # Total ticks spent from burst creation until serviced by the DRAM |
| 232system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers | 232system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers |
| 233system.physmem.avgQLat 13112.36 # Average queueing delay per DRAM burst | 233system.physmem.avgQLat 13071.72 # Average queueing delay per DRAM burst |
| 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 235system.physmem.avgMemAccLat 31862.36 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 144.63 # Average DRAM read bandwidth in MiByte/s | 235system.physmem.avgMemAccLat 31821.72 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 144.62 # Average DRAM read bandwidth in MiByte/s |
| 237system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s | 237system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s |
| 238system.physmem.avgRdBWSys 144.64 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s | 238system.physmem.avgRdBWSys 144.63 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 96.75 # Average system write bandwidth in MiByte/s |
| 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 241system.physmem.busUtil 1.89 # Data bus utilization in percentage 242system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes 244system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 241system.physmem.busUtil 1.89 # Data bus utilization in percentage 242system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes 244system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 245system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing 246system.physmem.readRowHits 112105 # Number of row buffer hits during reads 247system.physmem.writeRowHits 64137 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 74.44 # Row buffer hit rate for writes 250system.physmem.avgGap 265116.18 # Average gap between requests | 245system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing 246system.physmem.readRowHits 112096 # Number of row buffer hits during reads 247system.physmem.writeRowHits 64153 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 87.04 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 74.46 # Row buffer hit rate for writes 250system.physmem.avgGap 265138.50 # Average gap between requests |
| 251system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined | 251system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined |
| 252system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) 253system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) 254system.physmem_0.readEnergy 512194800 # Energy for read commands per rank (pJ) 255system.physmem_0.writeEnergy 278951040 # Energy for write commands per rank (pJ) 256system.physmem_0.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) 257system.physmem_0.actBackEnergy 11693696490 # Energy for active background per rank (pJ) 258system.physmem_0.preBackEnergy 23930394000 # Energy for precharge background per rank (pJ) 259system.physmem_0.totalEnergy 40371922185 # Total energy per rank (pJ) 260system.physmem_0.averagePower 708.527477 # Core power per rank (mW) 261system.physmem_0.memoryStateTime::IDLE 39682710000 # Time in different power states 262system.physmem_0.memoryStateTime::REF 1902680000 # Time in different power states | 252system.physmem_0.actEnergy 151963560 # Energy for activate commands per rank (pJ) 253system.physmem_0.preEnergy 82916625 # Energy for precharge commands per rank (pJ) 254system.physmem_0.readEnergy 512397600 # Energy for read commands per rank (pJ) 255system.physmem_0.writeEnergy 278957520 # Energy for write commands per rank (pJ) 256system.physmem_0.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) 257system.physmem_0.actBackEnergy 11726025750 # Energy for active background per rank (pJ) 258system.physmem_0.preBackEnergy 23906742000 # Energy for precharge background per rank (pJ) 259system.physmem_0.totalEnergy 40381153695 # Total energy per rank (pJ) 260system.physmem_0.averagePower 708.591931 # Core power per rank (mW) 261system.physmem_0.memoryStateTime::IDLE 39643767750 # Time in different power states 262system.physmem_0.memoryStateTime::REF 1902940000 # Time in different power states |
| 263system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 263system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 264system.physmem_0.memoryStateTime::ACT 15394661250 # Time in different power states | 264system.physmem_0.memoryStateTime::ACT 15441187500 # Time in different power states |
| 265system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 265system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 266system.physmem_1.actEnergy 140086800 # Energy for activate commands per rank (pJ) 267system.physmem_1.preEnergy 76436250 # Energy for precharge commands per rank (pJ) 268system.physmem_1.readEnergy 491673000 # Energy for read commands per rank (pJ) | 266system.physmem_1.actEnergy 140313600 # Energy for activate commands per rank (pJ) 267system.physmem_1.preEnergy 76560000 # Energy for precharge commands per rank (pJ) 268system.physmem_1.readEnergy 491751000 # Energy for read commands per rank (pJ) |
| 269system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) | 269system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) |
| 270system.physmem_1.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) 271system.physmem_1.actBackEnergy 11090732535 # Energy for active background per rank (pJ) 272system.physmem_1.preBackEnergy 24459309750 # Energy for precharge background per rank (pJ) 273system.physmem_1.totalEnergy 40259019375 # Total energy per rank (pJ) 274system.physmem_1.averagePower 706.546032 # Core power per rank (mW) 275system.physmem_1.memoryStateTime::IDLE 40563908250 # Time in different power states 276system.physmem_1.memoryStateTime::REF 1902680000 # Time in different power states | 270system.physmem_1.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) 271system.physmem_1.actBackEnergy 11059172775 # Energy for active background per rank (pJ) 272system.physmem_1.preBackEnergy 24491665500 # Energy for precharge background per rank (pJ) 273system.physmem_1.totalEnergy 40260752475 # Total energy per rank (pJ) 274system.physmem_1.averagePower 706.479908 # Core power per rank (mW) 275system.physmem_1.memoryStateTime::IDLE 40617302250 # Time in different power states 276system.physmem_1.memoryStateTime::REF 1902940000 # Time in different power states |
| 277system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 277system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 278system.physmem_1.memoryStateTime::ACT 14513554250 # Time in different power states | 278system.physmem_1.memoryStateTime::ACT 14467595250 # Time in different power states |
| 279system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 279system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 280system.cpu.branchPred.lookups 14800511 # Number of BP lookups 281system.cpu.branchPred.condPredicted 9905691 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 381680 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 9439152 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 6732150 # Number of BTB hits | 280system.cpu.branchPred.lookups 14800541 # Number of BP lookups 281system.cpu.branchPred.condPredicted 9905717 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 381681 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 9438549 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 6732145 # Number of BTB hits |
| 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 286system.cpu.branchPred.BTBHitPct 71.321555 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 1714112 # Number of times the RAS was used to get a target. | 286system.cpu.branchPred.BTBHitPct 71.326059 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 1714124 # Number of times the RAS was used to get a target. |
| 288system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. 289system.cpu_clk_domain.clock 500 # Clock period in ticks 290system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 399system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.itb.read_accesses 0 # DTB read accesses 401system.cpu.itb.write_accesses 0 # DTB write accesses 402system.cpu.itb.inst_accesses 0 # ITB inst accesses 403system.cpu.itb.hits 0 # DTB hits 404system.cpu.itb.misses 0 # DTB misses 405system.cpu.itb.accesses 0 # DTB accesses 406system.cpu.workload.num_syscalls 1946 # Number of system calls | 288system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. 289system.cpu_clk_domain.clock 500 # Clock period in ticks 290system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 399system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.itb.read_accesses 0 # DTB read accesses 401system.cpu.itb.write_accesses 0 # DTB write accesses 402system.cpu.itb.inst_accesses 0 # ITB inst accesses 403system.cpu.itb.hits 0 # DTB hits 404system.cpu.itb.misses 0 # DTB misses 405system.cpu.itb.accesses 0 # DTB accesses 406system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 407system.cpu.numCycles 113972449 # number of cpu cycles simulated | 407system.cpu.numCycles 113982045 # number of cpu cycles simulated |
| 408system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 409system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 410system.cpu.committedInsts 70915128 # Number of instructions committed 411system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed | 408system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 409system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 410system.cpu.committedInsts 70915128 # Number of instructions committed 411system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed |
| 412system.cpu.discardedOps 1144886 # Number of ops (including micro ops) which were discarded before commit | 412system.cpu.discardedOps 1144890 # Number of ops (including micro ops) which were discarded before commit |
| 413system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 413system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 414system.cpu.cpi 1.607167 # CPI: cycles per instruction 415system.cpu.ipc 0.622213 # IPC: instructions per cycle 416system.cpu.tickCycles 95596263 # Number of cycles that the object actually ticked 417system.cpu.idleCycles 18376186 # Total number of cycles that the object has spent stopped | 414system.cpu.cpi 1.607302 # CPI: cycles per instruction 415system.cpu.ipc 0.622161 # IPC: instructions per cycle 416system.cpu.tickCycles 95587829 # Number of cycles that the object actually ticked 417system.cpu.idleCycles 18394216 # Total number of cycles that the object has spent stopped |
| 418system.cpu.dcache.tags.replacements 156435 # number of replacements | 418system.cpu.dcache.tags.replacements 156435 # number of replacements |
| 419system.cpu.dcache.tags.tagsinuse 4067.140403 # Cycle average of tags in use 420system.cpu.dcache.tags.total_refs 42624247 # Total number of references to valid blocks. | 419system.cpu.dcache.tags.tagsinuse 4067.142814 # Cycle average of tags in use 420system.cpu.dcache.tags.total_refs 42624094 # Total number of references to valid blocks. |
| 421system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks. | 421system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks. |
| 422system.cpu.dcache.tags.avg_refs 265.520348 # Average number of references to valid blocks. 423system.cpu.dcache.tags.warmup_cycle 822680500 # Cycle when the warmup percentage was hit. 424system.cpu.dcache.tags.occ_blocks::cpu.data 4067.140403 # Average occupied blocks per requestor 425system.cpu.dcache.tags.occ_percent::cpu.data 0.992954 # Average percentage of cache occupancy 426system.cpu.dcache.tags.occ_percent::total 0.992954 # Average percentage of cache occupancy | 422system.cpu.dcache.tags.avg_refs 265.519395 # Average number of references to valid blocks. 423system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. 424system.cpu.dcache.tags.occ_blocks::cpu.data 4067.142814 # Average occupied blocks per requestor 425system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy 426system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy |
| 427system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 427system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 428system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 429system.cpu.dcache.tags.age_task_id_blocks_1024::1 1113 # Occupied blocks per task id 430system.cpu.dcache.tags.age_task_id_blocks_1024::2 2936 # Occupied blocks per task id | 428system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 429system.cpu.dcache.tags.age_task_id_blocks_1024::1 1110 # Occupied blocks per task id 430system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id |
| 431system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 431system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 432system.cpu.dcache.tags.tag_accesses 86016733 # Number of tag accesses 433system.cpu.dcache.tags.data_accesses 86016733 # Number of data accesses 434system.cpu.dcache.ReadReq_hits::cpu.data 22866807 # number of ReadReq hits 435system.cpu.dcache.ReadReq_hits::total 22866807 # number of ReadReq hits 436system.cpu.dcache.WriteReq_hits::cpu.data 19642189 # number of WriteReq hits 437system.cpu.dcache.WriteReq_hits::total 19642189 # number of WriteReq hits 438system.cpu.dcache.SoftPFReq_hits::cpu.data 83413 # number of SoftPFReq hits 439system.cpu.dcache.SoftPFReq_hits::total 83413 # number of SoftPFReq hits | 432system.cpu.dcache.tags.tag_accesses 86016729 # Number of tag accesses 433system.cpu.dcache.tags.data_accesses 86016729 # Number of data accesses 434system.cpu.dcache.ReadReq_hits::cpu.data 22866654 # number of ReadReq hits 435system.cpu.dcache.ReadReq_hits::total 22866654 # number of ReadReq hits 436system.cpu.dcache.WriteReq_hits::cpu.data 19642187 # number of WriteReq hits 437system.cpu.dcache.WriteReq_hits::total 19642187 # number of WriteReq hits 438system.cpu.dcache.SoftPFReq_hits::cpu.data 83415 # number of SoftPFReq hits 439system.cpu.dcache.SoftPFReq_hits::total 83415 # number of SoftPFReq hits |
| 440system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 441system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 442system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 443system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 440system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 441system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 442system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 443system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 444system.cpu.dcache.demand_hits::cpu.data 42508996 # number of demand (read+write) hits 445system.cpu.dcache.demand_hits::total 42508996 # number of demand (read+write) hits 446system.cpu.dcache.overall_hits::cpu.data 42592409 # number of overall hits 447system.cpu.dcache.overall_hits::total 42592409 # number of overall hits 448system.cpu.dcache.ReadReq_misses::cpu.data 51550 # number of ReadReq misses 449system.cpu.dcache.ReadReq_misses::total 51550 # number of ReadReq misses 450system.cpu.dcache.WriteReq_misses::cpu.data 207712 # number of WriteReq misses 451system.cpu.dcache.WriteReq_misses::total 207712 # number of WriteReq misses 452system.cpu.dcache.SoftPFReq_misses::cpu.data 44592 # number of SoftPFReq misses 453system.cpu.dcache.SoftPFReq_misses::total 44592 # number of SoftPFReq misses 454system.cpu.dcache.demand_misses::cpu.data 259262 # number of demand (read+write) misses 455system.cpu.dcache.demand_misses::total 259262 # number of demand (read+write) misses 456system.cpu.dcache.overall_misses::cpu.data 303854 # number of overall misses 457system.cpu.dcache.overall_misses::total 303854 # number of overall misses 458system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489104500 # number of ReadReq miss cycles 459system.cpu.dcache.ReadReq_miss_latency::total 1489104500 # number of ReadReq miss cycles 460system.cpu.dcache.WriteReq_miss_latency::cpu.data 16802314000 # number of WriteReq miss cycles 461system.cpu.dcache.WriteReq_miss_latency::total 16802314000 # number of WriteReq miss cycles 462system.cpu.dcache.demand_miss_latency::cpu.data 18291418500 # number of demand (read+write) miss cycles 463system.cpu.dcache.demand_miss_latency::total 18291418500 # number of demand (read+write) miss cycles 464system.cpu.dcache.overall_miss_latency::cpu.data 18291418500 # number of overall miss cycles 465system.cpu.dcache.overall_miss_latency::total 18291418500 # number of overall miss cycles 466system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) 467system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) | 444system.cpu.dcache.demand_hits::cpu.data 42508841 # number of demand (read+write) hits 445system.cpu.dcache.demand_hits::total 42508841 # number of demand (read+write) hits 446system.cpu.dcache.overall_hits::cpu.data 42592256 # number of overall hits 447system.cpu.dcache.overall_hits::total 42592256 # number of overall hits 448system.cpu.dcache.ReadReq_misses::cpu.data 51701 # number of ReadReq misses 449system.cpu.dcache.ReadReq_misses::total 51701 # number of ReadReq misses 450system.cpu.dcache.WriteReq_misses::cpu.data 207714 # number of WriteReq misses 451system.cpu.dcache.WriteReq_misses::total 207714 # number of WriteReq misses 452system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses 453system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses 454system.cpu.dcache.demand_misses::cpu.data 259415 # number of demand (read+write) misses 455system.cpu.dcache.demand_misses::total 259415 # number of demand (read+write) misses 456system.cpu.dcache.overall_misses::cpu.data 304005 # number of overall misses 457system.cpu.dcache.overall_misses::total 304005 # number of overall misses 458system.cpu.dcache.ReadReq_miss_latency::cpu.data 1492164500 # number of ReadReq miss cycles 459system.cpu.dcache.ReadReq_miss_latency::total 1492164500 # number of ReadReq miss cycles 460system.cpu.dcache.WriteReq_miss_latency::cpu.data 16804934500 # number of WriteReq miss cycles 461system.cpu.dcache.WriteReq_miss_latency::total 16804934500 # number of WriteReq miss cycles 462system.cpu.dcache.demand_miss_latency::cpu.data 18297099000 # number of demand (read+write) miss cycles 463system.cpu.dcache.demand_miss_latency::total 18297099000 # number of demand (read+write) miss cycles 464system.cpu.dcache.overall_miss_latency::cpu.data 18297099000 # number of overall miss cycles 465system.cpu.dcache.overall_miss_latency::total 18297099000 # number of overall miss cycles 466system.cpu.dcache.ReadReq_accesses::cpu.data 22918355 # number of ReadReq accesses(hits+misses) 467system.cpu.dcache.ReadReq_accesses::total 22918355 # number of ReadReq accesses(hits+misses) |
| 468system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 469system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 470system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) 471system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses) 472system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 468system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 469system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 470system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) 471system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses) 472system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 476system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses 477system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses 478system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses 479system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses 480system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses 481system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses | 476system.cpu.dcache.demand_accesses::cpu.data 42768256 # number of demand (read+write) accesses 477system.cpu.dcache.demand_accesses::total 42768256 # number of demand (read+write) accesses 478system.cpu.dcache.overall_accesses::cpu.data 42896261 # number of overall (read+write) accesses 479system.cpu.dcache.overall_accesses::total 42896261 # number of overall (read+write) accesses 480system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002256 # miss rate for ReadReq accesses 481system.cpu.dcache.ReadReq_miss_rate::total 0.002256 # miss rate for ReadReq accesses |
| 482system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses 483system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses | 482system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses 483system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses |
| 484system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348361 # miss rate for SoftPFReq accesses 485system.cpu.dcache.SoftPFReq_miss_rate::total 0.348361 # miss rate for SoftPFReq accesses 486system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses 487system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses 488system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses 489system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses 490system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28886.605238 # average ReadReq miss latency 491system.cpu.dcache.ReadReq_avg_miss_latency::total 28886.605238 # average ReadReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80892.360576 # average WriteReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::total 80892.360576 # average WriteReq miss latency 494system.cpu.dcache.demand_avg_miss_latency::cpu.data 70551.868380 # average overall miss latency 495system.cpu.dcache.demand_avg_miss_latency::total 70551.868380 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::cpu.data 60198.050709 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::total 60198.050709 # average overall miss latency | 484system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348346 # miss rate for SoftPFReq accesses 485system.cpu.dcache.SoftPFReq_miss_rate::total 0.348346 # miss rate for SoftPFReq accesses 486system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses 487system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses 488system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses 489system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses 490system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28861.424344 # average ReadReq miss latency 491system.cpu.dcache.ReadReq_avg_miss_latency::total 28861.424344 # average ReadReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80904.197599 # average WriteReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::total 80904.197599 # average WriteReq miss latency 494system.cpu.dcache.demand_avg_miss_latency::cpu.data 70532.155041 # average overall miss latency 495system.cpu.dcache.demand_avg_miss_latency::total 70532.155041 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::cpu.data 60186.835743 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::total 60186.835743 # average overall miss latency |
| 498system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.dcache.fast_writes 0 # number of fast writes performed 505system.cpu.dcache.cache_copies 0 # number of cache copies performed 506system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks 507system.cpu.dcache.writebacks::total 128400 # number of writebacks | 498system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.dcache.fast_writes 0 # number of fast writes performed 505system.cpu.dcache.cache_copies 0 # number of cache copies performed 506system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks 507system.cpu.dcache.writebacks::total 128400 # number of writebacks |
| 508system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22032 # number of ReadReq MSHR hits 509system.cpu.dcache.ReadReq_mshr_hits::total 22032 # number of ReadReq MSHR hits 510system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100684 # number of WriteReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::total 100684 # number of WriteReq MSHR hits 512system.cpu.dcache.demand_mshr_hits::cpu.data 122716 # number of demand (read+write) MSHR hits 513system.cpu.dcache.demand_mshr_hits::total 122716 # number of demand (read+write) MSHR hits 514system.cpu.dcache.overall_mshr_hits::cpu.data 122716 # number of overall MSHR hits 515system.cpu.dcache.overall_mshr_hits::total 122716 # number of overall MSHR hits | 508system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22183 # number of ReadReq MSHR hits 509system.cpu.dcache.ReadReq_mshr_hits::total 22183 # number of ReadReq MSHR hits 510system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100686 # number of WriteReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::total 100686 # number of WriteReq MSHR hits 512system.cpu.dcache.demand_mshr_hits::cpu.data 122869 # number of demand (read+write) MSHR hits 513system.cpu.dcache.demand_mshr_hits::total 122869 # number of demand (read+write) MSHR hits 514system.cpu.dcache.overall_mshr_hits::cpu.data 122869 # number of overall MSHR hits 515system.cpu.dcache.overall_mshr_hits::total 122869 # number of overall MSHR hits |
| 516system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses 517system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses 519system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses 520system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses 521system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses 522system.cpu.dcache.demand_mshr_misses::cpu.data 136546 # number of demand (read+write) MSHR misses 523system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses 524system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses 525system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses | 516system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses 517system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses 519system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses 520system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses 521system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses 522system.cpu.dcache.demand_mshr_misses::cpu.data 136546 # number of demand (read+write) MSHR misses 523system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses 524system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses 525system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses |
| 526system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 574723500 # number of ReadReq MSHR miss cycles 527system.cpu.dcache.ReadReq_mshr_miss_latency::total 574723500 # number of ReadReq MSHR miss cycles 528system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8485443000 # number of WriteReq MSHR miss cycles 529system.cpu.dcache.WriteReq_mshr_miss_latency::total 8485443000 # number of WriteReq MSHR miss cycles 530system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719503000 # number of SoftPFReq MSHR miss cycles 531system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719503000 # number of SoftPFReq MSHR miss cycles 532system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9060166500 # number of demand (read+write) MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::total 9060166500 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779669500 # number of overall MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::total 10779669500 # number of overall MSHR miss cycles | 526system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578376000 # number of ReadReq MSHR miss cycles 527system.cpu.dcache.ReadReq_mshr_miss_latency::total 578376000 # number of ReadReq MSHR miss cycles 528system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8484284000 # number of WriteReq MSHR miss cycles 529system.cpu.dcache.WriteReq_mshr_miss_latency::total 8484284000 # number of WriteReq MSHR miss cycles 530system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1716349500 # number of SoftPFReq MSHR miss cycles 531system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1716349500 # number of SoftPFReq MSHR miss cycles 532system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9062660000 # number of demand (read+write) MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::total 9062660000 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779009500 # number of overall MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::total 10779009500 # number of overall MSHR miss cycles |
| 536system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses 537system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses 538system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 539system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 540system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses 541system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses 542system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses 543system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses 544system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 545system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses | 536system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses 537system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses 538system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 539system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 540system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses 541system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses 542system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses 543system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses 544system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 545system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses |
| 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19470.272376 # average ReadReq mshr miss latency 547system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19470.272376 # average ReadReq mshr miss latency 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79282.458796 # average WriteReq mshr miss latency 549system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79282.458796 # average WriteReq mshr miss latency 550system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71690.765061 # average SoftPFReq mshr miss latency 551system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71690.765061 # average SoftPFReq mshr miss latency 552system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66352.485609 # average overall mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::total 66352.485609 # average overall mshr miss latency 554system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67150.080047 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::total 67150.080047 # average overall mshr miss latency | 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19594.010434 # average ReadReq mshr miss latency 547system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19594.010434 # average ReadReq mshr miss latency 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79271.629854 # average WriteReq mshr miss latency 549system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79271.629854 # average WriteReq mshr miss latency 550system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71559.287054 # average SoftPFReq mshr miss latency 551system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71559.287054 # average SoftPFReq mshr miss latency 552system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66370.746855 # average overall mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::total 66370.746855 # average overall mshr miss latency 554system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67145.968691 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::total 67145.968691 # average overall mshr miss latency |
| 556system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 556system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 557system.cpu.icache.tags.replacements 42865 # number of replacements 558system.cpu.icache.tags.tagsinuse 1852.538301 # Cycle average of tags in use 559system.cpu.icache.tags.total_refs 24941041 # Total number of references to valid blocks. 560system.cpu.icache.tags.sampled_refs 44907 # Sample count of references to valid blocks. 561system.cpu.icache.tags.avg_refs 555.393168 # Average number of references to valid blocks. | 557system.cpu.icache.tags.replacements 42866 # number of replacements 558system.cpu.icache.tags.tagsinuse 1852.547846 # Cycle average of tags in use 559system.cpu.icache.tags.total_refs 24941084 # Total number of references to valid blocks. 560system.cpu.icache.tags.sampled_refs 44908 # Sample count of references to valid blocks. 561system.cpu.icache.tags.avg_refs 555.381758 # Average number of references to valid blocks. |
| 562system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 562system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 563system.cpu.icache.tags.occ_blocks::cpu.inst 1852.538301 # Average occupied blocks per requestor 564system.cpu.icache.tags.occ_percent::cpu.inst 0.904560 # Average percentage of cache occupancy 565system.cpu.icache.tags.occ_percent::total 0.904560 # Average percentage of cache occupancy | 563system.cpu.icache.tags.occ_blocks::cpu.inst 1852.547846 # Average occupied blocks per requestor 564system.cpu.icache.tags.occ_percent::cpu.inst 0.904564 # Average percentage of cache occupancy 565system.cpu.icache.tags.occ_percent::total 0.904564 # Average percentage of cache occupancy |
| 566system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id | 566system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id |
| 567system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 568system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id | 567system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 568system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id |
| 569system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id 570system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id 571system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id | 569system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id 570system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id 571system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id |
| 572system.cpu.icache.tags.tag_accesses 50016805 # Number of tag accesses 573system.cpu.icache.tags.data_accesses 50016805 # Number of data accesses 574system.cpu.icache.ReadReq_hits::cpu.inst 24941041 # number of ReadReq hits 575system.cpu.icache.ReadReq_hits::total 24941041 # number of ReadReq hits 576system.cpu.icache.demand_hits::cpu.inst 24941041 # number of demand (read+write) hits 577system.cpu.icache.demand_hits::total 24941041 # number of demand (read+write) hits 578system.cpu.icache.overall_hits::cpu.inst 24941041 # number of overall hits 579system.cpu.icache.overall_hits::total 24941041 # number of overall hits 580system.cpu.icache.ReadReq_misses::cpu.inst 44908 # number of ReadReq misses 581system.cpu.icache.ReadReq_misses::total 44908 # number of ReadReq misses 582system.cpu.icache.demand_misses::cpu.inst 44908 # number of demand (read+write) misses 583system.cpu.icache.demand_misses::total 44908 # number of demand (read+write) misses 584system.cpu.icache.overall_misses::cpu.inst 44908 # number of overall misses 585system.cpu.icache.overall_misses::total 44908 # number of overall misses 586system.cpu.icache.ReadReq_miss_latency::cpu.inst 926324500 # number of ReadReq miss cycles 587system.cpu.icache.ReadReq_miss_latency::total 926324500 # number of ReadReq miss cycles 588system.cpu.icache.demand_miss_latency::cpu.inst 926324500 # number of demand (read+write) miss cycles 589system.cpu.icache.demand_miss_latency::total 926324500 # number of demand (read+write) miss cycles 590system.cpu.icache.overall_miss_latency::cpu.inst 926324500 # number of overall miss cycles 591system.cpu.icache.overall_miss_latency::total 926324500 # number of overall miss cycles 592system.cpu.icache.ReadReq_accesses::cpu.inst 24985949 # number of ReadReq accesses(hits+misses) 593system.cpu.icache.ReadReq_accesses::total 24985949 # number of ReadReq accesses(hits+misses) 594system.cpu.icache.demand_accesses::cpu.inst 24985949 # number of demand (read+write) accesses 595system.cpu.icache.demand_accesses::total 24985949 # number of demand (read+write) accesses 596system.cpu.icache.overall_accesses::cpu.inst 24985949 # number of overall (read+write) accesses 597system.cpu.icache.overall_accesses::total 24985949 # number of overall (read+write) accesses | 572system.cpu.icache.tags.tag_accesses 50016894 # Number of tag accesses 573system.cpu.icache.tags.data_accesses 50016894 # Number of data accesses 574system.cpu.icache.ReadReq_hits::cpu.inst 24941084 # number of ReadReq hits 575system.cpu.icache.ReadReq_hits::total 24941084 # number of ReadReq hits 576system.cpu.icache.demand_hits::cpu.inst 24941084 # number of demand (read+write) hits 577system.cpu.icache.demand_hits::total 24941084 # number of demand (read+write) hits 578system.cpu.icache.overall_hits::cpu.inst 24941084 # number of overall hits 579system.cpu.icache.overall_hits::total 24941084 # number of overall hits 580system.cpu.icache.ReadReq_misses::cpu.inst 44909 # number of ReadReq misses 581system.cpu.icache.ReadReq_misses::total 44909 # number of ReadReq misses 582system.cpu.icache.demand_misses::cpu.inst 44909 # number of demand (read+write) misses 583system.cpu.icache.demand_misses::total 44909 # number of demand (read+write) misses 584system.cpu.icache.overall_misses::cpu.inst 44909 # number of overall misses 585system.cpu.icache.overall_misses::total 44909 # number of overall misses 586system.cpu.icache.ReadReq_miss_latency::cpu.inst 929470000 # number of ReadReq miss cycles 587system.cpu.icache.ReadReq_miss_latency::total 929470000 # number of ReadReq miss cycles 588system.cpu.icache.demand_miss_latency::cpu.inst 929470000 # number of demand (read+write) miss cycles 589system.cpu.icache.demand_miss_latency::total 929470000 # number of demand (read+write) miss cycles 590system.cpu.icache.overall_miss_latency::cpu.inst 929470000 # number of overall miss cycles 591system.cpu.icache.overall_miss_latency::total 929470000 # number of overall miss cycles 592system.cpu.icache.ReadReq_accesses::cpu.inst 24985993 # number of ReadReq accesses(hits+misses) 593system.cpu.icache.ReadReq_accesses::total 24985993 # number of ReadReq accesses(hits+misses) 594system.cpu.icache.demand_accesses::cpu.inst 24985993 # number of demand (read+write) accesses 595system.cpu.icache.demand_accesses::total 24985993 # number of demand (read+write) accesses 596system.cpu.icache.overall_accesses::cpu.inst 24985993 # number of overall (read+write) accesses 597system.cpu.icache.overall_accesses::total 24985993 # number of overall (read+write) accesses |
| 598system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses 599system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses 600system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses 601system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses 602system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses 603system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses | 598system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses 599system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses 600system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses 601system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses 602system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses 603system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses |
| 604system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20627.159971 # average ReadReq miss latency 605system.cpu.icache.ReadReq_avg_miss_latency::total 20627.159971 # average ReadReq miss latency 606system.cpu.icache.demand_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency 607system.cpu.icache.demand_avg_miss_latency::total 20627.159971 # average overall miss latency 608system.cpu.icache.overall_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency 609system.cpu.icache.overall_avg_miss_latency::total 20627.159971 # average overall miss latency | 604system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20696.742301 # average ReadReq miss latency 605system.cpu.icache.ReadReq_avg_miss_latency::total 20696.742301 # average ReadReq miss latency 606system.cpu.icache.demand_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency 607system.cpu.icache.demand_avg_miss_latency::total 20696.742301 # average overall miss latency 608system.cpu.icache.overall_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency 609system.cpu.icache.overall_avg_miss_latency::total 20696.742301 # average overall miss latency |
| 610system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu.icache.fast_writes 0 # number of fast writes performed 617system.cpu.icache.cache_copies 0 # number of cache copies performed | 610system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu.icache.fast_writes 0 # number of fast writes performed 617system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 618system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44908 # number of ReadReq MSHR misses 619system.cpu.icache.ReadReq_mshr_misses::total 44908 # number of ReadReq MSHR misses 620system.cpu.icache.demand_mshr_misses::cpu.inst 44908 # number of demand (read+write) MSHR misses 621system.cpu.icache.demand_mshr_misses::total 44908 # number of demand (read+write) MSHR misses 622system.cpu.icache.overall_mshr_misses::cpu.inst 44908 # number of overall MSHR misses 623system.cpu.icache.overall_mshr_misses::total 44908 # number of overall MSHR misses 624system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 881417500 # number of ReadReq MSHR miss cycles 625system.cpu.icache.ReadReq_mshr_miss_latency::total 881417500 # number of ReadReq MSHR miss cycles 626system.cpu.icache.demand_mshr_miss_latency::cpu.inst 881417500 # number of demand (read+write) MSHR miss cycles 627system.cpu.icache.demand_mshr_miss_latency::total 881417500 # number of demand (read+write) MSHR miss cycles 628system.cpu.icache.overall_mshr_miss_latency::cpu.inst 881417500 # number of overall MSHR miss cycles 629system.cpu.icache.overall_mshr_miss_latency::total 881417500 # number of overall MSHR miss cycles | 618system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44909 # number of ReadReq MSHR misses 619system.cpu.icache.ReadReq_mshr_misses::total 44909 # number of ReadReq MSHR misses 620system.cpu.icache.demand_mshr_misses::cpu.inst 44909 # number of demand (read+write) MSHR misses 621system.cpu.icache.demand_mshr_misses::total 44909 # number of demand (read+write) MSHR misses 622system.cpu.icache.overall_mshr_misses::cpu.inst 44909 # number of overall MSHR misses 623system.cpu.icache.overall_mshr_misses::total 44909 # number of overall MSHR misses 624system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 884562000 # number of ReadReq MSHR miss cycles 625system.cpu.icache.ReadReq_mshr_miss_latency::total 884562000 # number of ReadReq MSHR miss cycles 626system.cpu.icache.demand_mshr_miss_latency::cpu.inst 884562000 # number of demand (read+write) MSHR miss cycles 627system.cpu.icache.demand_mshr_miss_latency::total 884562000 # number of demand (read+write) MSHR miss cycles 628system.cpu.icache.overall_mshr_miss_latency::cpu.inst 884562000 # number of overall MSHR miss cycles 629system.cpu.icache.overall_mshr_miss_latency::total 884562000 # number of overall MSHR miss cycles |
| 630system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses 631system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses 632system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses 633system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses 634system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses 635system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses | 630system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses 631system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses 632system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses 633system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses 634system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses 635system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses |
| 636system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19627.182239 # average ReadReq mshr miss latency 637system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19627.182239 # average ReadReq mshr miss latency 638system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency 639system.cpu.icache.demand_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency 640system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency 641system.cpu.icache.overall_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency | 636system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19696.764568 # average ReadReq mshr miss latency 637system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19696.764568 # average ReadReq mshr miss latency 638system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency 639system.cpu.icache.demand_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency 640system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency 641system.cpu.icache.overall_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency |
| 642system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 643system.cpu.l2cache.tags.replacements 95654 # number of replacements | 642system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 643system.cpu.l2cache.tags.replacements 95654 # number of replacements |
| 644system.cpu.l2cache.tags.tagsinuse 29860.809495 # Cycle average of tags in use 645system.cpu.l2cache.tags.total_refs 161643 # Total number of references to valid blocks. | 644system.cpu.l2cache.tags.tagsinuse 29860.905704 # Cycle average of tags in use 645system.cpu.l2cache.tags.total_refs 161645 # Total number of references to valid blocks. |
| 646system.cpu.l2cache.tags.sampled_refs 126772 # Sample count of references to valid blocks. | 646system.cpu.l2cache.tags.sampled_refs 126772 # Sample count of references to valid blocks. |
| 647system.cpu.l2cache.tags.avg_refs 1.275069 # Average number of references to valid blocks. | 647system.cpu.l2cache.tags.avg_refs 1.275084 # Average number of references to valid blocks. |
| 648system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 648system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 649system.cpu.l2cache.tags.occ_blocks::writebacks 26579.265460 # Average occupied blocks per requestor 650system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.835593 # Average occupied blocks per requestor 651system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.708442 # Average occupied blocks per requestor 652system.cpu.l2cache.tags.occ_percent::writebacks 0.811135 # Average percentage of cache occupancy 653system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049464 # Average percentage of cache occupancy 654system.cpu.l2cache.tags.occ_percent::cpu.data 0.050681 # Average percentage of cache occupancy 655system.cpu.l2cache.tags.occ_percent::total 0.911280 # Average percentage of cache occupancy | 649system.cpu.l2cache.tags.occ_blocks::writebacks 26579.253739 # Average occupied blocks per requestor 650system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.855600 # Average occupied blocks per requestor 651system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.796365 # Average occupied blocks per requestor 652system.cpu.l2cache.tags.occ_percent::writebacks 0.811134 # Average percentage of cache occupancy 653system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049465 # Average percentage of cache occupancy 654system.cpu.l2cache.tags.occ_percent::cpu.data 0.050683 # Average percentage of cache occupancy 655system.cpu.l2cache.tags.occ_percent::total 0.911283 # Average percentage of cache occupancy |
| 656system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id | 656system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id |
| 657system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 658system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1806 # Occupied blocks per task id 659system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12714 # Occupied blocks per task id 660system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15870 # Occupied blocks per task id | 657system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 658system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1809 # Occupied blocks per task id 659system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12704 # Occupied blocks per task id 660system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15880 # Occupied blocks per task id |
| 661system.cpu.l2cache.tags.age_task_id_blocks_1024::4 604 # Occupied blocks per task id 662system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id | 661system.cpu.l2cache.tags.age_task_id_blocks_1024::4 604 # Occupied blocks per task id 662system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id |
| 663system.cpu.l2cache.tags.tag_accesses 3409200 # Number of tag accesses 664system.cpu.l2cache.tags.data_accesses 3409200 # Number of data accesses | 663system.cpu.l2cache.tags.tag_accesses 3409216 # Number of tag accesses 664system.cpu.l2cache.tags.data_accesses 3409216 # Number of data accesses |
| 665system.cpu.l2cache.Writeback_hits::writebacks 128400 # number of Writeback hits 666system.cpu.l2cache.Writeback_hits::total 128400 # number of Writeback hits 667system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits 668system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits | 665system.cpu.l2cache.Writeback_hits::writebacks 128400 # number of Writeback hits 666system.cpu.l2cache.Writeback_hits::total 128400 # number of Writeback hits 667system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits 668system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits |
| 669system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39917 # number of ReadCleanReq hits 670system.cpu.l2cache.ReadCleanReq_hits::total 39917 # number of ReadCleanReq hits | 669system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39918 # number of ReadCleanReq hits 670system.cpu.l2cache.ReadCleanReq_hits::total 39918 # number of ReadCleanReq hits |
| 671system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31903 # number of ReadSharedReq hits 672system.cpu.l2cache.ReadSharedReq_hits::total 31903 # number of ReadSharedReq hits | 671system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31903 # number of ReadSharedReq hits 672system.cpu.l2cache.ReadSharedReq_hits::total 31903 # number of ReadSharedReq hits |
| 673system.cpu.l2cache.demand_hits::cpu.inst 39917 # number of demand (read+write) hits | 673system.cpu.l2cache.demand_hits::cpu.inst 39918 # number of demand (read+write) hits |
| 674system.cpu.l2cache.demand_hits::cpu.data 36655 # number of demand (read+write) hits | 674system.cpu.l2cache.demand_hits::cpu.data 36655 # number of demand (read+write) hits |
| 675system.cpu.l2cache.demand_hits::total 76572 # number of demand (read+write) hits 676system.cpu.l2cache.overall_hits::cpu.inst 39917 # number of overall hits | 675system.cpu.l2cache.demand_hits::total 76573 # number of demand (read+write) hits 676system.cpu.l2cache.overall_hits::cpu.inst 39918 # number of overall hits |
| 677system.cpu.l2cache.overall_hits::cpu.data 36655 # number of overall hits | 677system.cpu.l2cache.overall_hits::cpu.data 36655 # number of overall hits |
| 678system.cpu.l2cache.overall_hits::total 76572 # number of overall hits | 678system.cpu.l2cache.overall_hits::total 76573 # number of overall hits |
| 679system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses 680system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses 681system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4991 # number of ReadCleanReq misses 682system.cpu.l2cache.ReadCleanReq_misses::total 4991 # number of ReadCleanReq misses 683system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21600 # number of ReadSharedReq misses 684system.cpu.l2cache.ReadSharedReq_misses::total 21600 # number of ReadSharedReq misses 685system.cpu.l2cache.demand_misses::cpu.inst 4991 # number of demand (read+write) misses 686system.cpu.l2cache.demand_misses::cpu.data 123876 # number of demand (read+write) misses 687system.cpu.l2cache.demand_misses::total 128867 # number of demand (read+write) misses 688system.cpu.l2cache.overall_misses::cpu.inst 4991 # number of overall misses 689system.cpu.l2cache.overall_misses::cpu.data 123876 # number of overall misses 690system.cpu.l2cache.overall_misses::total 128867 # number of overall misses | 679system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses 680system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses 681system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4991 # number of ReadCleanReq misses 682system.cpu.l2cache.ReadCleanReq_misses::total 4991 # number of ReadCleanReq misses 683system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21600 # number of ReadSharedReq misses 684system.cpu.l2cache.ReadSharedReq_misses::total 21600 # number of ReadSharedReq misses 685system.cpu.l2cache.demand_misses::cpu.inst 4991 # number of demand (read+write) misses 686system.cpu.l2cache.demand_misses::cpu.data 123876 # number of demand (read+write) misses 687system.cpu.l2cache.demand_misses::total 128867 # number of demand (read+write) misses 688system.cpu.l2cache.overall_misses::cpu.inst 4991 # number of overall misses 689system.cpu.l2cache.overall_misses::cpu.data 123876 # number of overall misses 690system.cpu.l2cache.overall_misses::total 128867 # number of overall misses |
| 691system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8274960000 # number of ReadExReq miss cycles 692system.cpu.l2cache.ReadExReq_miss_latency::total 8274960000 # number of ReadExReq miss cycles 693system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394876000 # number of ReadCleanReq miss cycles 694system.cpu.l2cache.ReadCleanReq_miss_latency::total 394876000 # number of ReadCleanReq miss cycles 695system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1878573500 # number of ReadSharedReq miss cycles 696system.cpu.l2cache.ReadSharedReq_miss_latency::total 1878573500 # number of ReadSharedReq miss cycles 697system.cpu.l2cache.demand_miss_latency::cpu.inst 394876000 # number of demand (read+write) miss cycles 698system.cpu.l2cache.demand_miss_latency::cpu.data 10153533500 # number of demand (read+write) miss cycles 699system.cpu.l2cache.demand_miss_latency::total 10548409500 # number of demand (read+write) miss cycles 700system.cpu.l2cache.overall_miss_latency::cpu.inst 394876000 # number of overall miss cycles 701system.cpu.l2cache.overall_miss_latency::cpu.data 10153533500 # number of overall miss cycles 702system.cpu.l2cache.overall_miss_latency::total 10548409500 # number of overall miss cycles | 691system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8273802000 # number of ReadExReq miss cycles 692system.cpu.l2cache.ReadExReq_miss_latency::total 8273802000 # number of ReadExReq miss cycles 693system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394300500 # number of ReadCleanReq miss cycles 694system.cpu.l2cache.ReadCleanReq_miss_latency::total 394300500 # number of ReadCleanReq miss cycles 695system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1875098000 # number of ReadSharedReq miss cycles 696system.cpu.l2cache.ReadSharedReq_miss_latency::total 1875098000 # number of ReadSharedReq miss cycles 697system.cpu.l2cache.demand_miss_latency::cpu.inst 394300500 # number of demand (read+write) miss cycles 698system.cpu.l2cache.demand_miss_latency::cpu.data 10148900000 # number of demand (read+write) miss cycles 699system.cpu.l2cache.demand_miss_latency::total 10543200500 # number of demand (read+write) miss cycles 700system.cpu.l2cache.overall_miss_latency::cpu.inst 394300500 # number of overall miss cycles 701system.cpu.l2cache.overall_miss_latency::cpu.data 10148900000 # number of overall miss cycles 702system.cpu.l2cache.overall_miss_latency::total 10543200500 # number of overall miss cycles |
| 703system.cpu.l2cache.Writeback_accesses::writebacks 128400 # number of Writeback accesses(hits+misses) 704system.cpu.l2cache.Writeback_accesses::total 128400 # number of Writeback accesses(hits+misses) 705system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) 706system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) | 703system.cpu.l2cache.Writeback_accesses::writebacks 128400 # number of Writeback accesses(hits+misses) 704system.cpu.l2cache.Writeback_accesses::total 128400 # number of Writeback accesses(hits+misses) 705system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) 706system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) |
| 707system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44908 # number of ReadCleanReq accesses(hits+misses) 708system.cpu.l2cache.ReadCleanReq_accesses::total 44908 # number of ReadCleanReq accesses(hits+misses) | 707system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44909 # number of ReadCleanReq accesses(hits+misses) 708system.cpu.l2cache.ReadCleanReq_accesses::total 44909 # number of ReadCleanReq accesses(hits+misses) |
| 709system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses) 710system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses) | 709system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses) 710system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses) |
| 711system.cpu.l2cache.demand_accesses::cpu.inst 44908 # number of demand (read+write) accesses | 711system.cpu.l2cache.demand_accesses::cpu.inst 44909 # number of demand (read+write) accesses |
| 712system.cpu.l2cache.demand_accesses::cpu.data 160531 # number of demand (read+write) accesses | 712system.cpu.l2cache.demand_accesses::cpu.data 160531 # number of demand (read+write) accesses |
| 713system.cpu.l2cache.demand_accesses::total 205439 # number of demand (read+write) accesses 714system.cpu.l2cache.overall_accesses::cpu.inst 44908 # number of overall (read+write) accesses | 713system.cpu.l2cache.demand_accesses::total 205440 # number of demand (read+write) accesses 714system.cpu.l2cache.overall_accesses::cpu.inst 44909 # number of overall (read+write) accesses |
| 715system.cpu.l2cache.overall_accesses::cpu.data 160531 # number of overall (read+write) accesses | 715system.cpu.l2cache.overall_accesses::cpu.data 160531 # number of overall (read+write) accesses |
| 716system.cpu.l2cache.overall_accesses::total 205439 # number of overall (read+write) accesses | 716system.cpu.l2cache.overall_accesses::total 205440 # number of overall (read+write) accesses |
| 717system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses 718system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses | 717system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses 718system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses |
| 719system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111138 # miss rate for ReadCleanReq accesses 720system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111138 # miss rate for ReadCleanReq accesses | 719system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111136 # miss rate for ReadCleanReq accesses 720system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111136 # miss rate for ReadCleanReq accesses |
| 721system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403716 # miss rate for ReadSharedReq accesses 722system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403716 # miss rate for ReadSharedReq accesses | 721system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403716 # miss rate for ReadSharedReq accesses 722system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403716 # miss rate for ReadSharedReq accesses |
| 723system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111138 # miss rate for demand accesses | 723system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111136 # miss rate for demand accesses |
| 724system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses | 724system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses |
| 725system.cpu.l2cache.demand_miss_rate::total 0.627276 # miss rate for demand accesses 726system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111138 # miss rate for overall accesses | 725system.cpu.l2cache.demand_miss_rate::total 0.627273 # miss rate for demand accesses 726system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111136 # miss rate for overall accesses |
| 727system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses | 727system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses |
| 728system.cpu.l2cache.overall_miss_rate::total 0.627276 # miss rate for overall accesses 729system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80908.130940 # average ReadExReq miss latency 730system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80908.130940 # average ReadExReq miss latency 731system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79117.611701 # average ReadCleanReq miss latency 732system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79117.611701 # average ReadCleanReq miss latency 733system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86970.995370 # average ReadSharedReq miss latency 734system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86970.995370 # average ReadSharedReq miss latency 735system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency 736system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency 737system.cpu.l2cache.demand_avg_miss_latency::total 81855.009428 # average overall miss latency 738system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency 740system.cpu.l2cache.overall_avg_miss_latency::total 81855.009428 # average overall miss latency | 728system.cpu.l2cache.overall_miss_rate::total 0.627273 # miss rate for overall accesses 729system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80896.808635 # average ReadExReq miss latency 730system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80896.808635 # average ReadExReq miss latency 731system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79002.304147 # average ReadCleanReq miss latency 732system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79002.304147 # average ReadCleanReq miss latency 733system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86810.092593 # average ReadSharedReq miss latency 734system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86810.092593 # average ReadSharedReq miss latency 735system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency 736system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency 737system.cpu.l2cache.demand_avg_miss_latency::total 81814.587908 # average overall miss latency 738system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency 740system.cpu.l2cache.overall_avg_miss_latency::total 81814.587908 # average overall miss latency |
| 741system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 746system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.l2cache.fast_writes 0 # number of fast writes performed 748system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 767system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21535 # number of ReadSharedReq MSHR misses 768system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21535 # number of ReadSharedReq MSHR misses 769system.cpu.l2cache.demand_mshr_misses::cpu.inst 4981 # number of demand (read+write) MSHR misses 770system.cpu.l2cache.demand_mshr_misses::cpu.data 123811 # number of demand (read+write) MSHR misses 771system.cpu.l2cache.demand_mshr_misses::total 128792 # number of demand (read+write) MSHR misses 772system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses 773system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses 774system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses | 741system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 746system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.l2cache.fast_writes 0 # number of fast writes performed 748system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 767system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21535 # number of ReadSharedReq MSHR misses 768system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21535 # number of ReadSharedReq MSHR misses 769system.cpu.l2cache.demand_mshr_misses::cpu.inst 4981 # number of demand (read+write) MSHR misses 770system.cpu.l2cache.demand_mshr_misses::cpu.data 123811 # number of demand (read+write) MSHR misses 771system.cpu.l2cache.demand_mshr_misses::total 128792 # number of demand (read+write) MSHR misses 772system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses 773system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses 774system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses |
| 775system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7252200000 # number of ReadExReq MSHR miss cycles 776system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7252200000 # number of ReadExReq MSHR miss cycles 777system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 344388000 # number of ReadCleanReq MSHR miss cycles 778system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 344388000 # number of ReadCleanReq MSHR miss cycles 779system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1658643500 # number of ReadSharedReq MSHR miss cycles 780system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1658643500 # number of ReadSharedReq MSHR miss cycles 781system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 344388000 # number of demand (read+write) MSHR miss cycles 782system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8910843500 # number of demand (read+write) MSHR miss cycles 783system.cpu.l2cache.demand_mshr_miss_latency::total 9255231500 # number of demand (read+write) MSHR miss cycles 784system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 344388000 # number of overall MSHR miss cycles 785system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8910843500 # number of overall MSHR miss cycles 786system.cpu.l2cache.overall_mshr_miss_latency::total 9255231500 # number of overall MSHR miss cycles | 775system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7251042000 # number of ReadExReq MSHR miss cycles 776system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7251042000 # number of ReadExReq MSHR miss cycles 777system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 343845500 # number of ReadCleanReq MSHR miss cycles 778system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 343845500 # number of ReadCleanReq MSHR miss cycles 779system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1655136500 # number of ReadSharedReq MSHR miss cycles 780system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1655136500 # number of ReadSharedReq MSHR miss cycles 781system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 343845500 # number of demand (read+write) MSHR miss cycles 782system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8906178500 # number of demand (read+write) MSHR miss cycles 783system.cpu.l2cache.demand_mshr_miss_latency::total 9250024000 # number of demand (read+write) MSHR miss cycles 784system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 343845500 # number of overall MSHR miss cycles 785system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8906178500 # number of overall MSHR miss cycles 786system.cpu.l2cache.overall_mshr_miss_latency::total 9250024000 # number of overall MSHR miss cycles |
| 787system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 788system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 789system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses 790system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses | 787system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 788system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 789system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses 790system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses |
| 791system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for ReadCleanReq accesses 792system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110916 # mshr miss rate for ReadCleanReq accesses | 791system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for ReadCleanReq accesses 792system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110913 # mshr miss rate for ReadCleanReq accesses |
| 793system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses 794system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses | 793system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses 794system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses |
| 795system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for demand accesses | 795system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for demand accesses |
| 796system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses | 796system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses |
| 797system.cpu.l2cache.demand_mshr_miss_rate::total 0.626911 # mshr miss rate for demand accesses 798system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for overall accesses | 797system.cpu.l2cache.demand_mshr_miss_rate::total 0.626908 # mshr miss rate for demand accesses 798system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for overall accesses |
| 799system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses | 799system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses |
| 800system.cpu.l2cache.overall_mshr_miss_rate::total 0.626911 # mshr miss rate for overall accesses 801system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70908.130940 # average ReadExReq mshr miss latency 802system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70908.130940 # average ReadExReq mshr miss latency 803system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69140.333266 # average ReadCleanReq mshr miss latency 804system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69140.333266 # average ReadCleanReq mshr miss latency 805system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77020.826561 # average ReadSharedReq mshr miss latency 806system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77020.826561 # average ReadSharedReq mshr miss latency 807system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency 808system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency 809system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency 810system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency 811system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency 812system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency | 800system.cpu.l2cache.overall_mshr_miss_rate::total 0.626908 # mshr miss rate for overall accesses 801system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70896.808635 # average ReadExReq mshr miss latency 802system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70896.808635 # average ReadExReq mshr miss latency 803system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69031.419394 # average ReadCleanReq mshr miss latency 804system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69031.419394 # average ReadCleanReq mshr miss latency 805system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76857.975389 # average ReadSharedReq mshr miss latency 806system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76857.975389 # average ReadSharedReq mshr miss latency 807system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency 808system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency 809system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency 810system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency 811system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency 812system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency |
| 813system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 813system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 814system.cpu.toL2Bus.trans_dist::ReadResp 98410 # Transaction distribution | 814system.cpu.toL2Bus.snoop_filter.tot_requests 404741 # Total number of requests made to the snoop filter. 815system.cpu.toL2Bus.snoop_filter.hit_single_requests 199337 # Number of requests hitting in the snoop filter with a single holder of the requested data. 816system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 817system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. 818system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 819system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 820system.cpu.toL2Bus.trans_dist::ReadResp 98411 # Transaction distribution |
| 815system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution | 821system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution |
| 816system.cpu.toL2Bus.trans_dist::CleanEvict 72583 # Transaction distribution | 822system.cpu.toL2Bus.trans_dist::CleanEvict 72584 # Transaction distribution |
| 817system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution 818system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution | 823system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution 824system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution |
| 819system.cpu.toL2Bus.trans_dist::ReadCleanReq 44908 # Transaction distribution | 825system.cpu.toL2Bus.trans_dist::ReadCleanReq 44909 # Transaction distribution |
| 820system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution | 826system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution |
| 821system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129101 # Packet count per connected master and slave (bytes) | 827system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129104 # Packet count per connected master and slave (bytes) |
| 822system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes) | 828system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes) |
| 823system.cpu.toL2Bus.pkt_count::total 602363 # Packet count per connected master and slave (bytes) 824system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874048 # Cumulative packet size per connected master and slave (bytes) | 829system.cpu.toL2Bus.pkt_count::total 602366 # Packet count per connected master and slave (bytes) 830system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874112 # Cumulative packet size per connected master and slave (bytes) |
| 825system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes) | 831system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes) |
| 826system.cpu.toL2Bus.pkt_size::total 21365632 # Cumulative packet size per connected master and slave (bytes) | 832system.cpu.toL2Bus.pkt_size::total 21365696 # Cumulative packet size per connected master and slave (bytes) |
| 827system.cpu.toL2Bus.snoops 95654 # Total snoops (count) | 833system.cpu.toL2Bus.snoops 95654 # Total snoops (count) |
| 828system.cpu.toL2Bus.snoop_fanout::samples 500393 # Request fanout histogram 829system.cpu.toL2Bus.snoop_fanout::mean 1.191158 # Request fanout histogram 830system.cpu.toL2Bus.snoop_fanout::stdev 0.393213 # Request fanout histogram | 834system.cpu.toL2Bus.snoop_fanout::samples 500395 # Request fanout histogram 835system.cpu.toL2Bus.snoop_fanout::mean 0.038076 # Request fanout histogram 836system.cpu.toL2Bus.snoop_fanout::stdev 0.191682 # Request fanout histogram |
| 831system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 837system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 832system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 833system.cpu.toL2Bus.snoop_fanout::1 404739 80.88% 80.88% # Request fanout histogram 834system.cpu.toL2Bus.snoop_fanout::2 95654 19.12% 100.00% # Request fanout histogram | 838system.cpu.toL2Bus.snoop_fanout::0 481371 96.20% 96.20% # Request fanout histogram 839system.cpu.toL2Bus.snoop_fanout::1 18995 3.80% 99.99% # Request fanout histogram 840system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram |
| 835system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 841system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 836system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 842system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 837system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 843system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 838system.cpu.toL2Bus.snoop_fanout::total 500393 # Request fanout histogram 839system.cpu.toL2Bus.reqLayer0.occupancy 330769500 # Layer occupancy (ticks) | 844system.cpu.toL2Bus.snoop_fanout::total 500395 # Request fanout histogram 845system.cpu.toL2Bus.reqLayer0.occupancy 330770500 # Layer occupancy (ticks) |
| 840system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) | 846system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 841system.cpu.toL2Bus.respLayer0.occupancy 67366488 # Layer occupancy (ticks) | 847system.cpu.toL2Bus.respLayer0.occupancy 67369485 # Layer occupancy (ticks) |
| 842system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 848system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 843system.cpu.toL2Bus.respLayer1.occupancy 240828935 # Layer occupancy (ticks) | 849system.cpu.toL2Bus.respLayer1.occupancy 240829933 # Layer occupancy (ticks) |
| 844system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 845system.membus.trans_dist::ReadResp 26515 # Transaction distribution 846system.membus.trans_dist::Writeback 86157 # Transaction distribution 847system.membus.trans_dist::CleanEvict 7510 # Transaction distribution 848system.membus.trans_dist::ReadExReq 102276 # Transaction distribution 849system.membus.trans_dist::ReadExResp 102276 # Transaction distribution 850system.membus.trans_dist::ReadSharedReq 26515 # Transaction distribution 851system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351249 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 858system.membus.snoop_fanout::stdev 0 # Request fanout histogram 859system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 860system.membus.snoop_fanout::0 222458 100.00% 100.00% # Request fanout histogram 861system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 862system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 863system.membus.snoop_fanout::min_value 0 # Request fanout histogram 864system.membus.snoop_fanout::max_value 0 # Request fanout histogram 865system.membus.snoop_fanout::total 222458 # Request fanout histogram | 850system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 851system.membus.trans_dist::ReadResp 26515 # Transaction distribution 852system.membus.trans_dist::Writeback 86157 # Transaction distribution 853system.membus.trans_dist::CleanEvict 7510 # Transaction distribution 854system.membus.trans_dist::ReadExReq 102276 # Transaction distribution 855system.membus.trans_dist::ReadExResp 102276 # Transaction distribution 856system.membus.trans_dist::ReadSharedReq 26515 # Transaction distribution 857system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351249 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 864system.membus.snoop_fanout::stdev 0 # Request fanout histogram 865system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 866system.membus.snoop_fanout::0 222458 100.00% 100.00% # Request fanout histogram 867system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 868system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 869system.membus.snoop_fanout::min_value 0 # Request fanout histogram 870system.membus.snoop_fanout::max_value 0 # Request fanout histogram 871system.membus.snoop_fanout::total 222458 # Request fanout histogram |
| 866system.membus.reqLayer0.occupancy 591536000 # Layer occupancy (ticks) | 872system.membus.reqLayer0.occupancy 591531500 # Layer occupancy (ticks) |
| 867system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) | 873system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| 868system.membus.respLayer1.occupancy 679701000 # Layer occupancy (ticks) | 874system.membus.respLayer1.occupancy 679686000 # Layer occupancy (ticks) |
| 869system.membus.respLayer1.utilization 1.2 # Layer utilization (%) 870 871---------- End Simulation Statistics ---------- | 875system.membus.respLayer1.utilization 1.2 # Layer utilization (%) 876 877---------- End Simulation Statistics ---------- |