| stats.txt (10636:9ac724889705) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.057816 # Number of seconds simulated 4sim_ticks 57815555000 # Number of ticks simulated 5final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.058730 # Number of seconds simulated 4sim_ticks 58730125500 # Number of ticks simulated 5final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 131971 # Simulator instruction rate (inst/s) 8host_op_rate 168772 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 107593052 # Simulator tick rate (ticks/s) 10host_mem_usage 309228 # Number of bytes of host memory used 11host_seconds 537.35 # Real time elapsed on the host | 7host_inst_rate 197162 # Simulator instruction rate (inst/s) 8host_op_rate 252141 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 163284235 # Simulator tick rate (ticks/s) 10host_mem_usage 321164 # Number of bytes of host memory used 11host_seconds 359.68 # Real time elapsed on the host |
| 12sim_insts 70915127 # Number of instructions simulated 13sim_ops 90690083 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 70915127 # Number of instructions simulated 13sim_ops 90690083 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 324480 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7923328 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory |
| 21system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory | 21system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory |
| 23system.physmem.num_reads::cpu.inst 5070 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123802 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory | 23system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory |
| 26system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory | 26system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory |
| 28system.physmem.bw_read::cpu.inst 5612330 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 137044918 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 5612330 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 137044918 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 128872 # Number of read requests accepted | 28system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 128871 # Number of read requests accepted |
| 40system.physmem.writeReqs 83951 # Number of write requests accepted | 40system.physmem.writeReqs 83951 # Number of write requests accepted |
| 41system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue | 41system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue |
| 42system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue | 42system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue |
| 43system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM | 43system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM |
| 44system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue | 44system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue |
| 45system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side | 45system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side |
| 47system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8159 # Per bank write bursts | 47system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8159 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::1 8375 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8229 # Per bank write bursts | 52system.physmem.perBankRdBursts::1 8376 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8228 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::3 8171 # Per bank write bursts | 54system.physmem.perBankRdBursts::3 8171 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::4 8320 # Per bank write bursts | 55system.physmem.perBankRdBursts::4 8319 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::5 8450 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8088 # Per bank write bursts | 56system.physmem.perBankRdBursts::5 8450 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8088 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::7 7970 # Per bank write bursts | 58system.physmem.perBankRdBursts::7 7969 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::8 8071 # Per bank write bursts 60system.physmem.perBankRdBursts::9 7640 # Per bank write bursts | 59system.physmem.perBankRdBursts::8 8071 # Per bank write bursts 60system.physmem.perBankRdBursts::9 7640 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::10 7820 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7830 # Per bank write bursts | 61system.physmem.perBankRdBursts::10 7818 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7832 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::12 7881 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7879 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7977 # Per bank write bursts | 63system.physmem.perBankRdBursts::12 7881 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7879 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7977 # Per bank write bursts |
| 66system.physmem.perBankRdBursts::15 8006 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5183 # Per bank write bursts | 66system.physmem.perBankRdBursts::15 8007 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5180 # Per bank write bursts |
| 68system.physmem.perBankWrBursts::1 5376 # Per bank write bursts 69system.physmem.perBankWrBursts::2 5285 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5155 # Per bank write bursts 71system.physmem.perBankWrBursts::4 5266 # Per bank write bursts 72system.physmem.perBankWrBursts::5 5517 # Per bank write bursts | 68system.physmem.perBankWrBursts::1 5376 # Per bank write bursts 69system.physmem.perBankWrBursts::2 5285 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5155 # Per bank write bursts 71system.physmem.perBankWrBursts::4 5266 # Per bank write bursts 72system.physmem.perBankWrBursts::5 5517 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::6 5194 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5048 # Per bank write bursts | 73system.physmem.perBankWrBursts::6 5197 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5050 # Per bank write bursts |
| 75system.physmem.perBankWrBursts::8 5033 # Per bank write bursts | 75system.physmem.perBankWrBursts::8 5033 # Per bank write bursts |
| 76system.physmem.perBankWrBursts::9 5086 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5252 # Per bank write bursts | 76system.physmem.perBankWrBursts::9 5087 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5251 # Per bank write bursts |
| 78system.physmem.perBankWrBursts::11 5143 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5343 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5451 # Per bank write bursts | 78system.physmem.perBankWrBursts::11 5143 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5343 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5451 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::15 5225 # Per bank write bursts | 82system.physmem.perBankWrBursts::15 5227 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 57815523000 # Total gap between requests | 85system.physmem.totGap 58730091000 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 128872 # Read request sizes (log2) | 92system.physmem.readPktSize::6 128871 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 83951 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 83951 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see |
| 101system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see | 154system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see |
| 165system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 165system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes |
| 215system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes | 214system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 217system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads 232system.physmem.totQLat 1505377000 # Total ticks spent queuing 233system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM 234system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers 235system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst | 216system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads 230system.physmem.totQLat 1533027250 # Total ticks spent queuing 231system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers 233system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst |
| 236system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 237system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst 238system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s 239system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s 240system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s 241system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s | 235system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s 237system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s 238system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s |
| 242system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 243system.physmem.busUtil 1.84 # Data bus utilization in percentage 244system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads 245system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes | 241system.physmem.busUtil 1.81 # Data bus utilization in percentage 242system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes |
| 246system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing | 244system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing |
| 247system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing 248system.physmem.readRowHits 112203 # Number of row buffer hits during reads 249system.physmem.writeRowHits 62134 # Number of row buffer hits during writes 250system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads 251system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes 252system.physmem.avgGap 271660.13 # Average gap between requests 253system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined 254system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ) 255system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ) 256system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ) 257system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) 258system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) 259system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ) 260system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ) 261system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ) 262system.physmem_0.averagePower 707.837327 # Core power per rank (mW) 263system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states 264system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states | 245system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing 246system.physmem.readRowHits 112070 # Number of row buffer hits during reads 247system.physmem.writeRowHits 62147 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes 250system.physmem.avgGap 275958.74 # Average gap between requests 251system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined 252system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) 253system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) 254system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ) 255system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ) 256system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) 257system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ) 258system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ) 259system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ) 260system.physmem_0.averagePower 708.329716 # Core power per rank (mW) 261system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states 262system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states |
| 265system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 263system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 266system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states | 264system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states |
| 267system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 265system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 268system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ) 269system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ) 270system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ) 271system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ) 272system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) 273system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ) 274system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ) 275system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ) 276system.physmem_1.averagePower 706.292941 # Core power per rank (mW) 277system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states 278system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states | 266system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ) 267system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ) 268system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ) 269system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ) 270system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) 271system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ) 272system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ) 273system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ) 274system.physmem_1.averagePower 706.358131 # Core power per rank (mW) 275system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states 276system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states |
| 279system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 277system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 280system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states | 278system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states |
| 281system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 279system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 282system.cpu.branchPred.lookups 14822198 # Number of BP lookups 283system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits | 280system.cpu.branchPred.lookups 14827059 # Number of BP lookups 281system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits |
| 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 288system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target. | 286system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target. |
| 290system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. 291system.cpu_clk_domain.clock 500 # Clock period in ticks 292system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 401system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 402system.cpu.itb.read_accesses 0 # DTB read accesses 403system.cpu.itb.write_accesses 0 # DTB write accesses 404system.cpu.itb.inst_accesses 0 # ITB inst accesses 405system.cpu.itb.hits 0 # DTB hits 406system.cpu.itb.misses 0 # DTB misses 407system.cpu.itb.accesses 0 # DTB accesses 408system.cpu.workload.num_syscalls 1946 # Number of system calls | 288system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. 289system.cpu_clk_domain.clock 500 # Clock period in ticks 290system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 399system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.itb.read_accesses 0 # DTB read accesses 401system.cpu.itb.write_accesses 0 # DTB write accesses 402system.cpu.itb.inst_accesses 0 # ITB inst accesses 403system.cpu.itb.hits 0 # DTB hits 404system.cpu.itb.misses 0 # DTB misses 405system.cpu.itb.accesses 0 # DTB accesses 406system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 409system.cpu.numCycles 115631110 # number of cpu cycles simulated | 407system.cpu.numCycles 117460251 # number of cpu cycles simulated |
| 410system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 411system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 412system.cpu.committedInsts 70915127 # Number of instructions committed 413system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed | 408system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 409system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 410system.cpu.committedInsts 70915127 # Number of instructions committed 411system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed |
| 414system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit | 412system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit |
| 415system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 413system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 416system.cpu.cpi 1.630556 # CPI: cycles per instruction 417system.cpu.ipc 0.613288 # IPC: instructions per cycle 418system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked 419system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped 420system.cpu.dcache.tags.replacements 156428 # number of replacements 421system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use 422system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks. 423system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. 424system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. 425system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. 426system.cpu.dcache.tags.occ_blocks::cpu.data 4068.581764 # Average occupied blocks per requestor 427system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy 428system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy | 414system.cpu.cpi 1.656350 # CPI: cycles per instruction 415system.cpu.ipc 0.603737 # IPC: instructions per cycle 416system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked 417system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped 418system.cpu.dcache.tags.replacements 156434 # number of replacements 419system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use 420system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks. 421system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks. 422system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks. 423system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit. 424system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor 425system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy 426system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy |
| 429system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 427system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 430system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 431system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id 432system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id | 428system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 429system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id 430system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id |
| 433system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 431system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 434system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses 435system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses 436system.cpu.dcache.ReadReq_hits::cpu.data 22989229 # number of ReadReq hits 437system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits 438system.cpu.dcache.WriteReq_hits::cpu.data 19643835 # number of WriteReq hits 439system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits | 432system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses 433system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses 434system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits 435system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits 436system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits 437system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits |
| 440system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 441system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 442system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 443system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 438system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 439system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 440system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 441system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 444system.cpu.dcache.demand_hits::cpu.data 42633064 # number of demand (read+write) hits 445system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits 446system.cpu.dcache.overall_hits::cpu.data 42633064 # number of overall hits 447system.cpu.dcache.overall_hits::total 42633064 # number of overall hits 448system.cpu.dcache.ReadReq_misses::cpu.data 56065 # number of ReadReq misses 449system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses 450system.cpu.dcache.WriteReq_misses::cpu.data 206066 # number of WriteReq misses 451system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses 452system.cpu.dcache.demand_misses::cpu.data 262131 # number of demand (read+write) misses 453system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses 454system.cpu.dcache.overall_misses::cpu.data 262131 # number of overall misses 455system.cpu.dcache.overall_misses::total 262131 # number of overall misses 456system.cpu.dcache.ReadReq_miss_latency::cpu.data 2147242437 # number of ReadReq miss cycles 457system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles 458system.cpu.dcache.WriteReq_miss_latency::cpu.data 15196521000 # number of WriteReq miss cycles 459system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles 460system.cpu.dcache.demand_miss_latency::cpu.data 17343763437 # number of demand (read+write) miss cycles 461system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles 462system.cpu.dcache.overall_miss_latency::cpu.data 17343763437 # number of overall miss cycles 463system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles 464system.cpu.dcache.ReadReq_accesses::cpu.data 23045294 # number of ReadReq accesses(hits+misses) 465system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) | 442system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits 443system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits 444system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits 445system.cpu.dcache.overall_hits::total 42634623 # number of overall hits 446system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses 447system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses 448system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses 449system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses 450system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses 451system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses 452system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses 453system.cpu.dcache.overall_misses::total 262226 # number of overall misses 454system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles 455system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles 456system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles 457system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles 458system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles 459system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles 460system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles 461system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles 462system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses) 463system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses) |
| 466system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 467system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 468system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 469system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 470system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 471system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 464system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 465system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 466system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 467system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 468system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 469system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 472system.cpu.dcache.demand_accesses::cpu.data 42895195 # number of demand (read+write) accesses 473system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses 474system.cpu.dcache.overall_accesses::cpu.data 42895195 # number of overall (read+write) accesses 475system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses | 470system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses 471system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses 472system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses 473system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses |
| 476system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses 477system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses | 474system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses 475system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses |
| 478system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010381 # miss rate for WriteReq accesses 479system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses 480system.cpu.dcache.demand_miss_rate::cpu.data 0.006111 # miss rate for demand accesses 481system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses 482system.cpu.dcache.overall_miss_rate::cpu.data 0.006111 # miss rate for overall accesses 483system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses 484system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564 # average ReadReq miss latency 485system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency 486system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093 # average WriteReq miss latency 487system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency 488system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency 489system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency 490system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency 491system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency | 476system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses 477system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses 478system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses 479system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses 480system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses 481system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses 482system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency 483system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency 484system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency 485system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency 486system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency 487system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency 488system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency 489system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency |
| 492system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 493system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 494system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 495system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 496system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 497system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 498system.cpu.dcache.fast_writes 0 # number of fast writes performed 499system.cpu.dcache.cache_copies 0 # number of cache copies performed | 490system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 491system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 492system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 493system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 494system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 495system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 496system.cpu.dcache.fast_writes 0 # number of fast writes performed 497system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 500system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks 501system.cpu.dcache.writebacks::total 128441 # number of writebacks 502system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2577 # number of ReadReq MSHR hits 503system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits 504system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99030 # number of WriteReq MSHR hits 505system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number of WriteReq MSHR hits 506system.cpu.dcache.demand_mshr_hits::cpu.data 101607 # number of demand (read+write) MSHR hits 507system.cpu.dcache.demand_mshr_hits::total 101607 # number of demand (read+write) MSHR hits 508system.cpu.dcache.overall_mshr_hits::cpu.data 101607 # number of overall MSHR hits 509system.cpu.dcache.overall_mshr_hits::total 101607 # number of overall MSHR hits 510system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53488 # number of ReadReq MSHR misses 511system.cpu.dcache.ReadReq_mshr_misses::total 53488 # number of ReadReq MSHR misses 512system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107036 # number of WriteReq MSHR misses 513system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses 514system.cpu.dcache.demand_mshr_misses::cpu.data 160524 # number of demand (read+write) MSHR misses 515system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses 516system.cpu.dcache.overall_mshr_misses::cpu.data 160524 # number of overall MSHR misses 517system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses 518system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1987609313 # number of ReadReq MSHR miss cycles 519system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles 520system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7609976000 # number of WriteReq MSHR miss cycles 521system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles 522system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9597585313 # number of demand (read+write) MSHR miss cycles 523system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles 524system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9597585313 # number of overall MSHR miss cycles 525system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles | 498system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks 499system.cpu.dcache.writebacks::total 128445 # number of writebacks 500system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits 501system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits 502system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits 503system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits 504system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits 505system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits 506system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits 507system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits 508system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses 509system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses 510system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses 511system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses 512system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses 513system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses 514system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses 515system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses 516system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles 517system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles 518system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles 519system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles 520system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles 521system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles 522system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles 523system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles |
| 526system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses 527system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses 528system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 529system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 530system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for demand accesses 531system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses 532system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 533system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses | 524system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses 525system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses 526system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 527system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 528system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for demand accesses 529system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses 530system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 531system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses |
| 534system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877 # average ReadReq mshr miss latency 535system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency 536system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424 # average WriteReq mshr miss latency 537system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency 538system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency 539system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency 540system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency 541system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency | 532system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency 533system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency 534system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency 535system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency 536system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency 537system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency 538system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency 539system.cpu.dcache.overall_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency |
| 542system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 540system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 543system.cpu.icache.tags.replacements 42682 # number of replacements 544system.cpu.icache.tags.tagsinuse 1858.929385 # Cycle average of tags in use 545system.cpu.icache.tags.total_refs 25083355 # Total number of references to valid blocks. 546system.cpu.icache.tags.sampled_refs 44724 # Sample count of references to valid blocks. 547system.cpu.icache.tags.avg_refs 560.847755 # Average number of references to valid blocks. | 541system.cpu.icache.tags.replacements 42774 # number of replacements 542system.cpu.icache.tags.tagsinuse 1856.910000 # Cycle average of tags in use 543system.cpu.icache.tags.total_refs 25093452 # Total number of references to valid blocks. 544system.cpu.icache.tags.sampled_refs 44816 # Sample count of references to valid blocks. 545system.cpu.icache.tags.avg_refs 559.921724 # Average number of references to valid blocks. |
| 548system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 546system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 549system.cpu.icache.tags.occ_blocks::cpu.inst 1858.929385 # Average occupied blocks per requestor 550system.cpu.icache.tags.occ_percent::cpu.inst 0.907680 # Average percentage of cache occupancy 551system.cpu.icache.tags.occ_percent::total 0.907680 # Average percentage of cache occupancy | 547system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor 548system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy 549system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy |
| 552system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id | 550system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id |
| 553system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 554system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id 555system.cpu.icache.tags.age_task_id_blocks_1024::3 803 # Occupied blocks per task id 556system.cpu.icache.tags.age_task_id_blocks_1024::4 1117 # Occupied blocks per task id | 551system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 552system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 553system.cpu.icache.tags.age_task_id_blocks_1024::3 730 # Occupied blocks per task id 554system.cpu.icache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id |
| 557system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id | 555system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id |
| 558system.cpu.icache.tags.tag_accesses 50300884 # Number of tag accesses 559system.cpu.icache.tags.data_accesses 50300884 # Number of data accesses 560system.cpu.icache.ReadReq_hits::cpu.inst 25083355 # number of ReadReq hits 561system.cpu.icache.ReadReq_hits::total 25083355 # number of ReadReq hits 562system.cpu.icache.demand_hits::cpu.inst 25083355 # number of demand (read+write) hits 563system.cpu.icache.demand_hits::total 25083355 # number of demand (read+write) hits 564system.cpu.icache.overall_hits::cpu.inst 25083355 # number of overall hits 565system.cpu.icache.overall_hits::total 25083355 # number of overall hits 566system.cpu.icache.ReadReq_misses::cpu.inst 44725 # number of ReadReq misses 567system.cpu.icache.ReadReq_misses::total 44725 # number of ReadReq misses 568system.cpu.icache.demand_misses::cpu.inst 44725 # number of demand (read+write) misses 569system.cpu.icache.demand_misses::total 44725 # number of demand (read+write) misses 570system.cpu.icache.overall_misses::cpu.inst 44725 # number of overall misses 571system.cpu.icache.overall_misses::total 44725 # number of overall misses 572system.cpu.icache.ReadReq_miss_latency::cpu.inst 895927489 # number of ReadReq miss cycles 573system.cpu.icache.ReadReq_miss_latency::total 895927489 # number of ReadReq miss cycles 574system.cpu.icache.demand_miss_latency::cpu.inst 895927489 # number of demand (read+write) miss cycles 575system.cpu.icache.demand_miss_latency::total 895927489 # number of demand (read+write) miss cycles 576system.cpu.icache.overall_miss_latency::cpu.inst 895927489 # number of overall miss cycles 577system.cpu.icache.overall_miss_latency::total 895927489 # number of overall miss cycles 578system.cpu.icache.ReadReq_accesses::cpu.inst 25128080 # number of ReadReq accesses(hits+misses) 579system.cpu.icache.ReadReq_accesses::total 25128080 # number of ReadReq accesses(hits+misses) 580system.cpu.icache.demand_accesses::cpu.inst 25128080 # number of demand (read+write) accesses 581system.cpu.icache.demand_accesses::total 25128080 # number of demand (read+write) accesses 582system.cpu.icache.overall_accesses::cpu.inst 25128080 # number of overall (read+write) accesses 583system.cpu.icache.overall_accesses::total 25128080 # number of overall (read+write) accesses 584system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses 585system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses 586system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses 587system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses 588system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses 589system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses 590system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20031.917026 # average ReadReq miss latency 591system.cpu.icache.ReadReq_avg_miss_latency::total 20031.917026 # average ReadReq miss latency 592system.cpu.icache.demand_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency 593system.cpu.icache.demand_avg_miss_latency::total 20031.917026 # average overall miss latency 594system.cpu.icache.overall_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency 595system.cpu.icache.overall_avg_miss_latency::total 20031.917026 # average overall miss latency | 556system.cpu.icache.tags.tag_accesses 50321354 # Number of tag accesses 557system.cpu.icache.tags.data_accesses 50321354 # Number of data accesses 558system.cpu.icache.ReadReq_hits::cpu.inst 25093452 # number of ReadReq hits 559system.cpu.icache.ReadReq_hits::total 25093452 # number of ReadReq hits 560system.cpu.icache.demand_hits::cpu.inst 25093452 # number of demand (read+write) hits 561system.cpu.icache.demand_hits::total 25093452 # number of demand (read+write) hits 562system.cpu.icache.overall_hits::cpu.inst 25093452 # number of overall hits 563system.cpu.icache.overall_hits::total 25093452 # number of overall hits 564system.cpu.icache.ReadReq_misses::cpu.inst 44817 # number of ReadReq misses 565system.cpu.icache.ReadReq_misses::total 44817 # number of ReadReq misses 566system.cpu.icache.demand_misses::cpu.inst 44817 # number of demand (read+write) misses 567system.cpu.icache.demand_misses::total 44817 # number of demand (read+write) misses 568system.cpu.icache.overall_misses::cpu.inst 44817 # number of overall misses 569system.cpu.icache.overall_misses::total 44817 # number of overall misses 570system.cpu.icache.ReadReq_miss_latency::cpu.inst 937886990 # number of ReadReq miss cycles 571system.cpu.icache.ReadReq_miss_latency::total 937886990 # number of ReadReq miss cycles 572system.cpu.icache.demand_miss_latency::cpu.inst 937886990 # number of demand (read+write) miss cycles 573system.cpu.icache.demand_miss_latency::total 937886990 # number of demand (read+write) miss cycles 574system.cpu.icache.overall_miss_latency::cpu.inst 937886990 # number of overall miss cycles 575system.cpu.icache.overall_miss_latency::total 937886990 # number of overall miss cycles 576system.cpu.icache.ReadReq_accesses::cpu.inst 25138269 # number of ReadReq accesses(hits+misses) 577system.cpu.icache.ReadReq_accesses::total 25138269 # number of ReadReq accesses(hits+misses) 578system.cpu.icache.demand_accesses::cpu.inst 25138269 # number of demand (read+write) accesses 579system.cpu.icache.demand_accesses::total 25138269 # number of demand (read+write) accesses 580system.cpu.icache.overall_accesses::cpu.inst 25138269 # number of overall (read+write) accesses 581system.cpu.icache.overall_accesses::total 25138269 # number of overall (read+write) accesses 582system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001783 # miss rate for ReadReq accesses 583system.cpu.icache.ReadReq_miss_rate::total 0.001783 # miss rate for ReadReq accesses 584system.cpu.icache.demand_miss_rate::cpu.inst 0.001783 # miss rate for demand accesses 585system.cpu.icache.demand_miss_rate::total 0.001783 # miss rate for demand accesses 586system.cpu.icache.overall_miss_rate::cpu.inst 0.001783 # miss rate for overall accesses 587system.cpu.icache.overall_miss_rate::total 0.001783 # miss rate for overall accesses 588system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.036392 # average ReadReq miss latency 589system.cpu.icache.ReadReq_avg_miss_latency::total 20927.036392 # average ReadReq miss latency 590system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency 591system.cpu.icache.demand_avg_miss_latency::total 20927.036392 # average overall miss latency 592system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency 593system.cpu.icache.overall_avg_miss_latency::total 20927.036392 # average overall miss latency |
| 596system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 597system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 598system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 599system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 600system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 601system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 602system.cpu.icache.fast_writes 0 # number of fast writes performed 603system.cpu.icache.cache_copies 0 # number of cache copies performed | 594system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 595system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 596system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 597system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 598system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 599system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 600system.cpu.icache.fast_writes 0 # number of fast writes performed 601system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 604system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44725 # number of ReadReq MSHR misses 605system.cpu.icache.ReadReq_mshr_misses::total 44725 # number of ReadReq MSHR misses 606system.cpu.icache.demand_mshr_misses::cpu.inst 44725 # number of demand (read+write) MSHR misses 607system.cpu.icache.demand_mshr_misses::total 44725 # number of demand (read+write) MSHR misses 608system.cpu.icache.overall_mshr_misses::cpu.inst 44725 # number of overall MSHR misses 609system.cpu.icache.overall_mshr_misses::total 44725 # number of overall MSHR misses 610system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804564511 # number of ReadReq MSHR miss cycles 611system.cpu.icache.ReadReq_mshr_miss_latency::total 804564511 # number of ReadReq MSHR miss cycles 612system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804564511 # number of demand (read+write) MSHR miss cycles 613system.cpu.icache.demand_mshr_miss_latency::total 804564511 # number of demand (read+write) MSHR miss cycles 614system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804564511 # number of overall MSHR miss cycles 615system.cpu.icache.overall_mshr_miss_latency::total 804564511 # number of overall MSHR miss cycles 616system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses 617system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses 618system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses 619system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses 620system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses 621system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses 622system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17989.145020 # average ReadReq mshr miss latency 623system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17989.145020 # average ReadReq mshr miss latency 624system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency 625system.cpu.icache.demand_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency 626system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency 627system.cpu.icache.overall_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency | 602system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44817 # number of ReadReq MSHR misses 603system.cpu.icache.ReadReq_mshr_misses::total 44817 # number of ReadReq MSHR misses 604system.cpu.icache.demand_mshr_misses::cpu.inst 44817 # number of demand (read+write) MSHR misses 605system.cpu.icache.demand_mshr_misses::total 44817 # number of demand (read+write) MSHR misses 606system.cpu.icache.overall_mshr_misses::cpu.inst 44817 # number of overall MSHR misses 607system.cpu.icache.overall_mshr_misses::total 44817 # number of overall MSHR misses 608system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 868759010 # number of ReadReq MSHR miss cycles 609system.cpu.icache.ReadReq_mshr_miss_latency::total 868759010 # number of ReadReq MSHR miss cycles 610system.cpu.icache.demand_mshr_miss_latency::cpu.inst 868759010 # number of demand (read+write) MSHR miss cycles 611system.cpu.icache.demand_mshr_miss_latency::total 868759010 # number of demand (read+write) MSHR miss cycles 612system.cpu.icache.overall_mshr_miss_latency::cpu.inst 868759010 # number of overall MSHR miss cycles 613system.cpu.icache.overall_mshr_miss_latency::total 868759010 # number of overall MSHR miss cycles 614system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for ReadReq accesses 615system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001783 # mshr miss rate for ReadReq accesses 616system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for demand accesses 617system.cpu.icache.demand_mshr_miss_rate::total 0.001783 # mshr miss rate for demand accesses 618system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for overall accesses 619system.cpu.icache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses 620system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19384.586429 # average ReadReq mshr miss latency 621system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19384.586429 # average ReadReq mshr miss latency 622system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency 623system.cpu.icache.demand_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency 624system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency 625system.cpu.icache.overall_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency |
| 628system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 629system.cpu.l2cache.tags.replacements 95733 # number of replacements | 626system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 627system.cpu.l2cache.tags.replacements 95733 # number of replacements |
| 630system.cpu.l2cache.tags.tagsinuse 29936.958460 # Cycle average of tags in use 631system.cpu.l2cache.tags.total_refs 99697 # Total number of references to valid blocks. 632system.cpu.l2cache.tags.sampled_refs 126852 # Sample count of references to valid blocks. 633system.cpu.l2cache.tags.avg_refs 0.785932 # Average number of references to valid blocks. | 628system.cpu.l2cache.tags.tagsinuse 29885.598621 # Cycle average of tags in use 629system.cpu.l2cache.tags.total_refs 99802 # Total number of references to valid blocks. 630system.cpu.l2cache.tags.sampled_refs 126851 # Sample count of references to valid blocks. 631system.cpu.l2cache.tags.avg_refs 0.786766 # Average number of references to valid blocks. |
| 634system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 632system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 635system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor 636system.cpu.l2cache.tags.occ_blocks::cpu.inst 1563.058609 # Average occupied blocks per requestor 637system.cpu.l2cache.tags.occ_blocks::cpu.data 1666.382853 # Average occupied blocks per requestor 638system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # Average percentage of cache occupancy 639system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047701 # Average percentage of cache occupancy 640system.cpu.l2cache.tags.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy 641system.cpu.l2cache.tags.occ_percent::total 0.913603 # Average percentage of cache occupancy 642system.cpu.l2cache.tags.occ_task_id_blocks::1024 31119 # Occupied blocks per task id 643system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 644system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1137 # Occupied blocks per task id 645system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9778 # Occupied blocks per task id 646system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19493 # Occupied blocks per task id 647system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id 648system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949677 # Percentage of cache occupancy per task id 649system.cpu.l2cache.tags.tag_accesses 2903408 # Number of tag accesses 650system.cpu.l2cache.tags.data_accesses 2903408 # Number of data accesses 651system.cpu.l2cache.ReadReq_hits::cpu.inst 39644 # number of ReadReq hits 652system.cpu.l2cache.ReadReq_hits::cpu.data 31904 # number of ReadReq hits 653system.cpu.l2cache.ReadReq_hits::total 71548 # number of ReadReq hits 654system.cpu.l2cache.Writeback_hits::writebacks 128441 # number of Writeback hits 655system.cpu.l2cache.Writeback_hits::total 128441 # number of Writeback hits 656system.cpu.l2cache.ReadExReq_hits::cpu.data 4755 # number of ReadExReq hits 657system.cpu.l2cache.ReadExReq_hits::total 4755 # number of ReadExReq hits 658system.cpu.l2cache.demand_hits::cpu.inst 39644 # number of demand (read+write) hits 659system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits 660system.cpu.l2cache.demand_hits::total 76303 # number of demand (read+write) hits 661system.cpu.l2cache.overall_hits::cpu.inst 39644 # number of overall hits 662system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits 663system.cpu.l2cache.overall_hits::total 76303 # number of overall hits 664system.cpu.l2cache.ReadReq_misses::cpu.inst 5081 # number of ReadReq misses 665system.cpu.l2cache.ReadReq_misses::cpu.data 21584 # number of ReadReq misses | 633system.cpu.l2cache.tags.occ_blocks::writebacks 26636.535052 # Average occupied blocks per requestor 634system.cpu.l2cache.tags.occ_blocks::cpu.inst 1559.339588 # Average occupied blocks per requestor 635system.cpu.l2cache.tags.occ_blocks::cpu.data 1689.723980 # Average occupied blocks per requestor 636system.cpu.l2cache.tags.occ_percent::writebacks 0.812883 # Average percentage of cache occupancy 637system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047587 # Average percentage of cache occupancy 638system.cpu.l2cache.tags.occ_percent::cpu.data 0.051566 # Average percentage of cache occupancy 639system.cpu.l2cache.tags.occ_percent::total 0.912036 # Average percentage of cache occupancy 640system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id 641system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 642system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1015 # Occupied blocks per task id 643system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9129 # Occupied blocks per task id 644system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20264 # Occupied blocks per task id 645system.cpu.l2cache.tags.age_task_id_blocks_1024::4 591 # Occupied blocks per task id 646system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id 647system.cpu.l2cache.tags.tag_accesses 2904221 # Number of tag accesses 648system.cpu.l2cache.tags.data_accesses 2904221 # Number of data accesses 649system.cpu.l2cache.ReadReq_hits::cpu.inst 39738 # number of ReadReq hits 650system.cpu.l2cache.ReadReq_hits::cpu.data 31910 # number of ReadReq hits 651system.cpu.l2cache.ReadReq_hits::total 71648 # number of ReadReq hits 652system.cpu.l2cache.Writeback_hits::writebacks 128445 # number of Writeback hits 653system.cpu.l2cache.Writeback_hits::total 128445 # number of Writeback hits 654system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits 655system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits 656system.cpu.l2cache.demand_hits::cpu.inst 39738 # number of demand (read+write) hits 657system.cpu.l2cache.demand_hits::cpu.data 36664 # number of demand (read+write) hits 658system.cpu.l2cache.demand_hits::total 76402 # number of demand (read+write) hits 659system.cpu.l2cache.overall_hits::cpu.inst 39738 # number of overall hits 660system.cpu.l2cache.overall_hits::cpu.data 36664 # number of overall hits 661system.cpu.l2cache.overall_hits::total 76402 # number of overall hits 662system.cpu.l2cache.ReadReq_misses::cpu.inst 5079 # number of ReadReq misses 663system.cpu.l2cache.ReadReq_misses::cpu.data 21586 # number of ReadReq misses |
| 666system.cpu.l2cache.ReadReq_misses::total 26665 # number of ReadReq misses | 664system.cpu.l2cache.ReadReq_misses::total 26665 # number of ReadReq misses |
| 667system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses 668system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses 669system.cpu.l2cache.demand_misses::cpu.inst 5081 # number of demand (read+write) misses 670system.cpu.l2cache.demand_misses::cpu.data 123865 # number of demand (read+write) misses 671system.cpu.l2cache.demand_misses::total 128946 # number of demand (read+write) misses 672system.cpu.l2cache.overall_misses::cpu.inst 5081 # number of overall misses 673system.cpu.l2cache.overall_misses::cpu.data 123865 # number of overall misses 674system.cpu.l2cache.overall_misses::total 128946 # number of overall misses 675system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 363309000 # number of ReadReq miss cycles 676system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1614754750 # number of ReadReq miss cycles 677system.cpu.l2cache.ReadReq_miss_latency::total 1978063750 # number of ReadReq miss cycles 678system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7455355000 # number of ReadExReq miss cycles 679system.cpu.l2cache.ReadExReq_miss_latency::total 7455355000 # number of ReadExReq miss cycles 680system.cpu.l2cache.demand_miss_latency::cpu.inst 363309000 # number of demand (read+write) miss cycles 681system.cpu.l2cache.demand_miss_latency::cpu.data 9070109750 # number of demand (read+write) miss cycles 682system.cpu.l2cache.demand_miss_latency::total 9433418750 # number of demand (read+write) miss cycles 683system.cpu.l2cache.overall_miss_latency::cpu.inst 363309000 # number of overall miss cycles 684system.cpu.l2cache.overall_miss_latency::cpu.data 9070109750 # number of overall miss cycles 685system.cpu.l2cache.overall_miss_latency::total 9433418750 # number of overall miss cycles 686system.cpu.l2cache.ReadReq_accesses::cpu.inst 44725 # number of ReadReq accesses(hits+misses) 687system.cpu.l2cache.ReadReq_accesses::cpu.data 53488 # number of ReadReq accesses(hits+misses) 688system.cpu.l2cache.ReadReq_accesses::total 98213 # number of ReadReq accesses(hits+misses) 689system.cpu.l2cache.Writeback_accesses::writebacks 128441 # number of Writeback accesses(hits+misses) 690system.cpu.l2cache.Writeback_accesses::total 128441 # number of Writeback accesses(hits+misses) 691system.cpu.l2cache.ReadExReq_accesses::cpu.data 107036 # number of ReadExReq accesses(hits+misses) 692system.cpu.l2cache.ReadExReq_accesses::total 107036 # number of ReadExReq accesses(hits+misses) 693system.cpu.l2cache.demand_accesses::cpu.inst 44725 # number of demand (read+write) accesses 694system.cpu.l2cache.demand_accesses::cpu.data 160524 # number of demand (read+write) accesses 695system.cpu.l2cache.demand_accesses::total 205249 # number of demand (read+write) accesses 696system.cpu.l2cache.overall_accesses::cpu.inst 44725 # number of overall (read+write) accesses 697system.cpu.l2cache.overall_accesses::cpu.data 160524 # number of overall (read+write) accesses 698system.cpu.l2cache.overall_accesses::total 205249 # number of overall (read+write) accesses 699system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113605 # miss rate for ReadReq accesses 700system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403530 # miss rate for ReadReq accesses 701system.cpu.l2cache.ReadReq_miss_rate::total 0.271502 # miss rate for ReadReq accesses 702system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955576 # miss rate for ReadExReq accesses 703system.cpu.l2cache.ReadExReq_miss_rate::total 0.955576 # miss rate for ReadExReq accesses 704system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113605 # miss rate for demand accesses 705system.cpu.l2cache.demand_miss_rate::cpu.data 0.771629 # miss rate for demand accesses 706system.cpu.l2cache.demand_miss_rate::total 0.628242 # miss rate for demand accesses 707system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113605 # miss rate for overall accesses 708system.cpu.l2cache.overall_miss_rate::cpu.data 0.771629 # miss rate for overall accesses 709system.cpu.l2cache.overall_miss_rate::total 0.628242 # miss rate for overall accesses 710system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71503.444204 # average ReadReq miss latency 711system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74812.581079 # average ReadReq miss latency 712system.cpu.l2cache.ReadReq_avg_miss_latency::total 74182.027002 # average ReadReq miss latency 713system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72890.908380 # average ReadExReq miss latency 714system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.908380 # average ReadExReq miss latency 715system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency 716system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency 717system.cpu.l2cache.demand_avg_miss_latency::total 73157.901370 # average overall miss latency 718system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency 719system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency 720system.cpu.l2cache.overall_avg_miss_latency::total 73157.901370 # average overall miss latency | 665system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses 666system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses 667system.cpu.l2cache.demand_misses::cpu.inst 5079 # number of demand (read+write) misses 668system.cpu.l2cache.demand_misses::cpu.data 123866 # number of demand (read+write) misses 669system.cpu.l2cache.demand_misses::total 128945 # number of demand (read+write) misses 670system.cpu.l2cache.overall_misses::cpu.inst 5079 # number of overall misses 671system.cpu.l2cache.overall_misses::cpu.data 123866 # number of overall misses 672system.cpu.l2cache.overall_misses::total 128945 # number of overall misses 673system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 406663000 # number of ReadReq miss cycles 674system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1774587250 # number of ReadReq miss cycles 675system.cpu.l2cache.ReadReq_miss_latency::total 2181250250 # number of ReadReq miss cycles 676system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8245411750 # number of ReadExReq miss cycles 677system.cpu.l2cache.ReadExReq_miss_latency::total 8245411750 # number of ReadExReq miss cycles 678system.cpu.l2cache.demand_miss_latency::cpu.inst 406663000 # number of demand (read+write) miss cycles 679system.cpu.l2cache.demand_miss_latency::cpu.data 10019999000 # number of demand (read+write) miss cycles 680system.cpu.l2cache.demand_miss_latency::total 10426662000 # number of demand (read+write) miss cycles 681system.cpu.l2cache.overall_miss_latency::cpu.inst 406663000 # number of overall miss cycles 682system.cpu.l2cache.overall_miss_latency::cpu.data 10019999000 # number of overall miss cycles 683system.cpu.l2cache.overall_miss_latency::total 10426662000 # number of overall miss cycles 684system.cpu.l2cache.ReadReq_accesses::cpu.inst 44817 # number of ReadReq accesses(hits+misses) 685system.cpu.l2cache.ReadReq_accesses::cpu.data 53496 # number of ReadReq accesses(hits+misses) 686system.cpu.l2cache.ReadReq_accesses::total 98313 # number of ReadReq accesses(hits+misses) 687system.cpu.l2cache.Writeback_accesses::writebacks 128445 # number of Writeback accesses(hits+misses) 688system.cpu.l2cache.Writeback_accesses::total 128445 # number of Writeback accesses(hits+misses) 689system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) 690system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) 691system.cpu.l2cache.demand_accesses::cpu.inst 44817 # number of demand (read+write) accesses 692system.cpu.l2cache.demand_accesses::cpu.data 160530 # number of demand (read+write) accesses 693system.cpu.l2cache.demand_accesses::total 205347 # number of demand (read+write) accesses 694system.cpu.l2cache.overall_accesses::cpu.inst 44817 # number of overall (read+write) accesses 695system.cpu.l2cache.overall_accesses::cpu.data 160530 # number of overall (read+write) accesses 696system.cpu.l2cache.overall_accesses::total 205347 # number of overall (read+write) accesses 697system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113328 # miss rate for ReadReq accesses 698system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403507 # miss rate for ReadReq accesses 699system.cpu.l2cache.ReadReq_miss_rate::total 0.271226 # miss rate for ReadReq accesses 700system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955584 # miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_miss_rate::total 0.955584 # miss rate for ReadExReq accesses 702system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113328 # miss rate for demand accesses 703system.cpu.l2cache.demand_miss_rate::cpu.data 0.771607 # miss rate for demand accesses 704system.cpu.l2cache.demand_miss_rate::total 0.627937 # miss rate for demand accesses 705system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113328 # miss rate for overall accesses 706system.cpu.l2cache.overall_miss_rate::cpu.data 0.771607 # miss rate for overall accesses 707system.cpu.l2cache.overall_miss_rate::total 0.627937 # miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80067.532979 # average ReadReq miss latency 709system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82210.101455 # average ReadReq miss latency 710system.cpu.l2cache.ReadReq_avg_miss_latency::total 81801.997000 # average ReadReq miss latency 711system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80616.071079 # average ReadExReq miss latency 712system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80616.071079 # average ReadExReq miss latency 713system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80067.532979 # average overall miss latency 714system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80893.861108 # average overall miss latency 715system.cpu.l2cache.demand_avg_miss_latency::total 80861.312963 # average overall miss latency 716system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80067.532979 # average overall miss latency 717system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80893.861108 # average overall miss latency 718system.cpu.l2cache.overall_avg_miss_latency::total 80861.312963 # average overall miss latency |
| 721system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 722system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 725system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 726system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 727system.cpu.l2cache.fast_writes 0 # number of fast writes performed 728system.cpu.l2cache.cache_copies 0 # number of cache copies performed 729system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks 730system.cpu.l2cache.writebacks::total 83951 # number of writebacks 731system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits 732system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 733system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 734system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits 735system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits 736system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 737system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits 738system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits 739system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits | 719system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 720system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 722system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 724system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.l2cache.fast_writes 0 # number of fast writes performed 726system.cpu.l2cache.cache_copies 0 # number of cache copies performed 727system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks 728system.cpu.l2cache.writebacks::total 83951 # number of writebacks 729system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits 730system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 731system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 732system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits 733system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits 734system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 735system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits 736system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits 737system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits |
| 740system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5071 # number of ReadReq MSHR misses 741system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21521 # number of ReadReq MSHR misses | 738system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5069 # number of ReadReq MSHR misses 739system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21523 # number of ReadReq MSHR misses |
| 742system.cpu.l2cache.ReadReq_mshr_misses::total 26592 # number of ReadReq MSHR misses | 740system.cpu.l2cache.ReadReq_mshr_misses::total 26592 # number of ReadReq MSHR misses |
| 743system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses 744system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses 745system.cpu.l2cache.demand_mshr_misses::cpu.inst 5071 # number of demand (read+write) MSHR misses 746system.cpu.l2cache.demand_mshr_misses::cpu.data 123802 # number of demand (read+write) MSHR misses 747system.cpu.l2cache.demand_mshr_misses::total 128873 # number of demand (read+write) MSHR misses 748system.cpu.l2cache.overall_mshr_misses::cpu.inst 5071 # number of overall MSHR misses 749system.cpu.l2cache.overall_mshr_misses::cpu.data 123802 # number of overall MSHR misses 750system.cpu.l2cache.overall_mshr_misses::total 128873 # number of overall MSHR misses 751system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 298810000 # number of ReadReq MSHR miss cycles 752system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1336295500 # number of ReadReq MSHR miss cycles 753system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1635105500 # number of ReadReq MSHR miss cycles 754system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6164329000 # number of ReadExReq MSHR miss cycles 755system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6164329000 # number of ReadExReq MSHR miss cycles 756system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 298810000 # number of demand (read+write) MSHR miss cycles 757system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7500624500 # number of demand (read+write) MSHR miss cycles 758system.cpu.l2cache.demand_mshr_miss_latency::total 7799434500 # number of demand (read+write) MSHR miss cycles 759system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 298810000 # number of overall MSHR miss cycles 760system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7500624500 # number of overall MSHR miss cycles 761system.cpu.l2cache.overall_mshr_miss_latency::total 7799434500 # number of overall MSHR miss cycles 762system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for ReadReq accesses 763system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402352 # mshr miss rate for ReadReq accesses 764system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270758 # mshr miss rate for ReadReq accesses 765system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955576 # mshr miss rate for ReadExReq accesses 766system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955576 # mshr miss rate for ReadExReq accesses 767system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for demand accesses 768system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for demand accesses 769system.cpu.l2cache.demand_mshr_miss_rate::total 0.627886 # mshr miss rate for demand accesses 770system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for overall accesses 771system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for overall accesses 772system.cpu.l2cache.overall_mshr_miss_rate::total 0.627886 # mshr miss rate for overall accesses 773system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58925.261290 # average ReadReq mshr miss latency 774system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62092.630454 # average ReadReq mshr miss latency 775system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61488.624398 # average ReadReq mshr miss latency 776system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60268.564054 # average ReadExReq mshr miss latency 777system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60268.564054 # average ReadExReq mshr miss latency 778system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency 779system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency 780system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency 781system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency 782system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency 783system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency | 741system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses 742system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses 743system.cpu.l2cache.demand_mshr_misses::cpu.inst 5069 # number of demand (read+write) MSHR misses 744system.cpu.l2cache.demand_mshr_misses::cpu.data 123803 # number of demand (read+write) MSHR misses 745system.cpu.l2cache.demand_mshr_misses::total 128872 # number of demand (read+write) MSHR misses 746system.cpu.l2cache.overall_mshr_misses::cpu.inst 5069 # number of overall MSHR misses 747system.cpu.l2cache.overall_mshr_misses::cpu.data 123803 # number of overall MSHR misses 748system.cpu.l2cache.overall_mshr_misses::total 128872 # number of overall MSHR misses 749system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342505250 # number of ReadReq MSHR miss cycles 750system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1501079000 # number of ReadReq MSHR miss cycles 751system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1843584250 # number of ReadReq MSHR miss cycles 752system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6966637250 # number of ReadExReq MSHR miss cycles 753system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6966637250 # number of ReadExReq MSHR miss cycles 754system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342505250 # number of demand (read+write) MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8467716250 # number of demand (read+write) MSHR miss cycles 756system.cpu.l2cache.demand_mshr_miss_latency::total 8810221500 # number of demand (read+write) MSHR miss cycles 757system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342505250 # number of overall MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8467716250 # number of overall MSHR miss cycles 759system.cpu.l2cache.overall_mshr_miss_latency::total 8810221500 # number of overall MSHR miss cycles 760system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for ReadReq accesses 761system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402329 # mshr miss rate for ReadReq accesses 762system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270483 # mshr miss rate for ReadReq accesses 763system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955584 # mshr miss rate for ReadExReq accesses 764system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955584 # mshr miss rate for ReadExReq accesses 765system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for demand accesses 766system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::total 0.627582 # mshr miss rate for demand accesses 768system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for overall accesses 769system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::total 0.627582 # mshr miss rate for overall accesses 771system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67568.603275 # average ReadReq mshr miss latency 772system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69743.019096 # average ReadReq mshr miss latency 773system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69328.529257 # average ReadReq mshr miss latency 774system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68113.387270 # average ReadExReq mshr miss latency 775system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68113.387270 # average ReadExReq mshr miss latency 776system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency 778system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency 779system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency 781system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency |
| 784system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 782system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 785system.cpu.toL2Bus.trans_dist::ReadReq 98213 # Transaction distribution 786system.cpu.toL2Bus.trans_dist::ReadResp 98212 # Transaction distribution 787system.cpu.toL2Bus.trans_dist::Writeback 128441 # Transaction distribution 788system.cpu.toL2Bus.trans_dist::ReadExReq 107036 # Transaction distribution 789system.cpu.toL2Bus.trans_dist::ReadExResp 107036 # Transaction distribution 790system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89449 # Packet count per connected master and slave (bytes) 791system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449489 # Packet count per connected master and slave (bytes) 792system.cpu.toL2Bus.pkt_count::total 538938 # Packet count per connected master and slave (bytes) 793system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2862336 # Cumulative packet size per connected master and slave (bytes) 794system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18493760 # Cumulative packet size per connected master and slave (bytes) 795system.cpu.toL2Bus.pkt_size::total 21356096 # Cumulative packet size per connected master and slave (bytes) | 783system.cpu.toL2Bus.trans_dist::ReadReq 98313 # Transaction distribution 784system.cpu.toL2Bus.trans_dist::ReadResp 98312 # Transaction distribution 785system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution 786system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution 787system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution 788system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89633 # Packet count per connected master and slave (bytes) 789system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449505 # Packet count per connected master and slave (bytes) 790system.cpu.toL2Bus.pkt_count::total 539138 # Packet count per connected master and slave (bytes) 791system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2868224 # Cumulative packet size per connected master and slave (bytes) 792system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494400 # Cumulative packet size per connected master and slave (bytes) 793system.cpu.toL2Bus.pkt_size::total 21362624 # Cumulative packet size per connected master and slave (bytes) |
| 796system.cpu.toL2Bus.snoops 0 # Total snoops (count) | 794system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| 797system.cpu.toL2Bus.snoop_fanout::samples 333690 # Request fanout histogram 798system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram | 795system.cpu.toL2Bus.snoop_fanout::samples 333792 # Request fanout histogram 796system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram |
| 799system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 800system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 801system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 802system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 803system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 797system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 798system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 799system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 800system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 801system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 804system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 805system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 806system.cpu.toL2Bus.snoop_fanout::5 333690 100.00% 100.00% # Request fanout histogram 807system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram | 802system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram 803system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| 808system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 804system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 809system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 810system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 811system.cpu.toL2Bus.snoop_fanout::total 333690 # Request fanout histogram 812system.cpu.toL2Bus.reqLayer0.occupancy 295286000 # Layer occupancy (ticks) | 805system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 806system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 807system.cpu.toL2Bus.snoop_fanout::total 333792 # Request fanout histogram 808system.cpu.toL2Bus.reqLayer0.occupancy 295341000 # Layer occupancy (ticks) |
| 813system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) | 809system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) |
| 814system.cpu.toL2Bus.respLayer0.occupancy 68043489 # Layer occupancy (ticks) | 810system.cpu.toL2Bus.respLayer0.occupancy 68175990 # Layer occupancy (ticks) |
| 815system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 811system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 816system.cpu.toL2Bus.respLayer1.occupancy 268450687 # Layer occupancy (ticks) | 812system.cpu.toL2Bus.respLayer1.occupancy 268644937 # Layer occupancy (ticks) |
| 817system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 818system.membus.trans_dist::ReadReq 26591 # Transaction distribution 819system.membus.trans_dist::ReadResp 26591 # Transaction distribution 820system.membus.trans_dist::Writeback 83951 # Transaction distribution | 813system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 814system.membus.trans_dist::ReadReq 26591 # Transaction distribution 815system.membus.trans_dist::ReadResp 26591 # Transaction distribution 816system.membus.trans_dist::Writeback 83951 # Transaction distribution |
| 821system.membus.trans_dist::ReadExReq 102281 # Transaction distribution 822system.membus.trans_dist::ReadExResp 102281 # Transaction distribution 823system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341695 # Packet count per connected master and slave (bytes) 824system.membus.pkt_count::total 341695 # Packet count per connected master and slave (bytes) 825system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620672 # Cumulative packet size per connected master and slave (bytes) 826system.membus.pkt_size::total 13620672 # Cumulative packet size per connected master and slave (bytes) | 817system.membus.trans_dist::ReadExReq 102280 # Transaction distribution 818system.membus.trans_dist::ReadExResp 102280 # Transaction distribution 819system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341693 # Packet count per connected master and slave (bytes) 820system.membus.pkt_count::total 341693 # Packet count per connected master and slave (bytes) 821system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620608 # Cumulative packet size per connected master and slave (bytes) 822system.membus.pkt_size::total 13620608 # Cumulative packet size per connected master and slave (bytes) |
| 827system.membus.snoops 0 # Total snoops (count) | 823system.membus.snoops 0 # Total snoops (count) |
| 828system.membus.snoop_fanout::samples 212823 # Request fanout histogram | 824system.membus.snoop_fanout::samples 212822 # Request fanout histogram |
| 829system.membus.snoop_fanout::mean 0 # Request fanout histogram 830system.membus.snoop_fanout::stdev 0 # Request fanout histogram 831system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 825system.membus.snoop_fanout::mean 0 # Request fanout histogram 826system.membus.snoop_fanout::stdev 0 # Request fanout histogram 827system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 832system.membus.snoop_fanout::0 212823 100.00% 100.00% # Request fanout histogram | 828system.membus.snoop_fanout::0 212822 100.00% 100.00% # Request fanout histogram |
| 833system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 834system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 835system.membus.snoop_fanout::min_value 0 # Request fanout histogram 836system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 829system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 830system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 831system.membus.snoop_fanout::min_value 0 # Request fanout histogram 832system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 837system.membus.snoop_fanout::total 212823 # Request fanout histogram 838system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks) 839system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) 840system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks) 841system.membus.respLayer1.utilization 2.1 # Layer utilization (%) | 833system.membus.snoop_fanout::total 212822 # Request fanout histogram 834system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks) 835system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) 836system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks) 837system.membus.respLayer1.utilization 1.2 # Layer utilization (%) |
| 842 843---------- End Simulation Statistics ---------- | 838 839---------- End Simulation Statistics ---------- |