| stats.txt (10261:dc198e224a85) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.064367 # Number of seconds simulated 4sim_ticks 64366581500 # Number of ticks simulated 5final_tick 64366581500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.056337 # Number of seconds simulated 4sim_ticks 56337328500 # Number of ticks simulated 5final_tick 56337328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 99170 # Simulator instruction rate (inst/s) 8host_op_rate 140730 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 90012135 # Simulator tick rate (ticks/s) 10host_mem_usage 295432 # Number of bytes of host memory used 11host_seconds 715.09 # Real time elapsed on the host | 7host_inst_rate 184341 # Simulator instruction rate (inst/s) 8host_op_rate 235745 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 146446418 # Simulator tick rate (ticks/s) 10host_mem_usage 326872 # Number of bytes of host memory used 11host_seconds 384.70 # Real time elapsed on the host |
| 12sim_insts 70915127 # Number of instructions simulated | 12sim_insts 70915127 # Number of instructions simulated |
| 13sim_ops 100634375 # Number of ops (including micro ops) simulated | 13sim_ops 90690083 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory 17system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory 21system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 128317021 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 128317021 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 83478847 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 128317021 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 211795868 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 129052 # Number of read requests accepted 36system.physmem.writeReqs 83957 # Number of write requests accepted 37system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 8258880 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue 41system.physmem.bytesWritten 5371584 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 5373248 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 8247168 # Number of bytes read from this memory 17system.physmem.bytes_read::total 8247168 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 323904 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 323904 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory 21system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 128862 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 146389050 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 146389050 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 5749367 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 5749367 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 95369520 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 95369520 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 95369520 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 146389050 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 241758570 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 128862 # Number of read requests accepted 36system.physmem.writeReqs 83951 # Number of write requests accepted 37system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue 41system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue |
| 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 47system.physmem.perBankRdBursts::0 8196 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8381 # Per bank write bursts 49system.physmem.perBankRdBursts::2 8249 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8185 # Per bank write bursts 51system.physmem.perBankRdBursts::4 8327 # Per bank write bursts 52system.physmem.perBankRdBursts::5 8459 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8094 # Per bank write bursts 54system.physmem.perBankRdBursts::7 7981 # Per bank write bursts 55system.physmem.perBankRdBursts::8 8076 # Per bank write bursts 56system.physmem.perBankRdBursts::9 7644 # Per bank write bursts 57system.physmem.perBankRdBursts::10 7831 # Per bank write bursts 58system.physmem.perBankRdBursts::11 7843 # Per bank write bursts 59system.physmem.perBankRdBursts::12 7891 # Per bank write bursts 60system.physmem.perBankRdBursts::13 7884 # Per bank write bursts 61system.physmem.perBankRdBursts::14 7977 # Per bank write bursts 62system.physmem.perBankRdBursts::15 8027 # Per bank write bursts 63system.physmem.perBankWrBursts::0 5181 # Per bank write bursts 64system.physmem.perBankWrBursts::1 5375 # Per bank write bursts 65system.physmem.perBankWrBursts::2 5284 # Per bank write bursts | 47system.physmem.perBankRdBursts::0 8164 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8373 # Per bank write bursts 49system.physmem.perBankRdBursts::2 8238 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8169 # Per bank write bursts 51system.physmem.perBankRdBursts::4 8316 # Per bank write bursts 52system.physmem.perBankRdBursts::5 8449 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8089 # Per bank write bursts 54system.physmem.perBankRdBursts::7 7969 # Per bank write bursts 55system.physmem.perBankRdBursts::8 8071 # Per bank write bursts 56system.physmem.perBankRdBursts::9 7635 # Per bank write bursts 57system.physmem.perBankRdBursts::10 7816 # Per bank write bursts 58system.physmem.perBankRdBursts::11 7830 # Per bank write bursts 59system.physmem.perBankRdBursts::12 7881 # Per bank write bursts 60system.physmem.perBankRdBursts::13 7876 # Per bank write bursts 61system.physmem.perBankRdBursts::14 7976 # Per bank write bursts 62system.physmem.perBankRdBursts::15 8004 # Per bank write bursts 63system.physmem.perBankWrBursts::0 5182 # Per bank write bursts 64system.physmem.perBankWrBursts::1 5376 # Per bank write bursts 65system.physmem.perBankWrBursts::2 5285 # Per bank write bursts |
| 66system.physmem.perBankWrBursts::3 5155 # Per bank write bursts 67system.physmem.perBankWrBursts::4 5265 # Per bank write bursts 68system.physmem.perBankWrBursts::5 5517 # Per bank write bursts | 66system.physmem.perBankWrBursts::3 5155 # Per bank write bursts 67system.physmem.perBankWrBursts::4 5265 # Per bank write bursts 68system.physmem.perBankWrBursts::5 5517 # Per bank write bursts |
| 69system.physmem.perBankWrBursts::6 5201 # Per bank write bursts 70system.physmem.perBankWrBursts::7 5050 # Per bank write bursts 71system.physmem.perBankWrBursts::8 5034 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5087 # Per bank write bursts 73system.physmem.perBankWrBursts::10 5251 # Per bank write bursts 74system.physmem.perBankWrBursts::11 5146 # Per bank write bursts 75system.physmem.perBankWrBursts::12 5344 # Per bank write bursts | 69system.physmem.perBankWrBursts::6 5198 # Per bank write bursts 70system.physmem.perBankWrBursts::7 5049 # Per bank write bursts 71system.physmem.perBankWrBursts::8 5033 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5086 # Per bank write bursts 73system.physmem.perBankWrBursts::10 5252 # Per bank write bursts 74system.physmem.perBankWrBursts::11 5143 # Per bank write bursts 75system.physmem.perBankWrBursts::12 5343 # Per bank write bursts |
| 76system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5451 # Per bank write bursts | 76system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5451 # Per bank write bursts |
| 78system.physmem.perBankWrBursts::15 5227 # Per bank write bursts | 78system.physmem.perBankWrBursts::15 5224 # Per bank write bursts |
| 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 81system.physmem.totGap 64366550000 # Total gap between requests | 81system.physmem.totGap 56337297000 # Total gap between requests |
| 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) | 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 88system.physmem.readPktSize::6 129052 # Read request sizes (log2) | 88system.physmem.readPktSize::6 128862 # Read request sizes (log2) |
| 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) | 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 95system.physmem.writePktSize::6 83957 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 128466 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see | 95system.physmem.writePktSize::6 83951 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 126556 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 2278 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 143system.physmem.wrQLenPdf::15 633 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 4312 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 5147 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 5162 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 5167 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 5171 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 5182 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 5366 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 5212 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 5234 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 5667 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 5208 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::15 610 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 624 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 4267 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 5149 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 5182 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 5177 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 5179 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 5351 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 5232 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 5687 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 5245 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 5159 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 192system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 212.918314 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 334.655421 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 2767 7.13% 71.07% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2567 6.61% 77.68% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1675 4.31% 82.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 1312 3.38% 85.38% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 1197 3.08% 88.46% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 4479 11.54% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes | 192system.physmem.bytesPerActivate::samples 38348 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 355.034109 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 215.640084 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 336.462166 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 12103 31.56% 31.56% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 8116 21.16% 52.73% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 4102 10.70% 63.42% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 2869 7.48% 70.90% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2471 6.44% 77.35% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1658 4.32% 81.67% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 1256 3.28% 84.95% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 1197 3.12% 88.07% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 4576 11.93% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 38348 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 24.976149 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 361.694607 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes |
| 210system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes | 210system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes |
| 211system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes 214system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads | 211system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes 214system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::mean 16.273415 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::gmean 16.256579 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::stdev 0.772702 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::16 4535 87.94% 87.94% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::17 9 0.17% 88.11% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::18 476 9.23% 97.34% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::19 113 2.19% 99.53% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::20 16 0.31% 99.84% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::21 5 0.10% 99.94% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads |
| 227system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads | 225system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads |
| 228system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads 229system.physmem.totQLat 1458157250 # Total ticks spent queuing 230system.physmem.totMemAccLat 3877751000 # Total ticks spent from burst creation until serviced by the DRAM 231system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers 232system.physmem.avgQLat 11299.60 # Average queueing delay per DRAM burst | 226system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads 227system.physmem.totQLat 1494390000 # Total ticks spent queuing 228system.physmem.totMemAccLat 3910440000 # Total ticks spent from burst creation until serviced by the DRAM 229system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers 230system.physmem.avgQLat 11597.36 # Average queueing delay per DRAM burst |
| 233system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 231system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 234system.physmem.avgMemAccLat 30049.60 # Average memory access latency per DRAM burst 235system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s 236system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s 237system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s 238system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s | 232system.physmem.avgMemAccLat 30347.36 # Average memory access latency per DRAM burst 233system.physmem.avgRdBW 146.38 # Average DRAM read bandwidth in MiByte/s 234system.physmem.avgWrBW 95.34 # Average achieved write bandwidth in MiByte/s 235system.physmem.avgRdBWSys 146.39 # Average system read bandwidth in MiByte/s 236system.physmem.avgWrBWSys 95.37 # Average system write bandwidth in MiByte/s |
| 239system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 237system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 240system.physmem.busUtil 1.65 # Data bus utilization in percentage 241system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads 242system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes | 238system.physmem.busUtil 1.89 # Data bus utilization in percentage 239system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads 240system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes |
| 243system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing | 241system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing |
| 244system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing 245system.physmem.readRowHits 112129 # Number of row buffer hits during reads 246system.physmem.writeRowHits 62016 # Number of row buffer hits during writes 247system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads 248system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes 249system.physmem.avgGap 302177.61 # Average gap between requests 250system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined 251system.physmem.memoryStateTime::IDLE 37447706500 # Time in different power states 252system.physmem.memoryStateTime::REF 2149160000 # Time in different power states | 242system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing 243system.physmem.readRowHits 112251 # Number of row buffer hits during reads 244system.physmem.writeRowHits 62167 # Number of row buffer hits during writes 245system.physmem.readRowHitRate 87.11 # Row buffer hit rate for reads 246system.physmem.writeRowHitRate 74.05 # Row buffer hit rate for writes 247system.physmem.avgGap 264726.76 # Average gap between requests 248system.physmem.pageHitRate 81.96 # Row buffer hit rate, read and write combined 249system.physmem.memoryStateTime::IDLE 31175393250 # Time in different power states 250system.physmem.memoryStateTime::REF 1881100000 # Time in different power states |
| 253system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 251system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 254system.physmem.memoryStateTime::ACT 24764549750 # Time in different power states | 252system.physmem.memoryStateTime::ACT 23277299250 # Time in different power states |
| 255system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 253system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 256system.membus.throughput 211795868 # Throughput (bytes/s) 257system.membus.trans_dist::ReadReq 26785 # Transaction distribution 258system.membus.trans_dist::ReadResp 26785 # Transaction distribution 259system.membus.trans_dist::Writeback 83957 # Transaction distribution 260system.membus.trans_dist::ReadExReq 102267 # Transaction distribution 261system.membus.trans_dist::ReadExResp 102267 # Transaction distribution 262system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) 263system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) 264system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) 265system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) 266system.membus.data_through_bus 13632576 # Total data (bytes) | 254system.membus.throughput 241758570 # Throughput (bytes/s) 255system.membus.trans_dist::ReadReq 26583 # Transaction distribution 256system.membus.trans_dist::ReadResp 26583 # Transaction distribution 257system.membus.trans_dist::Writeback 83951 # Transaction distribution 258system.membus.trans_dist::ReadExReq 102279 # Transaction distribution 259system.membus.trans_dist::ReadExResp 102279 # Transaction distribution 260system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes) 261system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes) 262system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes) 263system.membus.tot_pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes) 264system.membus.data_through_bus 13620032 # Total data (bytes) |
| 267system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 265system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 268system.membus.reqLayer0.occupancy 975516500 # Layer occupancy (ticks) 269system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) 270system.membus.respLayer1.occupancy 1243562250 # Layer occupancy (ticks) 271system.membus.respLayer1.utilization 1.9 # Layer utilization (%) | 266system.membus.reqLayer0.occupancy 942262500 # Layer occupancy (ticks) 267system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) 268system.membus.respLayer1.occupancy 1221459500 # Layer occupancy (ticks) 269system.membus.respLayer1.utilization 2.2 # Layer utilization (%) |
| 272system.cpu_clk_domain.clock 500 # Clock period in ticks | 270system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 273system.cpu.branchPred.lookups 16883830 # Number of BP lookups 274system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted 275system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect 276system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups 277system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits | 271system.cpu.branchPred.lookups 14808792 # Number of BP lookups 272system.cpu.branchPred.condPredicted 9910132 # Number of conditional branches predicted 273system.cpu.branchPred.condIncorrect 393085 # Number of conditional branches incorrect 274system.cpu.branchPred.BTBLookups 9534896 # Number of BTB lookups 275system.cpu.branchPred.BTBHits 6736289 # Number of BTB hits |
| 278system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 276system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 279system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage 280system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. 281system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. | 277system.cpu.branchPred.BTBHitPct 70.648794 # BTB Hit Percentage 278system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target. 279system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. |
| 282system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 283system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 284system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 285system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 286system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 287system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 288system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 289system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 359system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 360system.cpu.itb.read_accesses 0 # DTB read accesses 361system.cpu.itb.write_accesses 0 # DTB write accesses 362system.cpu.itb.inst_accesses 0 # ITB inst accesses 363system.cpu.itb.hits 0 # DTB hits 364system.cpu.itb.misses 0 # DTB misses 365system.cpu.itb.accesses 0 # DTB accesses 366system.cpu.workload.num_syscalls 1946 # Number of system calls | 280system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 281system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 282system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 283system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 284system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 285system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 286system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 287system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 357system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 358system.cpu.itb.read_accesses 0 # DTB read accesses 359system.cpu.itb.write_accesses 0 # DTB write accesses 360system.cpu.itb.inst_accesses 0 # ITB inst accesses 361system.cpu.itb.hits 0 # DTB hits 362system.cpu.itb.misses 0 # DTB misses 363system.cpu.itb.accesses 0 # DTB accesses 364system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 367system.cpu.numCycles 128733163 # number of cpu cycles simulated | 365system.cpu.numCycles 112674657 # number of cpu cycles simulated |
| 368system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 369system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 370system.cpu.committedInsts 70915127 # Number of instructions committed | 366system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 367system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 368system.cpu.committedInsts 70915127 # Number of instructions committed |
| 371system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed 372system.cpu.discardedOps 2952341 # Number of ops (including micro ops) which were discarded before commit | 369system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed 370system.cpu.discardedOps 1227274 # Number of ops (including micro ops) which were discarded before commit |
| 373system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 371system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 374system.cpu.cpi 1.815313 # CPI: cycles per instruction 375system.cpu.ipc 0.550869 # IPC: instructions per cycle 376system.cpu.tickCycles 109168240 # Number of cycles that the object actually ticked 377system.cpu.idleCycles 19564923 # Total number of cycles that the object has spent stopped 378system.cpu.icache.tags.replacements 43522 # number of replacements 379system.cpu.icache.tags.tagsinuse 1864.297124 # Cycle average of tags in use 380system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. 381system.cpu.icache.tags.sampled_refs 45564 # Sample count of references to valid blocks. 382system.cpu.icache.tags.avg_refs 601.951146 # Average number of references to valid blocks. | 372system.cpu.cpi 1.588866 # CPI: cycles per instruction 373system.cpu.ipc 0.629380 # IPC: instructions per cycle 374system.cpu.tickCycles 93712970 # Number of cycles that the object actually ticked 375system.cpu.idleCycles 18961687 # Total number of cycles that the object has spent stopped 376system.cpu.icache.tags.replacements 42434 # number of replacements 377system.cpu.icache.tags.tagsinuse 1857.452171 # Cycle average of tags in use 378system.cpu.icache.tags.total_refs 24948252 # Total number of references to valid blocks. 379system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks. 380system.cpu.icache.tags.avg_refs 560.937404 # Average number of references to valid blocks. |
| 383system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 381system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 384system.cpu.icache.tags.occ_blocks::cpu.inst 1864.297124 # Average occupied blocks per requestor 385system.cpu.icache.tags.occ_percent::cpu.inst 0.910301 # Average percentage of cache occupancy 386system.cpu.icache.tags.occ_percent::total 0.910301 # Average percentage of cache occupancy | 382system.cpu.icache.tags.occ_blocks::cpu.inst 1857.452171 # Average occupied blocks per requestor 383system.cpu.icache.tags.occ_percent::cpu.inst 0.906959 # Average percentage of cache occupancy 384system.cpu.icache.tags.occ_percent::total 0.906959 # Average percentage of cache occupancy |
| 387system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id | 385system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id |
| 388system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 389system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id 390system.cpu.icache.tags.age_task_id_blocks_1024::3 727 # Occupied blocks per task id 391system.cpu.icache.tags.age_task_id_blocks_1024::4 1194 # Occupied blocks per task id | 386system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id 387system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id 388system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id 389system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id |
| 392system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id | 390system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id |
| 393system.cpu.icache.tags.tag_accesses 54991298 # Number of tag accesses 394system.cpu.icache.tags.data_accesses 54991298 # Number of data accesses 395system.cpu.icache.ReadReq_hits::cpu.inst 27427302 # number of ReadReq hits 396system.cpu.icache.ReadReq_hits::total 27427302 # number of ReadReq hits 397system.cpu.icache.demand_hits::cpu.inst 27427302 # number of demand (read+write) hits 398system.cpu.icache.demand_hits::total 27427302 # number of demand (read+write) hits 399system.cpu.icache.overall_hits::cpu.inst 27427302 # number of overall hits 400system.cpu.icache.overall_hits::total 27427302 # number of overall hits 401system.cpu.icache.ReadReq_misses::cpu.inst 45565 # number of ReadReq misses 402system.cpu.icache.ReadReq_misses::total 45565 # number of ReadReq misses 403system.cpu.icache.demand_misses::cpu.inst 45565 # number of demand (read+write) misses 404system.cpu.icache.demand_misses::total 45565 # number of demand (read+write) misses 405system.cpu.icache.overall_misses::cpu.inst 45565 # number of overall misses 406system.cpu.icache.overall_misses::total 45565 # number of overall misses 407system.cpu.icache.ReadReq_miss_latency::cpu.inst 909865240 # number of ReadReq miss cycles 408system.cpu.icache.ReadReq_miss_latency::total 909865240 # number of ReadReq miss cycles 409system.cpu.icache.demand_miss_latency::cpu.inst 909865240 # number of demand (read+write) miss cycles 410system.cpu.icache.demand_miss_latency::total 909865240 # number of demand (read+write) miss cycles 411system.cpu.icache.overall_miss_latency::cpu.inst 909865240 # number of overall miss cycles 412system.cpu.icache.overall_miss_latency::total 909865240 # number of overall miss cycles 413system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) 414system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) 415system.cpu.icache.demand_accesses::cpu.inst 27472867 # number of demand (read+write) accesses 416system.cpu.icache.demand_accesses::total 27472867 # number of demand (read+write) accesses 417system.cpu.icache.overall_accesses::cpu.inst 27472867 # number of overall (read+write) accesses 418system.cpu.icache.overall_accesses::total 27472867 # number of overall (read+write) accesses 419system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001659 # miss rate for ReadReq accesses 420system.cpu.icache.ReadReq_miss_rate::total 0.001659 # miss rate for ReadReq accesses 421system.cpu.icache.demand_miss_rate::cpu.inst 0.001659 # miss rate for demand accesses 422system.cpu.icache.demand_miss_rate::total 0.001659 # miss rate for demand accesses 423system.cpu.icache.overall_miss_rate::cpu.inst 0.001659 # miss rate for overall accesses 424system.cpu.icache.overall_miss_rate::total 0.001659 # miss rate for overall accesses 425system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19968.511796 # average ReadReq miss latency 426system.cpu.icache.ReadReq_avg_miss_latency::total 19968.511796 # average ReadReq miss latency 427system.cpu.icache.demand_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency 428system.cpu.icache.demand_avg_miss_latency::total 19968.511796 # average overall miss latency 429system.cpu.icache.overall_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency 430system.cpu.icache.overall_avg_miss_latency::total 19968.511796 # average overall miss latency | 391system.cpu.icache.tags.tag_accesses 50029934 # Number of tag accesses 392system.cpu.icache.tags.data_accesses 50029934 # Number of data accesses 393system.cpu.icache.ReadReq_hits::cpu.inst 24948252 # number of ReadReq hits 394system.cpu.icache.ReadReq_hits::total 24948252 # number of ReadReq hits 395system.cpu.icache.demand_hits::cpu.inst 24948252 # number of demand (read+write) hits 396system.cpu.icache.demand_hits::total 24948252 # number of demand (read+write) hits 397system.cpu.icache.overall_hits::cpu.inst 24948252 # number of overall hits 398system.cpu.icache.overall_hits::total 24948252 # number of overall hits 399system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses 400system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses 401system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses 402system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses 403system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses 404system.cpu.icache.overall_misses::total 44477 # number of overall misses 405system.cpu.icache.ReadReq_miss_latency::cpu.inst 894991489 # number of ReadReq miss cycles 406system.cpu.icache.ReadReq_miss_latency::total 894991489 # number of ReadReq miss cycles 407system.cpu.icache.demand_miss_latency::cpu.inst 894991489 # number of demand (read+write) miss cycles 408system.cpu.icache.demand_miss_latency::total 894991489 # number of demand (read+write) miss cycles 409system.cpu.icache.overall_miss_latency::cpu.inst 894991489 # number of overall miss cycles 410system.cpu.icache.overall_miss_latency::total 894991489 # number of overall miss cycles 411system.cpu.icache.ReadReq_accesses::cpu.inst 24992729 # number of ReadReq accesses(hits+misses) 412system.cpu.icache.ReadReq_accesses::total 24992729 # number of ReadReq accesses(hits+misses) 413system.cpu.icache.demand_accesses::cpu.inst 24992729 # number of demand (read+write) accesses 414system.cpu.icache.demand_accesses::total 24992729 # number of demand (read+write) accesses 415system.cpu.icache.overall_accesses::cpu.inst 24992729 # number of overall (read+write) accesses 416system.cpu.icache.overall_accesses::total 24992729 # number of overall (read+write) accesses 417system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses 418system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses 419system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses 420system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses 421system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses 422system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses 423system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721 # average ReadReq miss latency 424system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721 # average ReadReq miss latency 425system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency 426system.cpu.icache.demand_avg_miss_latency::total 20122.568721 # average overall miss latency 427system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency 428system.cpu.icache.overall_avg_miss_latency::total 20122.568721 # average overall miss latency |
| 431system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 432system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 433system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 434system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 435system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 436system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 437system.cpu.icache.fast_writes 0 # number of fast writes performed 438system.cpu.icache.cache_copies 0 # number of cache copies performed | 429system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 430system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 431system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 432system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 433system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 434system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 435system.cpu.icache.fast_writes 0 # number of fast writes performed 436system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 439system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45565 # number of ReadReq MSHR misses 440system.cpu.icache.ReadReq_mshr_misses::total 45565 # number of ReadReq MSHR misses 441system.cpu.icache.demand_mshr_misses::cpu.inst 45565 # number of demand (read+write) MSHR misses 442system.cpu.icache.demand_mshr_misses::total 45565 # number of demand (read+write) MSHR misses 443system.cpu.icache.overall_mshr_misses::cpu.inst 45565 # number of overall MSHR misses 444system.cpu.icache.overall_mshr_misses::total 45565 # number of overall MSHR misses 445system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 816831760 # number of ReadReq MSHR miss cycles 446system.cpu.icache.ReadReq_mshr_miss_latency::total 816831760 # number of ReadReq MSHR miss cycles 447system.cpu.icache.demand_mshr_miss_latency::cpu.inst 816831760 # number of demand (read+write) MSHR miss cycles 448system.cpu.icache.demand_mshr_miss_latency::total 816831760 # number of demand (read+write) MSHR miss cycles 449system.cpu.icache.overall_mshr_miss_latency::cpu.inst 816831760 # number of overall MSHR miss cycles 450system.cpu.icache.overall_mshr_miss_latency::total 816831760 # number of overall MSHR miss cycles 451system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for ReadReq accesses 452system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001659 # mshr miss rate for ReadReq accesses 453system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for demand accesses 454system.cpu.icache.demand_mshr_miss_rate::total 0.001659 # mshr miss rate for demand accesses 455system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for overall accesses 456system.cpu.icache.overall_mshr_miss_rate::total 0.001659 # mshr miss rate for overall accesses 457system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17926.736750 # average ReadReq mshr miss latency 458system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17926.736750 # average ReadReq mshr miss latency 459system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency 460system.cpu.icache.demand_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency 461system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency 462system.cpu.icache.overall_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency | 437system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44477 # number of ReadReq MSHR misses 438system.cpu.icache.ReadReq_mshr_misses::total 44477 # number of ReadReq MSHR misses 439system.cpu.icache.demand_mshr_misses::cpu.inst 44477 # number of demand (read+write) MSHR misses 440system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses 441system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses 442system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses 443system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804116511 # number of ReadReq MSHR miss cycles 444system.cpu.icache.ReadReq_mshr_miss_latency::total 804116511 # number of ReadReq MSHR miss cycles 445system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804116511 # number of demand (read+write) MSHR miss cycles 446system.cpu.icache.demand_mshr_miss_latency::total 804116511 # number of demand (read+write) MSHR miss cycles 447system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804116511 # number of overall MSHR miss cycles 448system.cpu.icache.overall_mshr_miss_latency::total 804116511 # number of overall MSHR miss cycles 449system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses 450system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses 451system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses 452system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses 453system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses 454system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses 455system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353 # average ReadReq mshr miss latency 456system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353 # average ReadReq mshr miss latency 457system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency 458system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency 459system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency 460system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency |
| 463system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 461system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 464system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) 465system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution 470system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) 472system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) 473system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) 475system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) 476system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) | 462system.cpu.toL2Bus.throughput 378768688 # Throughput (bytes/s) 463system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadExReq 107038 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadExResp 107038 # Transaction distribution 468system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 88953 # Packet count per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_count::total 538416 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes) 472system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes) 473system.cpu.toL2Bus.tot_pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.data_through_bus 21338816 # Total data (bytes) |
| 477system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 475system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 478system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) | 476system.cpu.toL2Bus.reqLayer0.occupancy 295133000 # Layer occupancy (ticks) |
| 479system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) | 477system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) |
| 480system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) | 478system.cpu.toL2Bus.respLayer0.occupancy 67675489 # Layer occupancy (ticks) |
| 481system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 479system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 482system.cpu.toL2Bus.respLayer1.occupancy 269478689 # Layer occupancy (ticks) 483system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 484system.cpu.l2cache.tags.replacements 95911 # number of replacements 485system.cpu.l2cache.tags.tagsinuse 30027.975303 # Cycle average of tags in use 486system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. 487system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. 488system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. | 480system.cpu.toL2Bus.respLayer1.occupancy 268454939 # Layer occupancy (ticks) 481system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 482system.cpu.l2cache.tags.replacements 95725 # number of replacements 483system.cpu.l2cache.tags.tagsinuse 29924.855625 # Cycle average of tags in use 484system.cpu.l2cache.tags.total_refs 99436 # Total number of references to valid blocks. 485system.cpu.l2cache.tags.sampled_refs 126843 # Sample count of references to valid blocks. 486system.cpu.l2cache.tags.avg_refs 0.783930 # Average number of references to valid blocks. |
| 489system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 487system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 490system.cpu.l2cache.tags.occ_blocks::writebacks 26739.140336 # Average occupied blocks per requestor 491system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.834967 # Average occupied blocks per requestor 492system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy 493system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy 494system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy 495system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id 496system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id 497system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id 498system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id 499system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id 500system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id 501system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id 502system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses 503system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses 504system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits 505system.cpu.l2cache.ReadReq_hits::total 72636 # number of ReadReq hits 506system.cpu.l2cache.Writeback_hits::writebacks 128565 # number of Writeback hits 507system.cpu.l2cache.Writeback_hits::total 128565 # number of Writeback hits 508system.cpu.l2cache.ReadExReq_hits::cpu.inst 4766 # number of ReadExReq hits 509system.cpu.l2cache.ReadExReq_hits::total 4766 # number of ReadExReq hits 510system.cpu.l2cache.demand_hits::cpu.inst 77402 # number of demand (read+write) hits 511system.cpu.l2cache.demand_hits::total 77402 # number of demand (read+write) hits 512system.cpu.l2cache.overall_hits::cpu.inst 77402 # number of overall hits 513system.cpu.l2cache.overall_hits::total 77402 # number of overall hits 514system.cpu.l2cache.ReadReq_misses::cpu.inst 26857 # number of ReadReq misses 515system.cpu.l2cache.ReadReq_misses::total 26857 # number of ReadReq misses 516system.cpu.l2cache.ReadExReq_misses::cpu.inst 102267 # number of ReadExReq misses 517system.cpu.l2cache.ReadExReq_misses::total 102267 # number of ReadExReq misses 518system.cpu.l2cache.demand_misses::cpu.inst 129124 # number of demand (read+write) misses 519system.cpu.l2cache.demand_misses::total 129124 # number of demand (read+write) misses 520system.cpu.l2cache.overall_misses::cpu.inst 129124 # number of overall misses 521system.cpu.l2cache.overall_misses::total 129124 # number of overall misses 522system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1992283500 # number of ReadReq miss cycles 523system.cpu.l2cache.ReadReq_miss_latency::total 1992283500 # number of ReadReq miss cycles 524system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7436939000 # number of ReadExReq miss cycles 525system.cpu.l2cache.ReadExReq_miss_latency::total 7436939000 # number of ReadExReq miss cycles 526system.cpu.l2cache.demand_miss_latency::cpu.inst 9429222500 # number of demand (read+write) miss cycles 527system.cpu.l2cache.demand_miss_latency::total 9429222500 # number of demand (read+write) miss cycles 528system.cpu.l2cache.overall_miss_latency::cpu.inst 9429222500 # number of overall miss cycles 529system.cpu.l2cache.overall_miss_latency::total 9429222500 # number of overall miss cycles 530system.cpu.l2cache.ReadReq_accesses::cpu.inst 99493 # number of ReadReq accesses(hits+misses) 531system.cpu.l2cache.ReadReq_accesses::total 99493 # number of ReadReq accesses(hits+misses) 532system.cpu.l2cache.Writeback_accesses::writebacks 128565 # number of Writeback accesses(hits+misses) 533system.cpu.l2cache.Writeback_accesses::total 128565 # number of Writeback accesses(hits+misses) 534system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107033 # number of ReadExReq accesses(hits+misses) 535system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) 536system.cpu.l2cache.demand_accesses::cpu.inst 206526 # number of demand (read+write) accesses 537system.cpu.l2cache.demand_accesses::total 206526 # number of demand (read+write) accesses 538system.cpu.l2cache.overall_accesses::cpu.inst 206526 # number of overall (read+write) accesses 539system.cpu.l2cache.overall_accesses::total 206526 # number of overall (read+write) accesses 540system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269939 # miss rate for ReadReq accesses 541system.cpu.l2cache.ReadReq_miss_rate::total 0.269939 # miss rate for ReadReq accesses 542system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955472 # miss rate for ReadExReq accesses 543system.cpu.l2cache.ReadExReq_miss_rate::total 0.955472 # miss rate for ReadExReq accesses 544system.cpu.l2cache.demand_miss_rate::cpu.inst 0.625219 # miss rate for demand accesses 545system.cpu.l2cache.demand_miss_rate::total 0.625219 # miss rate for demand accesses 546system.cpu.l2cache.overall_miss_rate::cpu.inst 0.625219 # miss rate for overall accesses 547system.cpu.l2cache.overall_miss_rate::total 0.625219 # miss rate for overall accesses 548system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74181.163198 # average ReadReq miss latency 549system.cpu.l2cache.ReadReq_avg_miss_latency::total 74181.163198 # average ReadReq miss latency 550system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.809254 # average ReadExReq miss latency 551system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.809254 # average ReadExReq miss latency 552system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency 553system.cpu.l2cache.demand_avg_miss_latency::total 73024.553917 # average overall miss latency 554system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency 555system.cpu.l2cache.overall_avg_miss_latency::total 73024.553917 # average overall miss latency | 488system.cpu.l2cache.tags.occ_blocks::writebacks 26686.795429 # Average occupied blocks per requestor 489system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.060196 # Average occupied blocks per requestor 490system.cpu.l2cache.tags.occ_percent::writebacks 0.814416 # Average percentage of cache occupancy 491system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098818 # Average percentage of cache occupancy 492system.cpu.l2cache.tags.occ_percent::total 0.913234 # Average percentage of cache occupancy 493system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id 494system.cpu.l2cache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id 495system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1148 # Occupied blocks per task id 496system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9890 # Occupied blocks per task id 497system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19364 # Occupied blocks per task id 498system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id 499system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id 500system.cpu.l2cache.tags.tag_accesses 2901241 # Number of tag accesses 501system.cpu.l2cache.tags.data_accesses 2901241 # Number of data accesses 502system.cpu.l2cache.ReadReq_hits::cpu.inst 71304 # number of ReadReq hits 503system.cpu.l2cache.ReadReq_hits::total 71304 # number of ReadReq hits 504system.cpu.l2cache.Writeback_hits::writebacks 128423 # number of Writeback hits 505system.cpu.l2cache.Writeback_hits::total 128423 # number of Writeback hits 506system.cpu.l2cache.ReadExReq_hits::cpu.inst 4759 # number of ReadExReq hits 507system.cpu.l2cache.ReadExReq_hits::total 4759 # number of ReadExReq hits 508system.cpu.l2cache.demand_hits::cpu.inst 76063 # number of demand (read+write) hits 509system.cpu.l2cache.demand_hits::total 76063 # number of demand (read+write) hits 510system.cpu.l2cache.overall_hits::cpu.inst 76063 # number of overall hits 511system.cpu.l2cache.overall_hits::total 76063 # number of overall hits 512system.cpu.l2cache.ReadReq_misses::cpu.inst 26655 # number of ReadReq misses 513system.cpu.l2cache.ReadReq_misses::total 26655 # number of ReadReq misses 514system.cpu.l2cache.ReadExReq_misses::cpu.inst 102279 # number of ReadExReq misses 515system.cpu.l2cache.ReadExReq_misses::total 102279 # number of ReadExReq misses 516system.cpu.l2cache.demand_misses::cpu.inst 128934 # number of demand (read+write) misses 517system.cpu.l2cache.demand_misses::total 128934 # number of demand (read+write) misses 518system.cpu.l2cache.overall_misses::cpu.inst 128934 # number of overall misses 519system.cpu.l2cache.overall_misses::total 128934 # number of overall misses 520system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978942750 # number of ReadReq miss cycles 521system.cpu.l2cache.ReadReq_miss_latency::total 1978942750 # number of ReadReq miss cycles 522system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7452442750 # number of ReadExReq miss cycles 523system.cpu.l2cache.ReadExReq_miss_latency::total 7452442750 # number of ReadExReq miss cycles 524system.cpu.l2cache.demand_miss_latency::cpu.inst 9431385500 # number of demand (read+write) miss cycles 525system.cpu.l2cache.demand_miss_latency::total 9431385500 # number of demand (read+write) miss cycles 526system.cpu.l2cache.overall_miss_latency::cpu.inst 9431385500 # number of overall miss cycles 527system.cpu.l2cache.overall_miss_latency::total 9431385500 # number of overall miss cycles 528system.cpu.l2cache.ReadReq_accesses::cpu.inst 97959 # number of ReadReq accesses(hits+misses) 529system.cpu.l2cache.ReadReq_accesses::total 97959 # number of ReadReq accesses(hits+misses) 530system.cpu.l2cache.Writeback_accesses::writebacks 128423 # number of Writeback accesses(hits+misses) 531system.cpu.l2cache.Writeback_accesses::total 128423 # number of Writeback accesses(hits+misses) 532system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107038 # number of ReadExReq accesses(hits+misses) 533system.cpu.l2cache.ReadExReq_accesses::total 107038 # number of ReadExReq accesses(hits+misses) 534system.cpu.l2cache.demand_accesses::cpu.inst 204997 # number of demand (read+write) accesses 535system.cpu.l2cache.demand_accesses::total 204997 # number of demand (read+write) accesses 536system.cpu.l2cache.overall_accesses::cpu.inst 204997 # number of overall (read+write) accesses 537system.cpu.l2cache.overall_accesses::total 204997 # number of overall (read+write) accesses 538system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.272104 # miss rate for ReadReq accesses 539system.cpu.l2cache.ReadReq_miss_rate::total 0.272104 # miss rate for ReadReq accesses 540system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955539 # miss rate for ReadExReq accesses 541system.cpu.l2cache.ReadExReq_miss_rate::total 0.955539 # miss rate for ReadExReq accesses 542system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628956 # miss rate for demand accesses 543system.cpu.l2cache.demand_miss_rate::total 0.628956 # miss rate for demand accesses 544system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628956 # miss rate for overall accesses 545system.cpu.l2cache.overall_miss_rate::total 0.628956 # miss rate for overall accesses 546system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74242.834365 # average ReadReq miss latency 547system.cpu.l2cache.ReadReq_avg_miss_latency::total 74242.834365 # average ReadReq miss latency 548system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72863.860128 # average ReadExReq miss latency 549system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72863.860128 # average ReadExReq miss latency 550system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency 551system.cpu.l2cache.demand_avg_miss_latency::total 73148.940543 # average overall miss latency 552system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency 553system.cpu.l2cache.overall_avg_miss_latency::total 73148.940543 # average overall miss latency |
| 556system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 559system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 561system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 562system.cpu.l2cache.fast_writes 0 # number of fast writes performed 563system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 554system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 555system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 556system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 558system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 559system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 560system.cpu.l2cache.fast_writes 0 # number of fast writes performed 561system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 564system.cpu.l2cache.writebacks::writebacks 83957 # number of writebacks 565system.cpu.l2cache.writebacks::total 83957 # number of writebacks | 562system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks 563system.cpu.l2cache.writebacks::total 83951 # number of writebacks |
| 566system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits 567system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 568system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits 569system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 570system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits 571system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits | 564system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits 565system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 566system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits 567system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 568system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits 569system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits |
| 572system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26786 # number of ReadReq MSHR misses 573system.cpu.l2cache.ReadReq_mshr_misses::total 26786 # number of ReadReq MSHR misses 574system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102267 # number of ReadExReq MSHR misses 575system.cpu.l2cache.ReadExReq_mshr_misses::total 102267 # number of ReadExReq MSHR misses 576system.cpu.l2cache.demand_mshr_misses::cpu.inst 129053 # number of demand (read+write) MSHR misses 577system.cpu.l2cache.demand_mshr_misses::total 129053 # number of demand (read+write) MSHR misses 578system.cpu.l2cache.overall_mshr_misses::cpu.inst 129053 # number of overall MSHR misses 579system.cpu.l2cache.overall_mshr_misses::total 129053 # number of overall MSHR misses 580system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1646558250 # number of ReadReq MSHR miss cycles 581system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1646558250 # number of ReadReq MSHR miss cycles 582system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6118064000 # number of ReadExReq MSHR miss cycles 583system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6118064000 # number of ReadExReq MSHR miss cycles 584system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7764622250 # number of demand (read+write) MSHR miss cycles 585system.cpu.l2cache.demand_mshr_miss_latency::total 7764622250 # number of demand (read+write) MSHR miss cycles 586system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7764622250 # number of overall MSHR miss cycles 587system.cpu.l2cache.overall_mshr_miss_latency::total 7764622250 # number of overall MSHR miss cycles 588system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269225 # mshr miss rate for ReadReq accesses 589system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269225 # mshr miss rate for ReadReq accesses 590system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955472 # mshr miss rate for ReadExReq accesses 591system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955472 # mshr miss rate for ReadExReq accesses 592system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for demand accesses 593system.cpu.l2cache.demand_mshr_miss_rate::total 0.624875 # mshr miss rate for demand accesses 594system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for overall accesses 595system.cpu.l2cache.overall_mshr_miss_rate::total 0.624875 # mshr miss rate for overall accesses 596system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61470.852311 # average ReadReq mshr miss latency 597system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61470.852311 # average ReadReq mshr miss latency 598system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.420390 # average ReadExReq mshr miss latency 599system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.420390 # average ReadExReq mshr miss latency 600system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency 601system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency 602system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency 603system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency | 570system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26584 # number of ReadReq MSHR misses 571system.cpu.l2cache.ReadReq_mshr_misses::total 26584 # number of ReadReq MSHR misses 572system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102279 # number of ReadExReq MSHR misses 573system.cpu.l2cache.ReadExReq_mshr_misses::total 102279 # number of ReadExReq MSHR misses 574system.cpu.l2cache.demand_mshr_misses::cpu.inst 128863 # number of demand (read+write) MSHR misses 575system.cpu.l2cache.demand_mshr_misses::total 128863 # number of demand (read+write) MSHR misses 576system.cpu.l2cache.overall_mshr_misses::cpu.inst 128863 # number of overall MSHR misses 577system.cpu.l2cache.overall_mshr_misses::total 128863 # number of overall MSHR misses 578system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1636163750 # number of ReadReq MSHR miss cycles 579system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1636163750 # number of ReadReq MSHR miss cycles 580system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6153335250 # number of ReadExReq MSHR miss cycles 581system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6153335250 # number of ReadExReq MSHR miss cycles 582system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7789499000 # number of demand (read+write) MSHR miss cycles 583system.cpu.l2cache.demand_mshr_miss_latency::total 7789499000 # number of demand (read+write) MSHR miss cycles 584system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7789499000 # number of overall MSHR miss cycles 585system.cpu.l2cache.overall_mshr_miss_latency::total 7789499000 # number of overall MSHR miss cycles 586system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.271379 # mshr miss rate for ReadReq accesses 587system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.271379 # mshr miss rate for ReadReq accesses 588system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955539 # mshr miss rate for ReadExReq accesses 589system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955539 # mshr miss rate for ReadExReq accesses 590system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for demand accesses 591system.cpu.l2cache.demand_mshr_miss_rate::total 0.628609 # mshr miss rate for demand accesses 592system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for overall accesses 593system.cpu.l2cache.overall_mshr_miss_rate::total 0.628609 # mshr miss rate for overall accesses 594system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61546.936127 # average ReadReq mshr miss latency 595system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61546.936127 # average ReadReq mshr miss latency 596system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60162.254715 # average ReadExReq mshr miss latency 597system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60162.254715 # average ReadExReq mshr miss latency 598system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency 599system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency 600system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency 601system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency |
| 604system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 602system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 605system.cpu.dcache.tags.replacements 156865 # number of replacements 606system.cpu.dcache.tags.tagsinuse 4070.633737 # Cycle average of tags in use 607system.cpu.dcache.tags.total_refs 47252087 # Total number of references to valid blocks. 608system.cpu.dcache.tags.sampled_refs 160961 # Sample count of references to valid blocks. 609system.cpu.dcache.tags.avg_refs 293.562335 # Average number of references to valid blocks. 610system.cpu.dcache.tags.warmup_cycle 802561250 # Cycle when the warmup percentage was hit. 611system.cpu.dcache.tags.occ_blocks::cpu.inst 4070.633737 # Average occupied blocks per requestor 612system.cpu.dcache.tags.occ_percent::cpu.inst 0.993807 # Average percentage of cache occupancy 613system.cpu.dcache.tags.occ_percent::total 0.993807 # Average percentage of cache occupancy | 603system.cpu.dcache.tags.replacements 156424 # number of replacements 604system.cpu.dcache.tags.tagsinuse 4068.182682 # Cycle average of tags in use 605system.cpu.dcache.tags.total_refs 42664218 # Total number of references to valid blocks. 606system.cpu.dcache.tags.sampled_refs 160520 # Sample count of references to valid blocks. 607system.cpu.dcache.tags.avg_refs 265.787553 # Average number of references to valid blocks. 608system.cpu.dcache.tags.warmup_cycle 770315250 # Cycle when the warmup percentage was hit. 609system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.182682 # Average occupied blocks per requestor 610system.cpu.dcache.tags.occ_percent::cpu.inst 0.993209 # Average percentage of cache occupancy 611system.cpu.dcache.tags.occ_percent::total 0.993209 # Average percentage of cache occupancy |
| 614system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 615system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id | 612system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 613system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id |
| 616system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id 617system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id | 614system.cpu.dcache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id 615system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id |
| 618system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 616system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 619system.cpu.dcache.tags.tag_accesses 95193929 # Number of tag accesses 620system.cpu.dcache.tags.data_accesses 95193929 # Number of data accesses 621system.cpu.dcache.ReadReq_hits::cpu.inst 27577955 # number of ReadReq hits 622system.cpu.dcache.ReadReq_hits::total 27577955 # number of ReadReq hits 623system.cpu.dcache.WriteReq_hits::cpu.inst 19642294 # number of WriteReq hits 624system.cpu.dcache.WriteReq_hits::total 19642294 # number of WriteReq hits | 617system.cpu.dcache.tags.tag_accesses 86013120 # Number of tag accesses 618system.cpu.dcache.tags.data_accesses 86013120 # Number of data accesses 619system.cpu.dcache.ReadReq_hits::cpu.inst 22988546 # number of ReadReq hits 620system.cpu.dcache.ReadReq_hits::total 22988546 # number of ReadReq hits 621system.cpu.dcache.WriteReq_hits::cpu.inst 19643834 # number of WriteReq hits 622system.cpu.dcache.WriteReq_hits::total 19643834 # number of WriteReq hits |
| 625system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits 626system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 627system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits 628system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 623system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits 624system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 625system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits 626system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 629system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits 630system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits 631system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits 632system.cpu.dcache.overall_hits::total 47220249 # number of overall hits 633system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses 634system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses 635system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses 636system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses 637system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses 638system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses 639system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses 640system.cpu.dcache.overall_misses::total 264397 # number of overall misses 641system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169299439 # number of ReadReq miss cycles 642system.cpu.dcache.ReadReq_miss_latency::total 2169299439 # number of ReadReq miss cycles 643system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315314750 # number of WriteReq miss cycles 644system.cpu.dcache.WriteReq_miss_latency::total 15315314750 # number of WriteReq miss cycles 645system.cpu.dcache.demand_miss_latency::cpu.inst 17484614189 # number of demand (read+write) miss cycles 646system.cpu.dcache.demand_miss_latency::total 17484614189 # number of demand (read+write) miss cycles 647system.cpu.dcache.overall_miss_latency::cpu.inst 17484614189 # number of overall miss cycles 648system.cpu.dcache.overall_miss_latency::total 17484614189 # number of overall miss cycles 649system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # number of ReadReq accesses(hits+misses) 650system.cpu.dcache.ReadReq_accesses::total 27634745 # number of ReadReq accesses(hits+misses) | 627system.cpu.dcache.demand_hits::cpu.inst 42632380 # number of demand (read+write) hits 628system.cpu.dcache.demand_hits::total 42632380 # number of demand (read+write) hits 629system.cpu.dcache.overall_hits::cpu.inst 42632380 # number of overall hits 630system.cpu.dcache.overall_hits::total 42632380 # number of overall hits 631system.cpu.dcache.ReadReq_misses::cpu.inst 56015 # number of ReadReq misses 632system.cpu.dcache.ReadReq_misses::total 56015 # number of ReadReq misses 633system.cpu.dcache.WriteReq_misses::cpu.inst 206067 # number of WriteReq misses 634system.cpu.dcache.WriteReq_misses::total 206067 # number of WriteReq misses 635system.cpu.dcache.demand_misses::cpu.inst 262082 # number of demand (read+write) misses 636system.cpu.dcache.demand_misses::total 262082 # number of demand (read+write) misses 637system.cpu.dcache.overall_misses::cpu.inst 262082 # number of overall misses 638system.cpu.dcache.overall_misses::total 262082 # number of overall misses 639system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2143200689 # number of ReadReq miss cycles 640system.cpu.dcache.ReadReq_miss_latency::total 2143200689 # number of ReadReq miss cycles 641system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15189809250 # number of WriteReq miss cycles 642system.cpu.dcache.WriteReq_miss_latency::total 15189809250 # number of WriteReq miss cycles 643system.cpu.dcache.demand_miss_latency::cpu.inst 17333009939 # number of demand (read+write) miss cycles 644system.cpu.dcache.demand_miss_latency::total 17333009939 # number of demand (read+write) miss cycles 645system.cpu.dcache.overall_miss_latency::cpu.inst 17333009939 # number of overall miss cycles 646system.cpu.dcache.overall_miss_latency::total 17333009939 # number of overall miss cycles 647system.cpu.dcache.ReadReq_accesses::cpu.inst 23044561 # number of ReadReq accesses(hits+misses) 648system.cpu.dcache.ReadReq_accesses::total 23044561 # number of ReadReq accesses(hits+misses) |
| 651system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) 652system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 653system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) 654system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 655system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) 656system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 649system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) 650system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 651system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) 652system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 653system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) 654system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 657system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses 658system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses 659system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses 660system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses 661system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses 662system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses 663system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses 664system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses 665system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses 666system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses 667system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses 668system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses 669system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38198.616640 # average ReadReq miss latency 670system.cpu.dcache.ReadReq_avg_miss_latency::total 38198.616640 # average ReadReq miss latency 671system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73770.704986 # average WriteReq miss latency 672system.cpu.dcache.WriteReq_avg_miss_latency::total 73770.704986 # average WriteReq miss latency 673system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency 674system.cpu.dcache.demand_avg_miss_latency::total 66130.153478 # average overall miss latency 675system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency 676system.cpu.dcache.overall_avg_miss_latency::total 66130.153478 # average overall miss latency | 655system.cpu.dcache.demand_accesses::cpu.inst 42894462 # number of demand (read+write) accesses 656system.cpu.dcache.demand_accesses::total 42894462 # number of demand (read+write) accesses 657system.cpu.dcache.overall_accesses::cpu.inst 42894462 # number of overall (read+write) accesses 658system.cpu.dcache.overall_accesses::total 42894462 # number of overall (read+write) accesses 659system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002431 # miss rate for ReadReq accesses 660system.cpu.dcache.ReadReq_miss_rate::total 0.002431 # miss rate for ReadReq accesses 661system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses 662system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses 663system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses 664system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses 665system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses 666system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses 667system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341 # average ReadReq miss latency 668system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341 # average ReadReq miss latency 669system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502 # average WriteReq miss latency 670system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502 # average WriteReq miss latency 671system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency 672system.cpu.dcache.demand_avg_miss_latency::total 66135.827485 # average overall miss latency 673system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency 674system.cpu.dcache.overall_avg_miss_latency::total 66135.827485 # average overall miss latency |
| 677system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 678system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 679system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 680system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 681system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 682system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 683system.cpu.dcache.fast_writes 0 # number of fast writes performed 684system.cpu.dcache.cache_copies 0 # number of cache copies performed | 675system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 676system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 678system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 679system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 680system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu.dcache.fast_writes 0 # number of fast writes performed 682system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 685system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks 686system.cpu.dcache.writebacks::total 128565 # number of writebacks 687system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits 688system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits 689system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits 690system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits 691system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits 692system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits 693system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits 694system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits 695system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses 696system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses 697system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses 698system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses 699system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses 700system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses 701system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses 702system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses 703system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001760311 # number of ReadReq MSHR miss cycles 704system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001760311 # number of ReadReq MSHR miss cycles 705system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591657000 # number of WriteReq MSHR miss cycles 706system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591657000 # number of WriteReq MSHR miss cycles 707system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593417311 # number of demand (read+write) MSHR miss cycles 708system.cpu.dcache.demand_mshr_miss_latency::total 9593417311 # number of demand (read+write) MSHR miss cycles 709system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593417311 # number of overall MSHR miss cycles 710system.cpu.dcache.overall_mshr_miss_latency::total 9593417311 # number of overall MSHR miss cycles 711system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses 712system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses | 683system.cpu.dcache.writebacks::writebacks 128423 # number of writebacks 684system.cpu.dcache.writebacks::total 128423 # number of writebacks 685system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2533 # number of ReadReq MSHR hits 686system.cpu.dcache.ReadReq_mshr_hits::total 2533 # number of ReadReq MSHR hits 687system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99029 # number of WriteReq MSHR hits 688system.cpu.dcache.WriteReq_mshr_hits::total 99029 # number of WriteReq MSHR hits 689system.cpu.dcache.demand_mshr_hits::cpu.inst 101562 # number of demand (read+write) MSHR hits 690system.cpu.dcache.demand_mshr_hits::total 101562 # number of demand (read+write) MSHR hits 691system.cpu.dcache.overall_mshr_hits::cpu.inst 101562 # number of overall MSHR hits 692system.cpu.dcache.overall_mshr_hits::total 101562 # number of overall MSHR hits 693system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53482 # number of ReadReq MSHR misses 694system.cpu.dcache.ReadReq_mshr_misses::total 53482 # number of ReadReq MSHR misses 695system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107038 # number of WriteReq MSHR misses 696system.cpu.dcache.WriteReq_mshr_misses::total 107038 # number of WriteReq MSHR misses 697system.cpu.dcache.demand_mshr_misses::cpu.inst 160520 # number of demand (read+write) MSHR misses 698system.cpu.dcache.demand_mshr_misses::total 160520 # number of demand (read+write) MSHR misses 699system.cpu.dcache.overall_mshr_misses::cpu.inst 160520 # number of overall MSHR misses 700system.cpu.dcache.overall_mshr_misses::total 160520 # number of overall MSHR misses 701system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1986266811 # number of ReadReq MSHR miss cycles 702system.cpu.dcache.ReadReq_mshr_miss_latency::total 1986266811 # number of ReadReq MSHR miss cycles 703system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7607104750 # number of WriteReq MSHR miss cycles 704system.cpu.dcache.WriteReq_mshr_miss_latency::total 7607104750 # number of WriteReq MSHR miss cycles 705system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593371561 # number of demand (read+write) MSHR miss cycles 706system.cpu.dcache.demand_mshr_miss_latency::total 9593371561 # number of demand (read+write) MSHR miss cycles 707system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593371561 # number of overall MSHR miss cycles 708system.cpu.dcache.overall_mshr_miss_latency::total 9593371561 # number of overall MSHR miss cycles 709system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses 710system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses |
| 713system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses 714system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses | 711system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses 712system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses |
| 715system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses 716system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses 717system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses 718system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses 719system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.127559 # average ReadReq mshr miss latency 720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.127559 # average ReadReq mshr miss latency 721system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.190371 # average WriteReq mshr miss latency 722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.190371 # average WriteReq mshr miss latency 723system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency 724system.cpu.dcache.demand_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency 725system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency 726system.cpu.dcache.overall_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency | 713system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for demand accesses 714system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses 715system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses 716system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses 717system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806 # average ReadReq mshr miss latency 718system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806 # average ReadReq mshr miss latency 719system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388 # average WriteReq mshr miss latency 720system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388 # average WriteReq mshr miss latency 721system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency 722system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency 723system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency 724system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency |
| 727system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 728 729---------- End Simulation Statistics ---------- | 725system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 726 727---------- End Simulation Statistics ---------- |