| stats.txt (10260:384d554cea8c) | stats.txt (10261:dc198e224a85) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.064367 # Number of seconds simulated 4sim_ticks 64366581500 # Number of ticks simulated |
|
| 3final_tick 64366581500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 5final_tick 64366581500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 4host_inst_rate 178791 # Simulator instruction rate (inst/s) 5host_mem_usage 302756 # Number of bytes of host memory used 6host_op_rate 253719 # Simulator op (including micro ops) rate (op/s) 7host_seconds 396.64 # Real time elapsed on the host 8host_tick_rate 162280857 # Simulator tick rate (ticks/s) | |
| 9sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 99170 # Simulator instruction rate (inst/s) 8host_op_rate 140730 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 90012135 # Simulator tick rate (ticks/s) 10host_mem_usage 295432 # Number of bytes of host memory used 11host_seconds 715.09 # Real time elapsed on the host |
|
| 10sim_insts 70915127 # Number of instructions simulated 11sim_ops 100634375 # Number of ops (including micro ops) simulated | 12sim_insts 70915127 # Number of instructions simulated 13sim_ops 100634375 # Number of ops (including micro ops) simulated |
| 12sim_seconds 0.064367 # Number of seconds simulated 13sim_ticks 64366581500 # Number of ticks simulated | 14system.voltage_domain.voltage 1 # Voltage in Volts |
| 14system.clk_domain.clock 1000 # Clock period in ticks | 15system.clk_domain.clock 1000 # Clock period in ticks |
| 15system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 16system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage 17system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits 18system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups 19system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. 20system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect 21system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted 22system.cpu.branchPred.lookups 16883830 # Number of BP lookups 23system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. 24system.cpu.committedInsts 70915127 # Number of instructions committed 25system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed 26system.cpu.cpi 1.815313 # CPI: cycles per instruction 27system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) 28system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 29system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits 30system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 31system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # number of ReadReq accesses(hits+misses) 32system.cpu.dcache.ReadReq_accesses::total 27634745 # number of ReadReq accesses(hits+misses) 33system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38199.338598 # average ReadReq miss latency 34system.cpu.dcache.ReadReq_avg_miss_latency::total 38199.338598 # average ReadReq miss latency 35system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.609683 # average ReadReq mshr miss latency 36system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.609683 # average ReadReq mshr miss latency 37system.cpu.dcache.ReadReq_hits::cpu.inst 27577955 # number of ReadReq hits 38system.cpu.dcache.ReadReq_hits::total 27577955 # number of ReadReq hits 39system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169340439 # number of ReadReq miss cycles 40system.cpu.dcache.ReadReq_miss_latency::total 2169340439 # number of ReadReq miss cycles 41system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses 42system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses 43system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses 44system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses 45system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits 46system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits 47system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001786311 # number of ReadReq MSHR miss cycles 48system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001786311 # number of ReadReq MSHR miss cycles 49system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses 50system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses 51system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses 52system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses 53system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) 54system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 55system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits 56system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 57system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) 58system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 59system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73771.399808 # average WriteReq miss latency 60system.cpu.dcache.WriteReq_avg_miss_latency::total 73771.399808 # average WriteReq miss latency 61system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.202050 # average WriteReq mshr miss latency 62system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.202050 # average WriteReq mshr miss latency 63system.cpu.dcache.WriteReq_hits::cpu.inst 19642294 # number of WriteReq hits 64system.cpu.dcache.WriteReq_hits::total 19642294 # number of WriteReq hits 65system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315459000 # number of WriteReq miss cycles 66system.cpu.dcache.WriteReq_miss_latency::total 15315459000 # number of WriteReq miss cycles 67system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses 68system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses 70system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses 71system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits 72system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits 73system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591658250 # number of WriteReq MSHR miss cycles 74system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591658250 # number of WriteReq MSHR miss cycles 75system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses 76system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 77system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses 78system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses 79system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 82system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 83system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 84system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85system.cpu.dcache.cache_copies 0 # number of cache copies performed 86system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses 87system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses 88system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.854128 # average overall miss latency 89system.cpu.dcache.demand_avg_miss_latency::total 66130.854128 # average overall miss latency 90system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59601.049701 # average overall mshr miss latency 91system.cpu.dcache.demand_avg_mshr_miss_latency::total 59601.049701 # average overall mshr miss latency 92system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits 93system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits 94system.cpu.dcache.demand_miss_latency::cpu.inst 17484799439 # number of demand (read+write) miss cycles 95system.cpu.dcache.demand_miss_latency::total 17484799439 # number of demand (read+write) miss cycles 96system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses 97system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses 98system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses 99system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses 100system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits 101system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits 102system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593444561 # number of demand (read+write) MSHR miss cycles 103system.cpu.dcache.demand_mshr_miss_latency::total 9593444561 # number of demand (read+write) MSHR miss cycles 104system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses 105system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses 106system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses 107system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses 108system.cpu.dcache.fast_writes 0 # number of fast writes performed 109system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 110system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses 111system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses 112system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.854128 # average overall miss latency 113system.cpu.dcache.overall_avg_miss_latency::total 66130.854128 # average overall miss latency 114system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59601.049701 # average overall mshr miss latency 115system.cpu.dcache.overall_avg_mshr_miss_latency::total 59601.049701 # average overall mshr miss latency 116system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits 117system.cpu.dcache.overall_hits::total 47220249 # number of overall hits 118system.cpu.dcache.overall_miss_latency::cpu.inst 17484799439 # number of overall miss cycles 119system.cpu.dcache.overall_miss_latency::total 17484799439 # number of overall miss cycles 120system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses 121system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses 122system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses 123system.cpu.dcache.overall_misses::total 264397 # number of overall misses 124system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits 125system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits 126system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593444561 # number of overall MSHR miss cycles 127system.cpu.dcache.overall_mshr_miss_latency::total 9593444561 # number of overall MSHR miss cycles 128system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses 129system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses 130system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses 131system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses 132system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 133system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id 134system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id 135system.cpu.dcache.tags.avg_refs 293.562335 # Average number of references to valid blocks. 136system.cpu.dcache.tags.data_accesses 95193929 # Number of data accesses 137system.cpu.dcache.tags.occ_blocks::cpu.inst 4070.633737 # Average occupied blocks per requestor 138system.cpu.dcache.tags.occ_percent::cpu.inst 0.993807 # Average percentage of cache occupancy 139system.cpu.dcache.tags.occ_percent::total 0.993807 # Average percentage of cache occupancy 140system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 141system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 142system.cpu.dcache.tags.replacements 156865 # number of replacements 143system.cpu.dcache.tags.sampled_refs 160961 # Sample count of references to valid blocks. 144system.cpu.dcache.tags.tag_accesses 95193929 # Number of tag accesses 145system.cpu.dcache.tags.tagsinuse 4070.633737 # Cycle average of tags in use 146system.cpu.dcache.tags.total_refs 47252087 # Total number of references to valid blocks. 147system.cpu.dcache.tags.warmup_cycle 802561250 # Cycle when the warmup percentage was hit. 148system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks 149system.cpu.dcache.writebacks::total 128565 # number of writebacks 150system.cpu.discardedOps 2952330 # Number of ops (including micro ops) which were discarded before commit 151system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 152system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 153system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 155system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 156system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 157system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 158system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 159system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 160system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 161system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 162system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 163system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 164system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 165system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 166system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 167system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 168system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 169system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 170system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 171system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 172system.cpu.dtb.accesses 0 # DTB accesses 173system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 174system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 175system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 176system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 177system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 178system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 179system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 180system.cpu.dtb.hits 0 # DTB hits 181system.cpu.dtb.inst_accesses 0 # ITB inst accesses 182system.cpu.dtb.inst_hits 0 # ITB inst hits 183system.cpu.dtb.inst_misses 0 # ITB inst misses 184system.cpu.dtb.misses 0 # DTB misses 185system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 186system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 187system.cpu.dtb.read_accesses 0 # DTB read accesses 188system.cpu.dtb.read_hits 0 # DTB read hits 189system.cpu.dtb.read_misses 0 # DTB read misses 190system.cpu.dtb.write_accesses 0 # DTB write accesses 191system.cpu.dtb.write_hits 0 # DTB write hits 192system.cpu.dtb.write_misses 0 # DTB write misses 193system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) 194system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) 195system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19971.672117 # average ReadReq miss latency 196system.cpu.icache.ReadReq_avg_miss_latency::total 19971.672117 # average ReadReq miss latency 197system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17929.897070 # average ReadReq mshr miss latency 198system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17929.897070 # average ReadReq mshr miss latency 199system.cpu.icache.ReadReq_hits::cpu.inst 27427302 # number of ReadReq hits 200system.cpu.icache.ReadReq_hits::total 27427302 # number of ReadReq hits 201system.cpu.icache.ReadReq_miss_latency::cpu.inst 910009240 # number of ReadReq miss cycles 202system.cpu.icache.ReadReq_miss_latency::total 910009240 # number of ReadReq miss cycles 203system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001659 # miss rate for ReadReq accesses 204system.cpu.icache.ReadReq_miss_rate::total 0.001659 # miss rate for ReadReq accesses 205system.cpu.icache.ReadReq_misses::cpu.inst 45565 # number of ReadReq misses 206system.cpu.icache.ReadReq_misses::total 45565 # number of ReadReq misses 207system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 816975760 # number of ReadReq MSHR miss cycles 208system.cpu.icache.ReadReq_mshr_miss_latency::total 816975760 # number of ReadReq MSHR miss cycles 209system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for ReadReq accesses 210system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001659 # mshr miss rate for ReadReq accesses 211system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45565 # number of ReadReq MSHR misses 212system.cpu.icache.ReadReq_mshr_misses::total 45565 # number of ReadReq MSHR misses 213system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 214system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 215system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 216system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 217system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 218system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 219system.cpu.icache.cache_copies 0 # number of cache copies performed 220system.cpu.icache.demand_accesses::cpu.inst 27472867 # number of demand (read+write) accesses 221system.cpu.icache.demand_accesses::total 27472867 # number of demand (read+write) accesses 222system.cpu.icache.demand_avg_miss_latency::cpu.inst 19971.672117 # average overall miss latency 223system.cpu.icache.demand_avg_miss_latency::total 19971.672117 # average overall miss latency 224system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17929.897070 # average overall mshr miss latency 225system.cpu.icache.demand_avg_mshr_miss_latency::total 17929.897070 # average overall mshr miss latency 226system.cpu.icache.demand_hits::cpu.inst 27427302 # number of demand (read+write) hits 227system.cpu.icache.demand_hits::total 27427302 # number of demand (read+write) hits 228system.cpu.icache.demand_miss_latency::cpu.inst 910009240 # number of demand (read+write) miss cycles 229system.cpu.icache.demand_miss_latency::total 910009240 # number of demand (read+write) miss cycles 230system.cpu.icache.demand_miss_rate::cpu.inst 0.001659 # miss rate for demand accesses 231system.cpu.icache.demand_miss_rate::total 0.001659 # miss rate for demand accesses 232system.cpu.icache.demand_misses::cpu.inst 45565 # number of demand (read+write) misses 233system.cpu.icache.demand_misses::total 45565 # number of demand (read+write) misses 234system.cpu.icache.demand_mshr_miss_latency::cpu.inst 816975760 # number of demand (read+write) MSHR miss cycles 235system.cpu.icache.demand_mshr_miss_latency::total 816975760 # number of demand (read+write) MSHR miss cycles 236system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for demand accesses 237system.cpu.icache.demand_mshr_miss_rate::total 0.001659 # mshr miss rate for demand accesses 238system.cpu.icache.demand_mshr_misses::cpu.inst 45565 # number of demand (read+write) MSHR misses 239system.cpu.icache.demand_mshr_misses::total 45565 # number of demand (read+write) MSHR misses 240system.cpu.icache.fast_writes 0 # number of fast writes performed 241system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 242system.cpu.icache.overall_accesses::cpu.inst 27472867 # number of overall (read+write) accesses 243system.cpu.icache.overall_accesses::total 27472867 # number of overall (read+write) accesses 244system.cpu.icache.overall_avg_miss_latency::cpu.inst 19971.672117 # average overall miss latency 245system.cpu.icache.overall_avg_miss_latency::total 19971.672117 # average overall miss latency 246system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17929.897070 # average overall mshr miss latency 247system.cpu.icache.overall_avg_mshr_miss_latency::total 17929.897070 # average overall mshr miss latency 248system.cpu.icache.overall_hits::cpu.inst 27427302 # number of overall hits 249system.cpu.icache.overall_hits::total 27427302 # number of overall hits 250system.cpu.icache.overall_miss_latency::cpu.inst 910009240 # number of overall miss cycles 251system.cpu.icache.overall_miss_latency::total 910009240 # number of overall miss cycles 252system.cpu.icache.overall_miss_rate::cpu.inst 0.001659 # miss rate for overall accesses 253system.cpu.icache.overall_miss_rate::total 0.001659 # miss rate for overall accesses 254system.cpu.icache.overall_misses::cpu.inst 45565 # number of overall misses 255system.cpu.icache.overall_misses::total 45565 # number of overall misses 256system.cpu.icache.overall_mshr_miss_latency::cpu.inst 816975760 # number of overall MSHR miss cycles 257system.cpu.icache.overall_mshr_miss_latency::total 816975760 # number of overall MSHR miss cycles 258system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for overall accesses 259system.cpu.icache.overall_mshr_miss_rate::total 0.001659 # mshr miss rate for overall accesses 260system.cpu.icache.overall_mshr_misses::cpu.inst 45565 # number of overall MSHR misses 261system.cpu.icache.overall_mshr_misses::total 45565 # number of overall MSHR misses 262system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 263system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id 264system.cpu.icache.tags.age_task_id_blocks_1024::3 727 # Occupied blocks per task id 265system.cpu.icache.tags.age_task_id_blocks_1024::4 1194 # Occupied blocks per task id 266system.cpu.icache.tags.avg_refs 601.951146 # Average number of references to valid blocks. 267system.cpu.icache.tags.data_accesses 54991298 # Number of data accesses 268system.cpu.icache.tags.occ_blocks::cpu.inst 1864.297147 # Average occupied blocks per requestor 269system.cpu.icache.tags.occ_percent::cpu.inst 0.910301 # Average percentage of cache occupancy 270system.cpu.icache.tags.occ_percent::total 0.910301 # Average percentage of cache occupancy 271system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id 272system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id 273system.cpu.icache.tags.replacements 43522 # number of replacements 274system.cpu.icache.tags.sampled_refs 45564 # Sample count of references to valid blocks. 275system.cpu.icache.tags.tag_accesses 54991298 # Number of tag accesses 276system.cpu.icache.tags.tagsinuse 1864.297147 # Cycle average of tags in use 277system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. 278system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 279system.cpu.idleCycles 19565206 # Total number of cycles that the CPU has spent unscheduled due to idling 280system.cpu.ipc 0.550869 # IPC: instructions per cycle 281system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 282system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 283system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 284system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 285system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 286system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 287system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 288system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 289system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 290system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 291system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 292system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 293system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 294system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 295system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 296system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 297system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 298system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 299system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 300system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 301system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 302system.cpu.itb.accesses 0 # DTB accesses 303system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 304system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 305system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 306system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 307system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 308system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 309system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 310system.cpu.itb.hits 0 # DTB hits 311system.cpu.itb.inst_accesses 0 # ITB inst accesses 312system.cpu.itb.inst_hits 0 # ITB inst hits 313system.cpu.itb.inst_misses 0 # ITB inst misses 314system.cpu.itb.misses 0 # DTB misses 315system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 316system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.itb.read_accesses 0 # DTB read accesses 318system.cpu.itb.read_hits 0 # DTB read hits 319system.cpu.itb.read_misses 0 # DTB read misses 320system.cpu.itb.write_accesses 0 # DTB write accesses 321system.cpu.itb.write_hits 0 # DTB write hits 322system.cpu.itb.write_misses 0 # DTB write misses 323system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107033 # number of ReadExReq accesses(hits+misses) 324system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) 325system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.821477 # average ReadExReq miss latency 326system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.821477 # average ReadExReq miss latency 327system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.466837 # average ReadExReq mshr miss latency 328system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.466837 # average ReadExReq mshr miss latency 329system.cpu.l2cache.ReadExReq_hits::cpu.inst 4766 # number of ReadExReq hits 330system.cpu.l2cache.ReadExReq_hits::total 4766 # number of ReadExReq hits 331system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7436940250 # number of ReadExReq miss cycles 332system.cpu.l2cache.ReadExReq_miss_latency::total 7436940250 # number of ReadExReq miss cycles 333system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955472 # miss rate for ReadExReq accesses 334system.cpu.l2cache.ReadExReq_miss_rate::total 0.955472 # miss rate for ReadExReq accesses 335system.cpu.l2cache.ReadExReq_misses::cpu.inst 102267 # number of ReadExReq misses 336system.cpu.l2cache.ReadExReq_misses::total 102267 # number of ReadExReq misses 337system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6118068750 # number of ReadExReq MSHR miss cycles 338system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6118068750 # number of ReadExReq MSHR miss cycles 339system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955472 # mshr miss rate for ReadExReq accesses 340system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955472 # mshr miss rate for ReadExReq accesses 341system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102267 # number of ReadExReq MSHR misses 342system.cpu.l2cache.ReadExReq_mshr_misses::total 102267 # number of ReadExReq MSHR misses 343system.cpu.l2cache.ReadReq_accesses::cpu.inst 99493 # number of ReadReq accesses(hits+misses) 344system.cpu.l2cache.ReadReq_accesses::total 99493 # number of ReadReq accesses(hits+misses) 345system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74187.493019 # average ReadReq miss latency 346system.cpu.l2cache.ReadReq_avg_miss_latency::total 74187.493019 # average ReadReq miss latency 347system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61477.049578 # average ReadReq mshr miss latency 348system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61477.049578 # average ReadReq mshr miss latency 349system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits 350system.cpu.l2cache.ReadReq_hits::total 72636 # number of ReadReq hits 351system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1992453500 # number of ReadReq miss cycles 352system.cpu.l2cache.ReadReq_miss_latency::total 1992453500 # number of ReadReq miss cycles 353system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269939 # miss rate for ReadReq accesses 354system.cpu.l2cache.ReadReq_miss_rate::total 0.269939 # miss rate for ReadReq accesses 355system.cpu.l2cache.ReadReq_misses::cpu.inst 26857 # number of ReadReq misses 356system.cpu.l2cache.ReadReq_misses::total 26857 # number of ReadReq misses 357system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits 358system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 359system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1646724250 # number of ReadReq MSHR miss cycles 360system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1646724250 # number of ReadReq MSHR miss cycles 361system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269225 # mshr miss rate for ReadReq accesses 362system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269225 # mshr miss rate for ReadReq accesses 363system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26786 # number of ReadReq MSHR misses 364system.cpu.l2cache.ReadReq_mshr_misses::total 26786 # number of ReadReq MSHR misses 365system.cpu.l2cache.Writeback_accesses::writebacks 128565 # number of Writeback accesses(hits+misses) 366system.cpu.l2cache.Writeback_accesses::total 128565 # number of Writeback accesses(hits+misses) 367system.cpu.l2cache.Writeback_hits::writebacks 128565 # number of Writeback hits 368system.cpu.l2cache.Writeback_hits::total 128565 # number of Writeback hits 369system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 370system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 371system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.l2cache.cache_copies 0 # number of cache copies performed 376system.cpu.l2cache.demand_accesses::cpu.inst 206526 # number of demand (read+write) accesses 377system.cpu.l2cache.demand_accesses::total 206526 # number of demand (read+write) accesses 378system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73025.880162 # average overall miss latency 379system.cpu.l2cache.demand_avg_miss_latency::total 73025.880162 # average overall miss latency 380system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60167.473829 # average overall mshr miss latency 381system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60167.473829 # average overall mshr miss latency 382system.cpu.l2cache.demand_hits::cpu.inst 77402 # number of demand (read+write) hits 383system.cpu.l2cache.demand_hits::total 77402 # number of demand (read+write) hits 384system.cpu.l2cache.demand_miss_latency::cpu.inst 9429393750 # number of demand (read+write) miss cycles 385system.cpu.l2cache.demand_miss_latency::total 9429393750 # number of demand (read+write) miss cycles 386system.cpu.l2cache.demand_miss_rate::cpu.inst 0.625219 # miss rate for demand accesses 387system.cpu.l2cache.demand_miss_rate::total 0.625219 # miss rate for demand accesses 388system.cpu.l2cache.demand_misses::cpu.inst 129124 # number of demand (read+write) misses 389system.cpu.l2cache.demand_misses::total 129124 # number of demand (read+write) misses 390system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits 391system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 392system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7764793000 # number of demand (read+write) MSHR miss cycles 393system.cpu.l2cache.demand_mshr_miss_latency::total 7764793000 # number of demand (read+write) MSHR miss cycles 394system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for demand accesses 395system.cpu.l2cache.demand_mshr_miss_rate::total 0.624875 # mshr miss rate for demand accesses 396system.cpu.l2cache.demand_mshr_misses::cpu.inst 129053 # number of demand (read+write) MSHR misses 397system.cpu.l2cache.demand_mshr_misses::total 129053 # number of demand (read+write) MSHR misses 398system.cpu.l2cache.fast_writes 0 # number of fast writes performed 399system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 400system.cpu.l2cache.overall_accesses::cpu.inst 206526 # number of overall (read+write) accesses 401system.cpu.l2cache.overall_accesses::total 206526 # number of overall (read+write) accesses 402system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73025.880162 # average overall miss latency 403system.cpu.l2cache.overall_avg_miss_latency::total 73025.880162 # average overall miss latency 404system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60167.473829 # average overall mshr miss latency 405system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60167.473829 # average overall mshr miss latency 406system.cpu.l2cache.overall_hits::cpu.inst 77402 # number of overall hits 407system.cpu.l2cache.overall_hits::total 77402 # number of overall hits 408system.cpu.l2cache.overall_miss_latency::cpu.inst 9429393750 # number of overall miss cycles 409system.cpu.l2cache.overall_miss_latency::total 9429393750 # number of overall miss cycles 410system.cpu.l2cache.overall_miss_rate::cpu.inst 0.625219 # miss rate for overall accesses 411system.cpu.l2cache.overall_miss_rate::total 0.625219 # miss rate for overall accesses 412system.cpu.l2cache.overall_misses::cpu.inst 129124 # number of overall misses 413system.cpu.l2cache.overall_misses::total 129124 # number of overall misses 414system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits 415system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits 416system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7764793000 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::total 7764793000 # number of overall MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for overall accesses 419system.cpu.l2cache.overall_mshr_miss_rate::total 0.624875 # mshr miss rate for overall accesses 420system.cpu.l2cache.overall_mshr_misses::cpu.inst 129053 # number of overall MSHR misses 421system.cpu.l2cache.overall_mshr_misses::total 129053 # number of overall MSHR misses 422system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id 423system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id 424system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id 425system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id 426system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id 427system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. 428system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses 429system.cpu.l2cache.tags.occ_blocks::writebacks 26739.141291 # Average occupied blocks per requestor 430system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.835051 # Average occupied blocks per requestor 431system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy 432system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy 433system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy 434system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id 435system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id 436system.cpu.l2cache.tags.replacements 95911 # number of replacements 437system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. 438system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses 439system.cpu.l2cache.tags.tagsinuse 30027.976342 # Cycle average of tags in use 440system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. 441system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 442system.cpu.l2cache.writebacks::writebacks 83957 # number of writebacks 443system.cpu.l2cache.writebacks::total 83957 # number of writebacks 444system.cpu.numCycles 128733163 # number of cpu cycles simulated 445system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 446system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 447system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 448system.cpu.tickCycles 109167957 # Number of cycles that the CPU actually ticked 449system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) 450system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) 451system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) 453system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) 454system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 455system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) 456system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 457system.cpu.toL2Bus.respLayer1.occupancy 269478939 # Layer occupancy (ticks) 458system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 459system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 460system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) 461system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) 462system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) 463system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) 464system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution 469system.cpu.workload.num_syscalls 1946 # Number of system calls 470system.cpu_clk_domain.clock 500 # Clock period in ticks 471system.membus.data_through_bus 13632576 # Total data (bytes) 472system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) 473system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) 474system.membus.reqLayer0.occupancy 975516000 # Layer occupancy (ticks) 475system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) 476system.membus.respLayer1.occupancy 1243562500 # Layer occupancy (ticks) 477system.membus.respLayer1.utilization 1.9 # Layer utilization (%) 478system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 479system.membus.throughput 211795868 # Throughput (bytes/s) 480system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) 481system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) 482system.membus.trans_dist::ReadReq 26785 # Transaction distribution 483system.membus.trans_dist::ReadResp 26785 # Transaction distribution 484system.membus.trans_dist::Writeback 83957 # Transaction distribution 485system.membus.trans_dist::ReadExReq 102267 # Transaction distribution 486system.membus.trans_dist::ReadExResp 102267 # Transaction distribution 487system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 488system.physmem.avgGap 302177.61 # Average gap between requests 489system.physmem.avgMemAccLat 30050.93 # Average memory access latency per DRAM burst 490system.physmem.avgQLat 11300.93 # Average queueing delay per DRAM burst 491system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s 492system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s 493system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 494system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s 495system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s 496system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing 497system.physmem.busUtil 1.65 # Data bus utilization in percentage 498system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads 499system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes 500system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) 501system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) | 16system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory 17system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory 21system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory |
| 502system.physmem.bw_read::cpu.inst 128317021 # Total read bandwidth from this memory (bytes/s) 503system.physmem.bw_read::total 128317021 # Total read bandwidth from this memory (bytes/s) | 26system.physmem.bw_read::cpu.inst 128317021 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 128317021 # Total read bandwidth from this memory (bytes/s) |
| 28system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) |
|
| 504system.physmem.bw_total::writebacks 83478847 # Total bandwidth to/from this memory (bytes/s) 505system.physmem.bw_total::cpu.inst 128317021 # Total bandwidth to/from this memory (bytes/s) 506system.physmem.bw_total::total 211795868 # Total bandwidth to/from this memory (bytes/s) | 32system.physmem.bw_total::writebacks 83478847 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 128317021 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 211795868 # Total bandwidth to/from this memory (bytes/s) |
| 507system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) 508system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) 509system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation 510system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation 511system.physmem.bytesPerActivate::gmean 212.915649 # Bytes accessed per row activation 512system.physmem.bytesPerActivate::stdev 334.657943 # Bytes accessed per row activation 513system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::384-511 2766 7.13% 71.07% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::512-639 2568 6.62% 77.68% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::640-767 1673 4.31% 81.99% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::768-895 1314 3.38% 85.38% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::896-1023 1198 3.09% 88.46% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::1024-1151 4478 11.54% 100.00% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation | 35system.physmem.readReqs 129052 # Number of read requests accepted 36system.physmem.writeReqs 83957 # Number of write requests accepted 37system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue |
| 523system.physmem.bytesReadDRAM 8258880 # Total number of bytes read from DRAM | 39system.physmem.bytesReadDRAM 8258880 # Total number of bytes read from DRAM |
| 524system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side | |
| 525system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue 526system.physmem.bytesWritten 5371584 # Total number of bytes written to DRAM | 40system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue 41system.physmem.bytesWritten 5371584 # Total number of bytes written to DRAM |
| 42system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side |
|
| 527system.physmem.bytesWrittenSys 5373248 # Total written bytes from the system interface side | 43system.physmem.bytesWrittenSys 5373248 # Total written bytes from the system interface side |
| 528system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory 529system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory 530system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory 531system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory 532system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory 533system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory 534system.physmem.memoryStateTime::IDLE 37439884750 # Time in different power states 535system.physmem.memoryStateTime::REF 2149160000 # Time in different power states 536system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 537system.physmem.memoryStateTime::ACT 24772371500 # Time in different power states 538system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 44system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue |
| 539system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 540system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 541system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 542system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 543system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory 544system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory 545system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory 546system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory 547system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined 548system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | |
| 549system.physmem.perBankRdBursts::0 8196 # Per bank write bursts 550system.physmem.perBankRdBursts::1 8381 # Per bank write bursts 551system.physmem.perBankRdBursts::2 8249 # Per bank write bursts 552system.physmem.perBankRdBursts::3 8185 # Per bank write bursts 553system.physmem.perBankRdBursts::4 8327 # Per bank write bursts 554system.physmem.perBankRdBursts::5 8459 # Per bank write bursts 555system.physmem.perBankRdBursts::6 8094 # Per bank write bursts 556system.physmem.perBankRdBursts::7 7981 # Per bank write bursts --- 16 unchanged lines hidden (view full) --- 573system.physmem.perBankWrBursts::8 5034 # Per bank write bursts 574system.physmem.perBankWrBursts::9 5087 # Per bank write bursts 575system.physmem.perBankWrBursts::10 5251 # Per bank write bursts 576system.physmem.perBankWrBursts::11 5146 # Per bank write bursts 577system.physmem.perBankWrBursts::12 5344 # Per bank write bursts 578system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 579system.physmem.perBankWrBursts::14 5451 # Per bank write bursts 580system.physmem.perBankWrBursts::15 5227 # Per bank write bursts | 47system.physmem.perBankRdBursts::0 8196 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8381 # Per bank write bursts 49system.physmem.perBankRdBursts::2 8249 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8185 # Per bank write bursts 51system.physmem.perBankRdBursts::4 8327 # Per bank write bursts 52system.physmem.perBankRdBursts::5 8459 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8094 # Per bank write bursts 54system.physmem.perBankRdBursts::7 7981 # Per bank write bursts --- 16 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::8 5034 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5087 # Per bank write bursts 73system.physmem.perBankWrBursts::10 5251 # Per bank write bursts 74system.physmem.perBankWrBursts::11 5146 # Per bank write bursts 75system.physmem.perBankWrBursts::12 5344 # Per bank write bursts 76system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5451 # Per bank write bursts 78system.physmem.perBankWrBursts::15 5227 # Per bank write bursts |
| 581system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes 582system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes 583system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes 584system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes 585system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes 586system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 587system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes 588system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes | 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 81system.physmem.totGap 64366550000 # Total gap between requests 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) 88system.physmem.readPktSize::6 129052 # Read request sizes (log2) 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) 95system.physmem.writePktSize::6 83957 # Write request sizes (log2) |
| 589system.physmem.rdQLenPdf::0 128466 # What read queue length does an incoming req see 590system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see 591system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see 592system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 593system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 594system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 595system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 596system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 613system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 614system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 615system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 616system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 617system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 618system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 619system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 620system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 96system.physmem.rdQLenPdf::0 128466 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 621system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue 622system.physmem.readPktSize::0 0 # Read request sizes (log2) 623system.physmem.readPktSize::1 0 # Read request sizes (log2) 624system.physmem.readPktSize::2 0 # Read request sizes (log2) 625system.physmem.readPktSize::3 0 # Read request sizes (log2) 626system.physmem.readPktSize::4 0 # Read request sizes (log2) 627system.physmem.readPktSize::5 0 # Read request sizes (log2) 628system.physmem.readPktSize::6 129052 # Read request sizes (log2) 629system.physmem.readReqs 129052 # Number of read requests accepted 630system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads 631system.physmem.readRowHits 112129 # Number of row buffer hits during reads 632system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue 633system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers 634system.physmem.totGap 64366550000 # Total gap between requests 635system.physmem.totMemAccLat 3877921750 # Total ticks spent from burst creation until serviced by the DRAM 636system.physmem.totQLat 1458328000 # Total ticks spent queuing 637system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads 638system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads 639system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads 640system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads 641system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads 642system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads 643system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads 644system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads 645system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads 646system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads 647system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads 648system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads 649system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads 650system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads 651system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads | |
| 652system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 653system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 654system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 655system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 656system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 657system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 658system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 659system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see --- 48 unchanged lines hidden (view full) --- 708system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 709system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 710system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 711system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 712system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 713system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 714system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 715system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 128system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see --- 48 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 716system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue 717system.physmem.writePktSize::0 0 # Write request sizes (log2) 718system.physmem.writePktSize::1 0 # Write request sizes (log2) 719system.physmem.writePktSize::2 0 # Write request sizes (log2) 720system.physmem.writePktSize::3 0 # Write request sizes (log2) 721system.physmem.writePktSize::4 0 # Write request sizes (log2) 722system.physmem.writePktSize::5 0 # Write request sizes (log2) 723system.physmem.writePktSize::6 83957 # Write request sizes (log2) 724system.physmem.writeReqs 83957 # Number of write requests accepted 725system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes | 192system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 212.918314 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 334.655421 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 2767 7.13% 71.07% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2567 6.61% 77.68% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1675 4.31% 82.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 1312 3.38% 85.38% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 1197 3.08% 88.46% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 4479 11.54% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes 214system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads 229system.physmem.totQLat 1458157250 # Total ticks spent queuing 230system.physmem.totMemAccLat 3877751000 # Total ticks spent from burst creation until serviced by the DRAM 231system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers 232system.physmem.avgQLat 11299.60 # Average queueing delay per DRAM burst 233system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 234system.physmem.avgMemAccLat 30049.60 # Average memory access latency per DRAM burst 235system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s 236system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s 237system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s 238system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s 239system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 240system.physmem.busUtil 1.65 # Data bus utilization in percentage 241system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads 242system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes 243system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 244system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing 245system.physmem.readRowHits 112129 # Number of row buffer hits during reads |
| 726system.physmem.writeRowHits 62016 # Number of row buffer hits during writes | 246system.physmem.writeRowHits 62016 # Number of row buffer hits during writes |
| 727system.voltage_domain.voltage 1 # Voltage in Volts | 247system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads 248system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes 249system.physmem.avgGap 302177.61 # Average gap between requests 250system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined 251system.physmem.memoryStateTime::IDLE 37447706500 # Time in different power states 252system.physmem.memoryStateTime::REF 2149160000 # Time in different power states 253system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 254system.physmem.memoryStateTime::ACT 24764549750 # Time in different power states 255system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 256system.membus.throughput 211795868 # Throughput (bytes/s) 257system.membus.trans_dist::ReadReq 26785 # Transaction distribution 258system.membus.trans_dist::ReadResp 26785 # Transaction distribution 259system.membus.trans_dist::Writeback 83957 # Transaction distribution 260system.membus.trans_dist::ReadExReq 102267 # Transaction distribution 261system.membus.trans_dist::ReadExResp 102267 # Transaction distribution 262system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) 263system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) 264system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) 265system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) 266system.membus.data_through_bus 13632576 # Total data (bytes) 267system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 268system.membus.reqLayer0.occupancy 975516500 # Layer occupancy (ticks) 269system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) 270system.membus.respLayer1.occupancy 1243562250 # Layer occupancy (ticks) 271system.membus.respLayer1.utilization 1.9 # Layer utilization (%) 272system.cpu_clk_domain.clock 500 # Clock period in ticks 273system.cpu.branchPred.lookups 16883830 # Number of BP lookups 274system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted 275system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect 276system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups 277system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits 278system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 279system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage 280system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. 281system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. 282system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 283system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 284system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 285system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 286system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 287system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 288system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 289system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 290system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 292system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 293system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 294system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 295system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 296system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 298system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 299system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 300system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 301system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 302system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 303system.cpu.dtb.inst_hits 0 # ITB inst hits 304system.cpu.dtb.inst_misses 0 # ITB inst misses 305system.cpu.dtb.read_hits 0 # DTB read hits 306system.cpu.dtb.read_misses 0 # DTB read misses 307system.cpu.dtb.write_hits 0 # DTB write hits 308system.cpu.dtb.write_misses 0 # DTB write misses 309system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 310system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 311system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 312system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 313system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 314system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 315system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 316system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 317system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.dtb.read_accesses 0 # DTB read accesses 319system.cpu.dtb.write_accesses 0 # DTB write accesses 320system.cpu.dtb.inst_accesses 0 # ITB inst accesses 321system.cpu.dtb.hits 0 # DTB hits 322system.cpu.dtb.misses 0 # DTB misses 323system.cpu.dtb.accesses 0 # DTB accesses 324system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 325system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 326system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 327system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 328system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 329system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 330system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 331system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 332system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 333system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 334system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 335system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 336system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 337system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 338system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 339system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 340system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 341system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 342system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 343system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 344system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 345system.cpu.itb.inst_hits 0 # ITB inst hits 346system.cpu.itb.inst_misses 0 # ITB inst misses 347system.cpu.itb.read_hits 0 # DTB read hits 348system.cpu.itb.read_misses 0 # DTB read misses 349system.cpu.itb.write_hits 0 # DTB write hits 350system.cpu.itb.write_misses 0 # DTB write misses 351system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 352system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 353system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 354system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 355system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 356system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 357system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 358system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 359system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 360system.cpu.itb.read_accesses 0 # DTB read accesses 361system.cpu.itb.write_accesses 0 # DTB write accesses 362system.cpu.itb.inst_accesses 0 # ITB inst accesses 363system.cpu.itb.hits 0 # DTB hits 364system.cpu.itb.misses 0 # DTB misses 365system.cpu.itb.accesses 0 # DTB accesses 366system.cpu.workload.num_syscalls 1946 # Number of system calls 367system.cpu.numCycles 128733163 # number of cpu cycles simulated 368system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 369system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 370system.cpu.committedInsts 70915127 # Number of instructions committed 371system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed 372system.cpu.discardedOps 2952341 # Number of ops (including micro ops) which were discarded before commit 373system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 374system.cpu.cpi 1.815313 # CPI: cycles per instruction 375system.cpu.ipc 0.550869 # IPC: instructions per cycle 376system.cpu.tickCycles 109168240 # Number of cycles that the object actually ticked 377system.cpu.idleCycles 19564923 # Total number of cycles that the object has spent stopped 378system.cpu.icache.tags.replacements 43522 # number of replacements 379system.cpu.icache.tags.tagsinuse 1864.297124 # Cycle average of tags in use 380system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. 381system.cpu.icache.tags.sampled_refs 45564 # Sample count of references to valid blocks. 382system.cpu.icache.tags.avg_refs 601.951146 # Average number of references to valid blocks. 383system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 384system.cpu.icache.tags.occ_blocks::cpu.inst 1864.297124 # Average occupied blocks per requestor 385system.cpu.icache.tags.occ_percent::cpu.inst 0.910301 # Average percentage of cache occupancy 386system.cpu.icache.tags.occ_percent::total 0.910301 # Average percentage of cache occupancy 387system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id 388system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 389system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id 390system.cpu.icache.tags.age_task_id_blocks_1024::3 727 # Occupied blocks per task id 391system.cpu.icache.tags.age_task_id_blocks_1024::4 1194 # Occupied blocks per task id 392system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id 393system.cpu.icache.tags.tag_accesses 54991298 # Number of tag accesses 394system.cpu.icache.tags.data_accesses 54991298 # Number of data accesses 395system.cpu.icache.ReadReq_hits::cpu.inst 27427302 # number of ReadReq hits 396system.cpu.icache.ReadReq_hits::total 27427302 # number of ReadReq hits 397system.cpu.icache.demand_hits::cpu.inst 27427302 # number of demand (read+write) hits 398system.cpu.icache.demand_hits::total 27427302 # number of demand (read+write) hits 399system.cpu.icache.overall_hits::cpu.inst 27427302 # number of overall hits 400system.cpu.icache.overall_hits::total 27427302 # number of overall hits 401system.cpu.icache.ReadReq_misses::cpu.inst 45565 # number of ReadReq misses 402system.cpu.icache.ReadReq_misses::total 45565 # number of ReadReq misses 403system.cpu.icache.demand_misses::cpu.inst 45565 # number of demand (read+write) misses 404system.cpu.icache.demand_misses::total 45565 # number of demand (read+write) misses 405system.cpu.icache.overall_misses::cpu.inst 45565 # number of overall misses 406system.cpu.icache.overall_misses::total 45565 # number of overall misses 407system.cpu.icache.ReadReq_miss_latency::cpu.inst 909865240 # number of ReadReq miss cycles 408system.cpu.icache.ReadReq_miss_latency::total 909865240 # number of ReadReq miss cycles 409system.cpu.icache.demand_miss_latency::cpu.inst 909865240 # number of demand (read+write) miss cycles 410system.cpu.icache.demand_miss_latency::total 909865240 # number of demand (read+write) miss cycles 411system.cpu.icache.overall_miss_latency::cpu.inst 909865240 # number of overall miss cycles 412system.cpu.icache.overall_miss_latency::total 909865240 # number of overall miss cycles 413system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) 414system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) 415system.cpu.icache.demand_accesses::cpu.inst 27472867 # number of demand (read+write) accesses 416system.cpu.icache.demand_accesses::total 27472867 # number of demand (read+write) accesses 417system.cpu.icache.overall_accesses::cpu.inst 27472867 # number of overall (read+write) accesses 418system.cpu.icache.overall_accesses::total 27472867 # number of overall (read+write) accesses 419system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001659 # miss rate for ReadReq accesses 420system.cpu.icache.ReadReq_miss_rate::total 0.001659 # miss rate for ReadReq accesses 421system.cpu.icache.demand_miss_rate::cpu.inst 0.001659 # miss rate for demand accesses 422system.cpu.icache.demand_miss_rate::total 0.001659 # miss rate for demand accesses 423system.cpu.icache.overall_miss_rate::cpu.inst 0.001659 # miss rate for overall accesses 424system.cpu.icache.overall_miss_rate::total 0.001659 # miss rate for overall accesses 425system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19968.511796 # average ReadReq miss latency 426system.cpu.icache.ReadReq_avg_miss_latency::total 19968.511796 # average ReadReq miss latency 427system.cpu.icache.demand_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency 428system.cpu.icache.demand_avg_miss_latency::total 19968.511796 # average overall miss latency 429system.cpu.icache.overall_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency 430system.cpu.icache.overall_avg_miss_latency::total 19968.511796 # average overall miss latency 431system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 432system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 433system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 434system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 435system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 436system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 437system.cpu.icache.fast_writes 0 # number of fast writes performed 438system.cpu.icache.cache_copies 0 # number of cache copies performed 439system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45565 # number of ReadReq MSHR misses 440system.cpu.icache.ReadReq_mshr_misses::total 45565 # number of ReadReq MSHR misses 441system.cpu.icache.demand_mshr_misses::cpu.inst 45565 # number of demand (read+write) MSHR misses 442system.cpu.icache.demand_mshr_misses::total 45565 # number of demand (read+write) MSHR misses 443system.cpu.icache.overall_mshr_misses::cpu.inst 45565 # number of overall MSHR misses 444system.cpu.icache.overall_mshr_misses::total 45565 # number of overall MSHR misses 445system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 816831760 # number of ReadReq MSHR miss cycles 446system.cpu.icache.ReadReq_mshr_miss_latency::total 816831760 # number of ReadReq MSHR miss cycles 447system.cpu.icache.demand_mshr_miss_latency::cpu.inst 816831760 # number of demand (read+write) MSHR miss cycles 448system.cpu.icache.demand_mshr_miss_latency::total 816831760 # number of demand (read+write) MSHR miss cycles 449system.cpu.icache.overall_mshr_miss_latency::cpu.inst 816831760 # number of overall MSHR miss cycles 450system.cpu.icache.overall_mshr_miss_latency::total 816831760 # number of overall MSHR miss cycles 451system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for ReadReq accesses 452system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001659 # mshr miss rate for ReadReq accesses 453system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for demand accesses 454system.cpu.icache.demand_mshr_miss_rate::total 0.001659 # mshr miss rate for demand accesses 455system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for overall accesses 456system.cpu.icache.overall_mshr_miss_rate::total 0.001659 # mshr miss rate for overall accesses 457system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17926.736750 # average ReadReq mshr miss latency 458system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17926.736750 # average ReadReq mshr miss latency 459system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency 460system.cpu.icache.demand_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency 461system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency 462system.cpu.icache.overall_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency 463system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 464system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) 465system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution 470system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) 472system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) 473system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) 475system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) 476system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) 477system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 478system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) 479system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 480system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) 481system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 482system.cpu.toL2Bus.respLayer1.occupancy 269478689 # Layer occupancy (ticks) 483system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 484system.cpu.l2cache.tags.replacements 95911 # number of replacements 485system.cpu.l2cache.tags.tagsinuse 30027.975303 # Cycle average of tags in use 486system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. 487system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. 488system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. 489system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 490system.cpu.l2cache.tags.occ_blocks::writebacks 26739.140336 # Average occupied blocks per requestor 491system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.834967 # Average occupied blocks per requestor 492system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy 493system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy 494system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy 495system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id 496system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id 497system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id 498system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id 499system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id 500system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id 501system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id 502system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses 503system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses 504system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits 505system.cpu.l2cache.ReadReq_hits::total 72636 # number of ReadReq hits 506system.cpu.l2cache.Writeback_hits::writebacks 128565 # number of Writeback hits 507system.cpu.l2cache.Writeback_hits::total 128565 # number of Writeback hits 508system.cpu.l2cache.ReadExReq_hits::cpu.inst 4766 # number of ReadExReq hits 509system.cpu.l2cache.ReadExReq_hits::total 4766 # number of ReadExReq hits 510system.cpu.l2cache.demand_hits::cpu.inst 77402 # number of demand (read+write) hits 511system.cpu.l2cache.demand_hits::total 77402 # number of demand (read+write) hits 512system.cpu.l2cache.overall_hits::cpu.inst 77402 # number of overall hits 513system.cpu.l2cache.overall_hits::total 77402 # number of overall hits 514system.cpu.l2cache.ReadReq_misses::cpu.inst 26857 # number of ReadReq misses 515system.cpu.l2cache.ReadReq_misses::total 26857 # number of ReadReq misses 516system.cpu.l2cache.ReadExReq_misses::cpu.inst 102267 # number of ReadExReq misses 517system.cpu.l2cache.ReadExReq_misses::total 102267 # number of ReadExReq misses 518system.cpu.l2cache.demand_misses::cpu.inst 129124 # number of demand (read+write) misses 519system.cpu.l2cache.demand_misses::total 129124 # number of demand (read+write) misses 520system.cpu.l2cache.overall_misses::cpu.inst 129124 # number of overall misses 521system.cpu.l2cache.overall_misses::total 129124 # number of overall misses 522system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1992283500 # number of ReadReq miss cycles 523system.cpu.l2cache.ReadReq_miss_latency::total 1992283500 # number of ReadReq miss cycles 524system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7436939000 # number of ReadExReq miss cycles 525system.cpu.l2cache.ReadExReq_miss_latency::total 7436939000 # number of ReadExReq miss cycles 526system.cpu.l2cache.demand_miss_latency::cpu.inst 9429222500 # number of demand (read+write) miss cycles 527system.cpu.l2cache.demand_miss_latency::total 9429222500 # number of demand (read+write) miss cycles 528system.cpu.l2cache.overall_miss_latency::cpu.inst 9429222500 # number of overall miss cycles 529system.cpu.l2cache.overall_miss_latency::total 9429222500 # number of overall miss cycles 530system.cpu.l2cache.ReadReq_accesses::cpu.inst 99493 # number of ReadReq accesses(hits+misses) 531system.cpu.l2cache.ReadReq_accesses::total 99493 # number of ReadReq accesses(hits+misses) 532system.cpu.l2cache.Writeback_accesses::writebacks 128565 # number of Writeback accesses(hits+misses) 533system.cpu.l2cache.Writeback_accesses::total 128565 # number of Writeback accesses(hits+misses) 534system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107033 # number of ReadExReq accesses(hits+misses) 535system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) 536system.cpu.l2cache.demand_accesses::cpu.inst 206526 # number of demand (read+write) accesses 537system.cpu.l2cache.demand_accesses::total 206526 # number of demand (read+write) accesses 538system.cpu.l2cache.overall_accesses::cpu.inst 206526 # number of overall (read+write) accesses 539system.cpu.l2cache.overall_accesses::total 206526 # number of overall (read+write) accesses 540system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269939 # miss rate for ReadReq accesses 541system.cpu.l2cache.ReadReq_miss_rate::total 0.269939 # miss rate for ReadReq accesses 542system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955472 # miss rate for ReadExReq accesses 543system.cpu.l2cache.ReadExReq_miss_rate::total 0.955472 # miss rate for ReadExReq accesses 544system.cpu.l2cache.demand_miss_rate::cpu.inst 0.625219 # miss rate for demand accesses 545system.cpu.l2cache.demand_miss_rate::total 0.625219 # miss rate for demand accesses 546system.cpu.l2cache.overall_miss_rate::cpu.inst 0.625219 # miss rate for overall accesses 547system.cpu.l2cache.overall_miss_rate::total 0.625219 # miss rate for overall accesses 548system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74181.163198 # average ReadReq miss latency 549system.cpu.l2cache.ReadReq_avg_miss_latency::total 74181.163198 # average ReadReq miss latency 550system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.809254 # average ReadExReq miss latency 551system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.809254 # average ReadExReq miss latency 552system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency 553system.cpu.l2cache.demand_avg_miss_latency::total 73024.553917 # average overall miss latency 554system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency 555system.cpu.l2cache.overall_avg_miss_latency::total 73024.553917 # average overall miss latency 556system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 559system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 561system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 562system.cpu.l2cache.fast_writes 0 # number of fast writes performed 563system.cpu.l2cache.cache_copies 0 # number of cache copies performed 564system.cpu.l2cache.writebacks::writebacks 83957 # number of writebacks 565system.cpu.l2cache.writebacks::total 83957 # number of writebacks 566system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits 567system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 568system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits 569system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 570system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits 571system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits 572system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26786 # number of ReadReq MSHR misses 573system.cpu.l2cache.ReadReq_mshr_misses::total 26786 # number of ReadReq MSHR misses 574system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102267 # number of ReadExReq MSHR misses 575system.cpu.l2cache.ReadExReq_mshr_misses::total 102267 # number of ReadExReq MSHR misses 576system.cpu.l2cache.demand_mshr_misses::cpu.inst 129053 # number of demand (read+write) MSHR misses 577system.cpu.l2cache.demand_mshr_misses::total 129053 # number of demand (read+write) MSHR misses 578system.cpu.l2cache.overall_mshr_misses::cpu.inst 129053 # number of overall MSHR misses 579system.cpu.l2cache.overall_mshr_misses::total 129053 # number of overall MSHR misses 580system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1646558250 # number of ReadReq MSHR miss cycles 581system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1646558250 # number of ReadReq MSHR miss cycles 582system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6118064000 # number of ReadExReq MSHR miss cycles 583system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6118064000 # number of ReadExReq MSHR miss cycles 584system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7764622250 # number of demand (read+write) MSHR miss cycles 585system.cpu.l2cache.demand_mshr_miss_latency::total 7764622250 # number of demand (read+write) MSHR miss cycles 586system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7764622250 # number of overall MSHR miss cycles 587system.cpu.l2cache.overall_mshr_miss_latency::total 7764622250 # number of overall MSHR miss cycles 588system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269225 # mshr miss rate for ReadReq accesses 589system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269225 # mshr miss rate for ReadReq accesses 590system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955472 # mshr miss rate for ReadExReq accesses 591system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955472 # mshr miss rate for ReadExReq accesses 592system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for demand accesses 593system.cpu.l2cache.demand_mshr_miss_rate::total 0.624875 # mshr miss rate for demand accesses 594system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for overall accesses 595system.cpu.l2cache.overall_mshr_miss_rate::total 0.624875 # mshr miss rate for overall accesses 596system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61470.852311 # average ReadReq mshr miss latency 597system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61470.852311 # average ReadReq mshr miss latency 598system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.420390 # average ReadExReq mshr miss latency 599system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.420390 # average ReadExReq mshr miss latency 600system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency 601system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency 602system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency 603system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency 604system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 605system.cpu.dcache.tags.replacements 156865 # number of replacements 606system.cpu.dcache.tags.tagsinuse 4070.633737 # Cycle average of tags in use 607system.cpu.dcache.tags.total_refs 47252087 # Total number of references to valid blocks. 608system.cpu.dcache.tags.sampled_refs 160961 # Sample count of references to valid blocks. 609system.cpu.dcache.tags.avg_refs 293.562335 # Average number of references to valid blocks. 610system.cpu.dcache.tags.warmup_cycle 802561250 # Cycle when the warmup percentage was hit. 611system.cpu.dcache.tags.occ_blocks::cpu.inst 4070.633737 # Average occupied blocks per requestor 612system.cpu.dcache.tags.occ_percent::cpu.inst 0.993807 # Average percentage of cache occupancy 613system.cpu.dcache.tags.occ_percent::total 0.993807 # Average percentage of cache occupancy 614system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 615system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 616system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id 617system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id 618system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 619system.cpu.dcache.tags.tag_accesses 95193929 # Number of tag accesses 620system.cpu.dcache.tags.data_accesses 95193929 # Number of data accesses 621system.cpu.dcache.ReadReq_hits::cpu.inst 27577955 # number of ReadReq hits 622system.cpu.dcache.ReadReq_hits::total 27577955 # number of ReadReq hits 623system.cpu.dcache.WriteReq_hits::cpu.inst 19642294 # number of WriteReq hits 624system.cpu.dcache.WriteReq_hits::total 19642294 # number of WriteReq hits 625system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits 626system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 627system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits 628system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 629system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits 630system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits 631system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits 632system.cpu.dcache.overall_hits::total 47220249 # number of overall hits 633system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses 634system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses 635system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses 636system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses 637system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses 638system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses 639system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses 640system.cpu.dcache.overall_misses::total 264397 # number of overall misses 641system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169299439 # number of ReadReq miss cycles 642system.cpu.dcache.ReadReq_miss_latency::total 2169299439 # number of ReadReq miss cycles 643system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315314750 # number of WriteReq miss cycles 644system.cpu.dcache.WriteReq_miss_latency::total 15315314750 # number of WriteReq miss cycles 645system.cpu.dcache.demand_miss_latency::cpu.inst 17484614189 # number of demand (read+write) miss cycles 646system.cpu.dcache.demand_miss_latency::total 17484614189 # number of demand (read+write) miss cycles 647system.cpu.dcache.overall_miss_latency::cpu.inst 17484614189 # number of overall miss cycles 648system.cpu.dcache.overall_miss_latency::total 17484614189 # number of overall miss cycles 649system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # number of ReadReq accesses(hits+misses) 650system.cpu.dcache.ReadReq_accesses::total 27634745 # number of ReadReq accesses(hits+misses) 651system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) 652system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 653system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) 654system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 655system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) 656system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 657system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses 658system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses 659system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses 660system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses 661system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses 662system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses 663system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses 664system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses 665system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses 666system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses 667system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses 668system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses 669system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38198.616640 # average ReadReq miss latency 670system.cpu.dcache.ReadReq_avg_miss_latency::total 38198.616640 # average ReadReq miss latency 671system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73770.704986 # average WriteReq miss latency 672system.cpu.dcache.WriteReq_avg_miss_latency::total 73770.704986 # average WriteReq miss latency 673system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency 674system.cpu.dcache.demand_avg_miss_latency::total 66130.153478 # average overall miss latency 675system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency 676system.cpu.dcache.overall_avg_miss_latency::total 66130.153478 # average overall miss latency 677system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 678system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 679system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 680system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 681system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 682system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 683system.cpu.dcache.fast_writes 0 # number of fast writes performed 684system.cpu.dcache.cache_copies 0 # number of cache copies performed 685system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks 686system.cpu.dcache.writebacks::total 128565 # number of writebacks 687system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits 688system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits 689system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits 690system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits 691system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits 692system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits 693system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits 694system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits 695system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses 696system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses 697system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses 698system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses 699system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses 700system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses 701system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses 702system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses 703system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001760311 # number of ReadReq MSHR miss cycles 704system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001760311 # number of ReadReq MSHR miss cycles 705system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591657000 # number of WriteReq MSHR miss cycles 706system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591657000 # number of WriteReq MSHR miss cycles 707system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593417311 # number of demand (read+write) MSHR miss cycles 708system.cpu.dcache.demand_mshr_miss_latency::total 9593417311 # number of demand (read+write) MSHR miss cycles 709system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593417311 # number of overall MSHR miss cycles 710system.cpu.dcache.overall_mshr_miss_latency::total 9593417311 # number of overall MSHR miss cycles 711system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses 712system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses 713system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses 714system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 715system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses 716system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses 717system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses 718system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses 719system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.127559 # average ReadReq mshr miss latency 720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.127559 # average ReadReq mshr miss latency 721system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.190371 # average WriteReq mshr miss latency 722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.190371 # average WriteReq mshr miss latency 723system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency 724system.cpu.dcache.demand_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency 725system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency 726system.cpu.dcache.overall_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency 727system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 728 729---------- End Simulation Statistics ---------- | 728 729---------- End Simulation Statistics ---------- |