3,5c3,5
< sim_seconds 0.060131 # Number of seconds simulated
< sim_ticks 60130734500 # Number of ticks simulated
< final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.060132 # Number of seconds simulated
> sim_ticks 60131512500 # Number of ticks simulated
> final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 310652 # Simulator instruction rate (inst/s)
< host_op_rate 397278 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 263409545 # Simulator tick rate (ticks/s)
< host_mem_usage 281384 # Number of bytes of host memory used
< host_seconds 228.28 # Real time elapsed on the host
---
> host_inst_rate 320494 # Simulator instruction rate (inst/s)
> host_op_rate 409865 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 271758284 # Simulator tick rate (ticks/s)
> host_mem_usage 281048 # Number of bytes of host memory used
> host_seconds 221.27 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
29,39c29,39
< system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s)
86c86
< system.physmem.totGap 60130703000 # Total gap between requests
---
> system.physmem.totGap 60131481000 # Total gap between requests
199,204c199,204
< system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation
206,208c206,208
< system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation
230,231c230,231
< system.physmem.totQLat 3048956750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3049168000 # Total ticks spent queuing
> system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM
233c233
< system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst
235c235
< system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst
250c250
< system.physmem.avgGap 279590.56 # Average gap between requests
---
> system.physmem.avgGap 279594.18 # Average gap between requests
256,270c256,270
< system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ)
< system.physmem_0.averagePower 386.883743 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states
---
> system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ)
> system.physmem_0.averagePower 386.918165 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states
276,284c276,284
< system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ)
< system.physmem_1.averagePower 383.200220 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states
---
> system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ)
> system.physmem_1.averagePower 383.198268 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states
286,290c286,290
< system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
294c294
< system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups
297,298c297,298
< system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target.
305c305
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
335c335
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
365c365
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
395c395
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
426,427c426,427
< system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 120261469 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 120263025 # number of cpu cycles simulated
434,435c434,435
< system.cpu.cpi 1.695850 # CPI: cycles per instruction
< system.cpu.ipc 0.589675 # IPC: instructions per cycle
---
> system.cpu.cpi 1.695872 # CPI: cycles per instruction
> system.cpu.ipc 0.589667 # IPC: instructions per cycle
475,477c475,477
< system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
479,480c479,480
< system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks.
482c482
< system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks.
484c484
< system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor
492,496c492,496
< system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits
505,508c505,508
< system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits
< system.cpu.dcache.overall_hits::total 42605457 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits
> system.cpu.dcache.overall_hits::total 42605460 # number of overall hits
519,528c519,528
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses)
537,540c537,540
< system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses
551,558c551,558
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency
585,594c585,594
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles
605,615c605,615
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
617c617
< system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1851.999823 # Cycle average of tags in use
622,624c622,624
< system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1851.999823 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.904297 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.904297 # Average percentage of cache occupancy
634c634
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
647,652c647,652
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042263500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 1042263500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 1042263500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 1042263500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 1042263500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 1042263500 # number of overall miss cycles
665,670c665,670
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 22862.672194 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 22862.672194 # average overall miss latency
685,690c685,690
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996676500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 996676500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996676500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 996676500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996676500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 996676500 # number of overall MSHR miss cycles
697,703c697,703
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.694130 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.694130 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
705c705
< system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 31292.341702 # Cycle average of tags in use
709,712c709,712
< system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.warmup_cycle 10980599000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 476.632754 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.083150 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.625798 # Average occupied blocks per requestor
726c726
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
755,766c755,766
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269327500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9269327500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492863000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 492863000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2253034500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 2253034500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 492863000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11522362000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12015225000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 492863000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11522362000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12015225000 # number of overall miss cycles
795,806c795,806
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.207219 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.207219 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109842.433697 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109842.433697 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103426.115498 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103426.115498 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 93439.706660 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 93439.706660 # average overall miss latency
839,850c839,850
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246157500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246157500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446695500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446695500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029647000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029647000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446695500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275804500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10722500000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446695500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275804500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 10722500000 # number of overall MSHR miss cycles
865,876c865,876
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency
883c883
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
923c923
< system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
946c946
< system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks)
948c948
< system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks)
< sim_seconds 0.060131 # Number of seconds simulated
< sim_ticks 60130734500 # Number of ticks simulated
< final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.060132 # Number of seconds simulated
> sim_ticks 60131512500 # Number of ticks simulated
> final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 310652 # Simulator instruction rate (inst/s)
< host_op_rate 397278 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 263409545 # Simulator tick rate (ticks/s)
< host_mem_usage 281384 # Number of bytes of host memory used
< host_seconds 228.28 # Real time elapsed on the host
---
> host_inst_rate 320494 # Simulator instruction rate (inst/s)
> host_op_rate 409865 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 271758284 # Simulator tick rate (ticks/s)
> host_mem_usage 281048 # Number of bytes of host memory used
> host_seconds 221.27 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
29,39c29,39
< system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s)
86c86
< system.physmem.totGap 60130703000 # Total gap between requests
---
> system.physmem.totGap 60131481000 # Total gap between requests
199,204c199,204
< system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation
206,208c206,208
< system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation
230,231c230,231
< system.physmem.totQLat 3048956750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3049168000 # Total ticks spent queuing
> system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM
233c233
< system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst
235c235
< system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst
250c250
< system.physmem.avgGap 279590.56 # Average gap between requests
---
> system.physmem.avgGap 279594.18 # Average gap between requests
256,270c256,270
< system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ)
< system.physmem_0.averagePower 386.883743 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states
---
> system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ)
> system.physmem_0.averagePower 386.918165 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states
276,284c276,284
< system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ)
< system.physmem_1.averagePower 383.200220 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states
---
> system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ)
> system.physmem_1.averagePower 383.198268 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states
286,290c286,290
< system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
294c294
< system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups
297,298c297,298
< system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target.
305c305
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
335c335
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
365c365
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
395c395
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
426,427c426,427
< system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 120261469 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 120263025 # number of cpu cycles simulated
434,435c434,435
< system.cpu.cpi 1.695850 # CPI: cycles per instruction
< system.cpu.ipc 0.589675 # IPC: instructions per cycle
---
> system.cpu.cpi 1.695872 # CPI: cycles per instruction
> system.cpu.ipc 0.589667 # IPC: instructions per cycle
475,477c475,477
< system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
479,480c479,480
< system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks.
482c482
< system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks.
484c484
< system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor
492,496c492,496
< system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits
505,508c505,508
< system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits
< system.cpu.dcache.overall_hits::total 42605457 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits
> system.cpu.dcache.overall_hits::total 42605460 # number of overall hits
519,528c519,528
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses)
537,540c537,540
< system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses
551,558c551,558
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency
585,594c585,594
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles
605,615c605,615
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
617c617
< system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1851.999823 # Cycle average of tags in use
622,624c622,624
< system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1851.999823 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.904297 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.904297 # Average percentage of cache occupancy
634c634
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
647,652c647,652
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042263500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 1042263500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 1042263500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 1042263500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 1042263500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 1042263500 # number of overall miss cycles
665,670c665,670
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 22862.672194 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 22862.672194 # average overall miss latency
685,690c685,690
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996676500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 996676500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996676500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 996676500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996676500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 996676500 # number of overall MSHR miss cycles
697,703c697,703
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.694130 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.694130 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
705c705
< system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 31292.341702 # Cycle average of tags in use
709,712c709,712
< system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.warmup_cycle 10980599000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 476.632754 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.083150 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.625798 # Average occupied blocks per requestor
726c726
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
755,766c755,766
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269327500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9269327500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492863000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 492863000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2253034500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 2253034500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 492863000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11522362000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12015225000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 492863000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11522362000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12015225000 # number of overall miss cycles
795,806c795,806
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.207219 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.207219 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109842.433697 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109842.433697 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103426.115498 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103426.115498 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 93439.706660 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 93439.706660 # average overall miss latency
839,850c839,850
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246157500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246157500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446695500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446695500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029647000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029647000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446695500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275804500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10722500000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446695500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275804500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 10722500000 # number of overall MSHR miss cycles
865,876c865,876
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency
883c883
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
923c923
< system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
946c946
< system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks)
948c948
< system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks)