3,5c3,5
< sim_seconds 0.058750 # Number of seconds simulated
< sim_ticks 58750410500 # Number of ticks simulated
< final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.060131 # Number of seconds simulated
> sim_ticks 60130734500 # Number of ticks simulated
> final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 179920 # Simulator instruction rate (inst/s)
< host_op_rate 230092 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 149057017 # Simulator tick rate (ticks/s)
< host_mem_usage 281832 # Number of bytes of host memory used
< host_seconds 394.15 # Real time elapsed on the host
---
> host_inst_rate 142105 # Simulator instruction rate (inst/s)
> host_op_rate 181732 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 120494644 # Simulator tick rate (ticks/s)
> host_mem_usage 279144 # Number of bytes of host memory used
> host_seconds 499.03 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
29,39c29,39
< system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s)
44,46c44,46
< system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
< system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM
---
> system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
> system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM
49c49
< system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
60,61c60,61
< system.physmem.perBankRdBursts::8 8053 # Per bank write bursts
< system.physmem.perBankRdBursts::9 7612 # Per bank write bursts
---
> system.physmem.perBankRdBursts::8 8054 # Per bank write bursts
> system.physmem.perBankRdBursts::9 7613 # Per bank write bursts
68c68
< system.physmem.perBankWrBursts::0 5399 # Per bank write bursts
---
> system.physmem.perBankWrBursts::0 5400 # Per bank write bursts
70,71c70,71
< system.physmem.perBankWrBursts::2 5476 # Per bank write bursts
< system.physmem.perBankWrBursts::3 5348 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 5475 # Per bank write bursts
> system.physmem.perBankWrBursts::3 5349 # Per bank write bursts
73c73
< system.physmem.perBankWrBursts::5 5588 # Per bank write bursts
---
> system.physmem.perBankWrBursts::5 5586 # Per bank write bursts
77c77
< system.physmem.perBankWrBursts::9 5136 # Per bank write bursts
---
> system.physmem.perBankWrBursts::9 5135 # Per bank write bursts
86c86
< system.physmem.totGap 58750379000 # Total gap between requests
---
> system.physmem.totGap 60130703000 # Total gap between requests
101,105c101,105
< system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
148,165c148,165
< system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see
167,168c167,168
< system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
197,215c197,215
< system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes
218,232c218,233
< system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads
< system.physmem.totQLat 1552277750 # Total ticks spent queuing
< system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads
> system.physmem.totQLat 3048956750 # Total ticks spent queuing
> system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst
234,238c235,239
< system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s
240,242c241,243
< system.physmem.busUtil 1.83 # Data bus utilization in percentage
< system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes
---
> system.physmem.busUtil 1.79 # Data bus utilization in percentage
> system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes
244,284c245,295
< system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing
< system.physmem.readRowHits 112029 # Number of row buffer hits during reads
< system.physmem.writeRowHits 70027 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes
< system.physmem.avgGap 273172.45 # Average gap between requests
< system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ)
< system.physmem_0.averagePower 705.717335 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ)
< system.physmem_1.averagePower 704.382975 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 14827613 # Number of BP lookups
< system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits
---
> system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing
> system.physmem.readRowHits 112228 # Number of row buffer hits during reads
> system.physmem.writeRowHits 69923 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes
> system.physmem.avgGap 279590.56 # Average gap between requests
> system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ)
> system.physmem_0.averagePower 386.883743 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states
> system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ)
> system.physmem_1.averagePower 383.200220 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 14827796 # Number of BP lookups
> system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits
286,287c297,298
< system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target.
289,290c300,301
< system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits.
---
> system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits.
294c305
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
324c335
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
354c365
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
384c395
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
415,416c426,427
< system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 117500821 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 120261469 # number of cpu cycles simulated
421c432
< system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit
423,424c434,435
< system.cpu.cpi 1.656921 # CPI: cycles per instruction
< system.cpu.ipc 0.603529 # IPC: instructions per cycle
---
> system.cpu.cpi 1.695850 # CPI: cycles per instruction
> system.cpu.ipc 0.589675 # IPC: instructions per cycle
460,462c471,473
< system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
464,465c475,476
< system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks.
467,471c478,482
< system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy
473,475c484,486
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id
477,485c488,496
< system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits
490,513c501,524
< system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits
< system.cpu.dcache.overall_hits::total 42605646 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses
< system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses
< system.cpu.dcache.overall_misses::total 299891 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits
> system.cpu.dcache.overall_hits::total 42605457 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses
> system.cpu.dcache.overall_misses::total 299788 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses)
516,517c527,528
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses)
522,544c533,555
< system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349931 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.349931 # miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.005964 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.005964 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.006990 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.006990 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked
546c557
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
548c559
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked
552,559c563,570
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17840 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 17840 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100712 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 100712 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 118552 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 118552 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 118552 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 118552 # number of overall MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits
570,579c581,590
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 586674000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 586674000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401236500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401236500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788829000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788829000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8987910500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10776739500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10776739500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles
584,585c595,596
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187428 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187428 # mshr miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187431 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187431 # mshr miss rate for SoftPFReq accesses
590,600c601,611
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
602,603c613,614
< system.cpu.icache.tags.tagsinuse 1854.190293 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 25047618 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks.
605c616
< system.cpu.icache.tags.avg_refs 549.446509 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks.
607,609c618,620
< system.cpu.icache.tags.occ_blocks::cpu.inst 1854.190293 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.905366 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.905366 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy
611,612c622,623
< system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
614,615c625,626
< system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::3 898 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 # Occupied blocks per task id
617,625c628,636
< system.cpu.icache.tags.tag_accesses 50231999 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 50231999 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 25047618 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 25047618 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 25047618 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 25047618 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 25047618 # number of overall hits
< system.cpu.icache.overall_hits::total 25047618 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 25048343 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 25048343 # number of overall hits
> system.cpu.icache.overall_hits::total 25048343 # number of overall hits
632,643c643,654
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 918433000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 918433000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 918433000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 918433000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 918433000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 918433000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 25093206 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 25093206 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 25093206 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 25093206 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 25093206 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 25093206 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 25093931 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 25093931 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 25093931 # number of overall (read+write) accesses
650,655c661,666
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20146.376239 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20146.376239 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20146.376239 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20146.376239 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency
670,675c681,686
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 872846000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 872846000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 872846000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 872846000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 872846000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 872846000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles
682,688c693,699
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19146.398175 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19146.398175 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
690,691c701,702
< system.cpu.l2cache.tags.tagsinuse 31328.460689 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 268173 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks.
693,701c704,712
< system.cpu.l2cache.tags.avg_refs 2.063758 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 10596662000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 480.299456 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1381.968758 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 29466.192474 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.014658 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042174 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.899237 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.956069 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.954966 # Average percentage of cache occupancy
703,706c714,717
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1189 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13615 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17003 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12834 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17840 # Occupied blocks per task id
711c722
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
718,719c729,730
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41100 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 41100 # number of ReadCleanReq hits
---
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41101 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 41101 # number of ReadCleanReq hits
722c733
< system.cpu.l2cache.demand_hits::cpu.inst 41100 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 41101 # number of demand (read+write) hits
724,725c735,736
< system.cpu.l2cache.demand_hits::total 77546 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 41100 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 77547 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 41101 # number of overall hits
727c738
< system.cpu.l2cache.overall_hits::total 77546 # number of overall hits
---
> system.cpu.l2cache.overall_hits::total 77547 # number of overall hits
730,731c741,742
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4488 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 4488 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4487 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 4487 # number of ReadCleanReq misses
734c745
< system.cpu.l2cache.demand_misses::cpu.inst 4488 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 4487 # number of demand (read+write) misses
736,737c747,748
< system.cpu.l2cache.demand_misses::total 128589 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 4488 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 128588 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses
739,751c750,762
< system.cpu.l2cache.overall_misses::total 128589 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8191072500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8191072500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 369038000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 369038000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1957896000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1957896000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 369038000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10148968500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10518006500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 369038000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10148968500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10518006500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::total 128588 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles
770,771c781,782
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098447 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098447 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098425 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098425 # miss rate for ReadCleanReq accesses
774c785
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098447 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098425 # miss rate for demand accesses
776,777c787,788
< system.cpu.l2cache.demand_miss_rate::total 0.623810 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098447 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.623805 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses
779,791c790,802
< system.cpu.l2cache.overall_miss_rate::total 0.623810 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80055.831387 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80055.831387 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82227.718360 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82227.718360 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89877.708410 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89877.708410 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 81795.538499 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 81795.538499 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency
800,801c811,812
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
---
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits
804c815
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
806,807c817,818
< system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
809c820
< system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
824,835c835,846
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7167902500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7167902500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 323146000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 323146000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1736095500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1736095500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 323146000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8903998000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9227144000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 323146000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8903998000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9227144000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles
850,861c861,872
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency
868c879
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
898c909
< system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks)
908c919
< system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
931c942
< system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks)
933,934c944,945
< system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 1.1 # Layer utilization (%)