3,5c3,5
< sim_seconds 0.057816 # Number of seconds simulated
< sim_ticks 57815555000 # Number of ticks simulated
< final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.058730 # Number of seconds simulated
> sim_ticks 58730125500 # Number of ticks simulated
> final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 131971 # Simulator instruction rate (inst/s)
< host_op_rate 168772 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 107593052 # Simulator tick rate (ticks/s)
< host_mem_usage 309228 # Number of bytes of host memory used
< host_seconds 537.35 # Real time elapsed on the host
---
> host_inst_rate 197162 # Simulator instruction rate (inst/s)
> host_op_rate 252141 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 163284235 # Simulator tick rate (ticks/s)
> host_mem_usage 321164 # Number of bytes of host memory used
> host_seconds 359.68 # Real time elapsed on the host
16,20c16,20
< system.physmem.bytes_read::cpu.inst 324480 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 7923328 # Number of bytes read from this memory
< system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory
> system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory
23,25c23,25
< system.physmem.num_reads::cpu.inst 5070 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 123802 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory
28,39c28,39
< system.physmem.bw_read::cpu.inst 5612330 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 137044918 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 5612330 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 137044918 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 128872 # Number of read requests accepted
---
> system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 128871 # Number of read requests accepted
41c41
< system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue
43c43
< system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM
45,46c45,46
< system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side
---
> system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side
52,53c52,53
< system.physmem.perBankRdBursts::1 8375 # Per bank write bursts
< system.physmem.perBankRdBursts::2 8229 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 8376 # Per bank write bursts
> system.physmem.perBankRdBursts::2 8228 # Per bank write bursts
55c55
< system.physmem.perBankRdBursts::4 8320 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 8319 # Per bank write bursts
58c58
< system.physmem.perBankRdBursts::7 7970 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 7969 # Per bank write bursts
61,62c61,62
< system.physmem.perBankRdBursts::10 7820 # Per bank write bursts
< system.physmem.perBankRdBursts::11 7830 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 7818 # Per bank write bursts
> system.physmem.perBankRdBursts::11 7832 # Per bank write bursts
66,67c66,67
< system.physmem.perBankRdBursts::15 8006 # Per bank write bursts
< system.physmem.perBankWrBursts::0 5183 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 8007 # Per bank write bursts
> system.physmem.perBankWrBursts::0 5180 # Per bank write bursts
73,74c73,74
< system.physmem.perBankWrBursts::6 5194 # Per bank write bursts
< system.physmem.perBankWrBursts::7 5048 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 5197 # Per bank write bursts
> system.physmem.perBankWrBursts::7 5050 # Per bank write bursts
76,77c76,77
< system.physmem.perBankWrBursts::9 5086 # Per bank write bursts
< system.physmem.perBankWrBursts::10 5252 # Per bank write bursts
---
> system.physmem.perBankWrBursts::9 5087 # Per bank write bursts
> system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
82c82
< system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 5227 # Per bank write bursts
85c85
< system.physmem.totGap 57815523000 # Total gap between requests
---
> system.physmem.totGap 58730091000 # Total gap between requests
92c92
< system.physmem.readPktSize::6 128872 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 128871 # Read request sizes (log2)
101,102c101,102
< system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
147,153c147,153
< system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see
155,164c155,164
< system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see
196,214c196,213
< system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes
217,235c216,233
< system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads
< system.physmem.totQLat 1505377000 # Total ticks spent queuing
< system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads
> system.physmem.totQLat 1533027250 # Total ticks spent queuing
> system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst
237,241c235,239
< system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s
243,245c241,243
< system.physmem.busUtil 1.84 # Data bus utilization in percentage
< system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes
---
> system.physmem.busUtil 1.81 # Data bus utilization in percentage
> system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes
247,264c245,262
< system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing
< system.physmem.readRowHits 112203 # Number of row buffer hits during reads
< system.physmem.writeRowHits 62134 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes
< system.physmem.avgGap 271660.13 # Average gap between requests
< system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ)
< system.physmem_0.averagePower 707.837327 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states
---
> system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing
> system.physmem.readRowHits 112070 # Number of row buffer hits during reads
> system.physmem.writeRowHits 62147 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes
> system.physmem.avgGap 275958.74 # Average gap between requests
> system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ)
> system.physmem_0.averagePower 708.329716 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states
266c264
< system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states
268,278c266,276
< system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ)
< system.physmem_1.averagePower 706.292941 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states
---
> system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ)
> system.physmem_1.averagePower 706.358131 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states
280c278
< system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states
282,286c280,284
< system.cpu.branchPred.lookups 14822198 # Number of BP lookups
< system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits
---
> system.cpu.branchPred.lookups 14827059 # Number of BP lookups
> system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits
288,289c286,287
< system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target.
409c407
< system.cpu.numCycles 115631110 # number of cpu cycles simulated
---
> system.cpu.numCycles 117460251 # number of cpu cycles simulated
414c412
< system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit
416,428c414,426
< system.cpu.cpi 1.630556 # CPI: cycles per instruction
< system.cpu.ipc 0.613288 # IPC: instructions per cycle
< system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 156428 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4068.581764 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy
---
> system.cpu.cpi 1.656350 # CPI: cycles per instruction
> system.cpu.ipc 0.603737 # IPC: instructions per cycle
> system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 156434 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy
430,432c428,430
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id
434,439c432,437
< system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 22989229 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 19643835 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits
444,465c442,463
< system.cpu.dcache.demand_hits::cpu.data 42633064 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42633064 # number of overall hits
< system.cpu.dcache.overall_hits::total 42633064 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 56065 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 206066 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 262131 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 262131 # number of overall misses
< system.cpu.dcache.overall_misses::total 262131 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 2147242437 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 15196521000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 17343763437 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17343763437 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23045294 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits
> system.cpu.dcache.overall_hits::total 42634623 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses
> system.cpu.dcache.overall_misses::total 262226 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses)
472,475c470,473
< system.cpu.dcache.demand_accesses::cpu.data 42895195 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 42895195 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses
478,491c476,489
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010381 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.006111 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.006111 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency
500,525c498,523
< system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks
< system.cpu.dcache.writebacks::total 128441 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2577 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99030 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 101607 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 101607 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 101607 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 101607 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53488 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 53488 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107036 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 160524 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 160524 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1987609313 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7609976000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9597585313 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9597585313 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles
---
> system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks
> system.cpu.dcache.writebacks::total 128445 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles
534,541c532,539
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency
543,547c541,545
< system.cpu.icache.tags.replacements 42682 # number of replacements
< system.cpu.icache.tags.tagsinuse 1858.929385 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 25083355 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 44724 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 560.847755 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 42774 # number of replacements
> system.cpu.icache.tags.tagsinuse 1856.910000 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 25093452 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 44816 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 559.921724 # Average number of references to valid blocks.
549,551c547,549
< system.cpu.icache.tags.occ_blocks::cpu.inst 1858.929385 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.907680 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.907680 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy
553,556c551,554
< system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 803 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1117 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 730 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id
558,595c556,593
< system.cpu.icache.tags.tag_accesses 50300884 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 50300884 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 25083355 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 25083355 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 25083355 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 25083355 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 25083355 # number of overall hits
< system.cpu.icache.overall_hits::total 25083355 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 44725 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 44725 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 44725 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 44725 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 44725 # number of overall misses
< system.cpu.icache.overall_misses::total 44725 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 895927489 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 895927489 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 895927489 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 895927489 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 895927489 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 895927489 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 25128080 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 25128080 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 25128080 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 25128080 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 25128080 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 25128080 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20031.917026 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20031.917026 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20031.917026 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20031.917026 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 50321354 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 50321354 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 25093452 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 25093452 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 25093452 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 25093452 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 25093452 # number of overall hits
> system.cpu.icache.overall_hits::total 25093452 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 44817 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 44817 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 44817 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 44817 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 44817 # number of overall misses
> system.cpu.icache.overall_misses::total 44817 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 937886990 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 937886990 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 937886990 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 937886990 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 937886990 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 937886990 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 25138269 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 25138269 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 25138269 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 25138269 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 25138269 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 25138269 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001783 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.001783 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.001783 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.001783 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.001783 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.001783 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.036392 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20927.036392 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20927.036392 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20927.036392 # average overall miss latency
604,627c602,625
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44725 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 44725 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 44725 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 44725 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 44725 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 44725 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804564511 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 804564511 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804564511 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 804564511 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804564511 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 804564511 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17989.145020 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17989.145020 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44817 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 44817 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 44817 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 44817 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 44817 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 44817 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 868759010 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 868759010 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 868759010 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 868759010 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 868759010 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 868759010 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001783 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.001783 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19384.586429 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19384.586429 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency
630,633c628,631
< system.cpu.l2cache.tags.tagsinuse 29936.958460 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 99697 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 126852 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.785932 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 29885.598621 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 99802 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 126851 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.786766 # Average number of references to valid blocks.
635,665c633,663
< system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1563.058609 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 1666.382853 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047701 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.913603 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 31119 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1137 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9778 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19493 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949677 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 2903408 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 2903408 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 39644 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 31904 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 71548 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 128441 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 128441 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 4755 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 4755 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 39644 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 76303 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 39644 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits
< system.cpu.l2cache.overall_hits::total 76303 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 5081 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 21584 # number of ReadReq misses
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 26636.535052 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1559.339588 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1689.723980 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.812883 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047587 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.051566 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.912036 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1015 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9129 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20264 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 591 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 2904221 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 2904221 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 39738 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 31910 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 71648 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 128445 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 128445 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 39738 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 36664 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 76402 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 39738 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 36664 # number of overall hits
> system.cpu.l2cache.overall_hits::total 76402 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 5079 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 21586 # number of ReadReq misses
667,720c665,718
< system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 5081 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 123865 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 128946 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 5081 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 123865 # number of overall misses
< system.cpu.l2cache.overall_misses::total 128946 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 363309000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1614754750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1978063750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7455355000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7455355000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 363309000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9070109750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 9433418750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 363309000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9070109750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 9433418750 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 44725 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 53488 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 98213 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 128441 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 128441 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 107036 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 107036 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 44725 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 160524 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 205249 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 44725 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 160524 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 205249 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113605 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403530 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.271502 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955576 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.955576 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113605 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.771629 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.628242 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113605 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.771629 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.628242 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71503.444204 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74812.581079 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74182.027002 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72890.908380 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.908380 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73157.901370 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73157.901370 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 5079 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 123866 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 128945 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 5079 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 123866 # number of overall misses
> system.cpu.l2cache.overall_misses::total 128945 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 406663000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1774587250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2181250250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8245411750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8245411750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 406663000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10019999000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 10426662000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 406663000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10019999000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 10426662000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 44817 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 53496 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 98313 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 128445 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 128445 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 44817 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 160530 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 205347 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 44817 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 160530 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 205347 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113328 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403507 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.271226 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955584 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.955584 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113328 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.771607 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.627937 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113328 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.771607 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.627937 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80067.532979 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82210.101455 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 81801.997000 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80616.071079 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80616.071079 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80067.532979 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80893.861108 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80861.312963 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80067.532979 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80893.861108 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80861.312963 # average overall miss latency
740,741c738,739
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5071 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21521 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5069 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21523 # number of ReadReq MSHR misses
743,783c741,781
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 5071 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 123802 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 128873 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 5071 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 123802 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 128873 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 298810000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1336295500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1635105500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6164329000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6164329000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 298810000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7500624500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 7799434500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 298810000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7500624500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 7799434500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402352 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270758 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955576 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955576 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.627886 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.627886 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58925.261290 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62092.630454 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61488.624398 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60268.564054 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60268.564054 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 5069 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 123803 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 128872 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 5069 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 123803 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 128872 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342505250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1501079000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1843584250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6966637250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6966637250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342505250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8467716250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 8810221500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342505250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8467716250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 8810221500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402329 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270483 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955584 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955584 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.627582 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.627582 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67568.603275 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69743.019096 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69328.529257 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68113.387270 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68113.387270 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency
785,795c783,793
< system.cpu.toL2Bus.trans_dist::ReadReq 98213 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 98212 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 128441 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 107036 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 107036 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89449 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449489 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 538938 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2862336 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18493760 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 21356096 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadReq 98313 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 98312 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89633 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449505 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 539138 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2868224 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494400 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 21362624 # Cumulative packet size per connected master and slave (bytes)
797,798c795,796
< system.cpu.toL2Bus.snoop_fanout::samples 333690 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 333792 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
804,807c802,803
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 333690 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
809,812c805,808
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 333690 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 295286000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 333792 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 295341000 # Layer occupancy (ticks)
814c810
< system.cpu.toL2Bus.respLayer0.occupancy 68043489 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 68175990 # Layer occupancy (ticks)
816c812
< system.cpu.toL2Bus.respLayer1.occupancy 268450687 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 268644937 # Layer occupancy (ticks)
821,826c817,822
< system.membus.trans_dist::ReadExReq 102281 # Transaction distribution
< system.membus.trans_dist::ReadExResp 102281 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341695 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 341695 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620672 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 13620672 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
> system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341693 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 341693 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620608 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 13620608 # Cumulative packet size per connected master and slave (bytes)
828c824
< system.membus.snoop_fanout::samples 212823 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 212822 # Request fanout histogram
832c828
< system.membus.snoop_fanout::0 212823 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 212822 100.00% 100.00% # Request fanout histogram
837,841c833,837
< system.membus.snoop_fanout::total 212823 # Request fanout histogram
< system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
< system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 2.1 # Layer utilization (%)
---
> system.membus.snoop_fanout::total 212822 # Request fanout histogram
> system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
> system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 1.2 # Layer utilization (%)