3,5c3,5
< sim_seconds 0.056374 # Number of seconds simulated
< sim_ticks 56374399500 # Number of ticks simulated
< final_tick 56374399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.057847 # Number of seconds simulated
> sim_ticks 57847312000 # Number of ticks simulated
> final_tick 57847312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 200830 # Simulator instruction rate (inst/s)
< host_op_rate 256832 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 159651052 # Simulator tick rate (ticks/s)
< host_mem_usage 319716 # Number of bytes of host memory used
< host_seconds 353.11 # Real time elapsed on the host
---
> host_inst_rate 186854 # Simulator instruction rate (inst/s)
> host_op_rate 238959 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 152421830 # Simulator tick rate (ticks/s)
> host_mem_usage 261476 # Number of bytes of host memory used
> host_seconds 379.52 # Real time elapsed on the host
16,19c16,19
< system.physmem.bytes_read::cpu.inst 8247168 # Number of bytes read from this memory
< system.physmem.bytes_read::total 8247168 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 323904 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 323904 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 8247680 # Number of bytes read from this memory
> system.physmem.bytes_read::total 8247680 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory
22,23c22,23
< system.physmem.num_reads::cpu.inst 128862 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 128870 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 128870 # Number of read requests responded to by this memory
26,35c26,35
< system.physmem.bw_read::cpu.inst 146292787 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 146292787 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 5745587 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 5745587 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 95306807 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 95306807 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 95306807 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 146292787 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 241599593 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 128862 # Number of read requests accepted
---
> system.physmem.bw_read::cpu.inst 142576720 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 142576720 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 5607037 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 5607037 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 92880098 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 92880098 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 92880098 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 142576720 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 235456818 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 128870 # Number of read requests accepted
37c37
< system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 128870 # Number of DRAM read bursts, including those serviced by the write queue
39,42c39,42
< system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
< system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side
---
> system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
> system.physmem.bytesWritten 5370944 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 8247680 # Total read bytes from the system interface side
44c44
< system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
47,52c47,52
< system.physmem.perBankRdBursts::0 8164 # Per bank write bursts
< system.physmem.perBankRdBursts::1 8373 # Per bank write bursts
< system.physmem.perBankRdBursts::2 8238 # Per bank write bursts
< system.physmem.perBankRdBursts::3 8169 # Per bank write bursts
< system.physmem.perBankRdBursts::4 8316 # Per bank write bursts
< system.physmem.perBankRdBursts::5 8449 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 8158 # Per bank write bursts
> system.physmem.perBankRdBursts::1 8375 # Per bank write bursts
> system.physmem.perBankRdBursts::2 8229 # Per bank write bursts
> system.physmem.perBankRdBursts::3 8171 # Per bank write bursts
> system.physmem.perBankRdBursts::4 8319 # Per bank write bursts
> system.physmem.perBankRdBursts::5 8450 # Per bank write bursts
54c54
< system.physmem.perBankRdBursts::7 7969 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 7970 # Per bank write bursts
56,57c56,57
< system.physmem.perBankRdBursts::9 7635 # Per bank write bursts
< system.physmem.perBankRdBursts::10 7816 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 7641 # Per bank write bursts
> system.physmem.perBankRdBursts::10 7819 # Per bank write bursts
60,63c60,63
< system.physmem.perBankRdBursts::13 7876 # Per bank write bursts
< system.physmem.perBankRdBursts::14 7976 # Per bank write bursts
< system.physmem.perBankRdBursts::15 8004 # Per bank write bursts
< system.physmem.perBankWrBursts::0 5186 # Per bank write bursts
---
> system.physmem.perBankRdBursts::13 7879 # Per bank write bursts
> system.physmem.perBankRdBursts::14 7977 # Per bank write bursts
> system.physmem.perBankRdBursts::15 8006 # Per bank write bursts
> system.physmem.perBankWrBursts::0 5181 # Per bank write bursts
67c67
< system.physmem.perBankWrBursts::4 5265 # Per bank write bursts
---
> system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
69,70c69,70
< system.physmem.perBankWrBursts::6 5196 # Per bank write bursts
< system.physmem.perBankWrBursts::7 5049 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
> system.physmem.perBankWrBursts::7 5047 # Per bank write bursts
72,73c72,73
< system.physmem.perBankWrBursts::9 5086 # Per bank write bursts
< system.physmem.perBankWrBursts::10 5252 # Per bank write bursts
---
> system.physmem.perBankWrBursts::9 5087 # Per bank write bursts
> system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
78c78
< system.physmem.perBankWrBursts::15 5224 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
81c81
< system.physmem.totGap 56374368000 # Total gap between requests
---
> system.physmem.totGap 57847280000 # Total gap between requests
88c88
< system.physmem.readPktSize::6 128862 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 128870 # Read request sizes (log2)
96,97c96,97
< system.physmem.rdQLenPdf::0 126558 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2276 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see
143,149c143,149
< system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 651 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4263 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5162 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 620 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 634 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5165 # What write queue length does an incoming req see
151,163c151,163
< system.physmem.wrQLenPdf::23 5165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5162 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5289 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5740 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5259 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 5168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5180 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5287 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5206 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5744 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5252 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5160 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
192,209c192,209
< system.physmem.bytesPerActivate::samples 38259 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 355.901827 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 215.943020 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 337.187447 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 12097 31.62% 31.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 8058 21.06% 52.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4075 10.65% 63.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2806 7.33% 70.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2532 6.62% 77.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1601 4.18% 81.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1324 3.46% 84.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1160 3.03% 87.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 4606 12.04% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 38259 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5153 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 24.995537 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 361.849882 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 5150 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 38379 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 354.780687 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 215.561409 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 335.824723 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 12139 31.63% 31.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 8088 21.07% 52.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4086 10.65% 63.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2872 7.48% 70.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2530 6.59% 77.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1664 4.34% 81.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1273 3.32% 85.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1227 3.20% 88.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 4500 11.73% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 38379 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 24.981187 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 361.178240 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes
211c211
< system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
213,230c213,231
< system.physmem.rdPerTurnAround::total 5153 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5153 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.286435 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.268739 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.792681 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 4505 87.42% 87.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 6 0.12% 87.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 503 9.76% 97.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 112 2.17% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 16 0.31% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 4 0.08% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 5 0.10% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5153 # Writes before turning the bus around for reads
< system.physmem.totQLat 1533288750 # Total ticks spent queuing
< system.physmem.totMemAccLat 3949338750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 11899.24 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.276377 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.259366 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.777117 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 4528 87.82% 87.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 7 0.14% 87.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 480 9.31% 97.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 121 2.35% 99.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 14 0.27% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads
> system.physmem.totQLat 1539171500 # Total ticks spent queuing
> system.physmem.totMemAccLat 3955390250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 11944.06 # Average queueing delay per DRAM burst
232,236c233,237
< system.physmem.avgMemAccLat 30649.24 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 146.29 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 95.28 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 146.29 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 95.31 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 30694.06 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 142.57 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 92.85 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 142.58 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 92.88 # Average system write bandwidth in MiByte/s
238,240c239,241
< system.physmem.busUtil 1.89 # Data bus utilization in percentage
< system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes
---
> system.physmem.busUtil 1.84 # Data bus utilization in percentage
> system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes
242,250c243,251
< system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing
< system.physmem.readRowHits 112227 # Number of row buffer hits during reads
< system.physmem.writeRowHits 62289 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.20 # Row buffer hit rate for writes
< system.physmem.avgGap 264900.96 # Average gap between requests
< system.physmem.pageHitRate 82.01 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 30998356250 # Time in different power states
< system.physmem.memoryStateTime::REF 1882400000 # Time in different power states
---
> system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing
> system.physmem.readRowHits 112176 # Number of row buffer hits during reads
> system.physmem.writeRowHits 62224 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes
> system.physmem.avgGap 271811.90 # Average gap between requests
> system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 32236826000 # Time in different power states
> system.physmem.memoryStateTime::REF 1931540000 # Time in different power states
252c253
< system.physmem.memoryStateTime::ACT 23491967500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 23675959000 # Time in different power states
254,301c255,277
< system.physmem.actEnergy::0 150716160 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 138521880 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 82236000 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 75582375 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 512857800 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 492039600 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 272347920 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 271479600 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 3681974400 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 3681974400 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 11715197175 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 11107328085 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 23547137250 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 24080355750 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 39962466705 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 39847281690 # Total energy per rank (pJ)
< system.physmem.averagePower::0 708.897385 # Core power per rank (mW)
< system.physmem.averagePower::1 706.854109 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 26583 # Transaction distribution
< system.membus.trans_dist::ReadResp 26583 # Transaction distribution
< system.membus.trans_dist::Writeback 83951 # Transaction distribution
< system.membus.trans_dist::ReadExReq 102279 # Transaction distribution
< system.membus.trans_dist::ReadExResp 102279 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 212813 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 212813 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 212813 # Request fanout histogram
< system.membus.reqLayer0.occupancy 942245500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
< system.membus.respLayer1.occupancy 1221409750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 2.2 # Layer utilization (%)
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.branchPred.lookups 14808790 # Number of BP lookups
< system.cpu.branchPred.condPredicted 9910130 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 393084 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9534894 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 6736290 # Number of BTB hits
---
> system.physmem.actEnergy::0 151237800 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 138899880 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 82520625 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 75788625 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 512678400 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 492078600 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 272322000 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 271486080 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 3778092240 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 3778092240 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 11712850200 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 11277598770 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 24432156750 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 24813956250 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 40941858015 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 40847900445 # Total energy per rank (pJ)
> system.physmem.averagePower::0 707.794027 # Core power per rank (mW)
> system.physmem.averagePower::1 706.169709 # Core power per rank (mW)
> system.cpu.branchPred.lookups 14825675 # Number of BP lookups
> system.cpu.branchPred.condPredicted 9917897 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 395023 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9456669 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 6745546 # Number of BTB hits
303,304c279,280
< system.cpu.branchPred.BTBHitPct 70.648819 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 71.331100 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1719567 # Number of times the RAS was used to get a target.
305a282
> system.cpu_clk_domain.clock 500 # Clock period in ticks
391c368
< system.cpu.numCycles 112748799 # number of cpu cycles simulated
---
> system.cpu.numCycles 115694624 # number of cpu cycles simulated
396c373
< system.cpu.discardedOps 1227279 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1146301 # Number of ops (including micro ops) which were discarded before commit
398,650c375,387
< system.cpu.cpi 1.589912 # CPI: cycles per instruction
< system.cpu.ipc 0.628966 # IPC: instructions per cycle
< system.cpu.tickCycles 93715149 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 19033650 # Total number of cycles that the object has spent stopped
< system.cpu.icache.tags.replacements 42434 # number of replacements
< system.cpu.icache.tags.tagsinuse 1857.503994 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 24948244 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 560.937225 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 1857.503994 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.906984 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.906984 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 50029918 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 50029918 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 24948244 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 24948244 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 24948244 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 24948244 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 24948244 # number of overall hits
< system.cpu.icache.overall_hits::total 24948244 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses
< system.cpu.icache.overall_misses::total 44477 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 894634739 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 894634739 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 894634739 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 894634739 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 894634739 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 894634739 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 24992721 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 24992721 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 24992721 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 24992721 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 24992721 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 24992721 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20114.547721 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20114.547721 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20114.547721 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20114.547721 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44477 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 44477 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 44477 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 803759261 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 803759261 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 803759261 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 803759261 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 803759261 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 803759261 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18071.346111 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18071.346111 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 107038 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 107038 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 88953 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 538416 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 0 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 333420 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 333420 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 333420 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 295133000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 67675739 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 268453439 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
< system.cpu.l2cache.tags.replacements 95725 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 29925.727358 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 99436 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 126843 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.783930 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 26686.334760 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3239.392599 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.814402 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098858 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.913261 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9850 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19418 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 2901241 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 2901241 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 71304 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 71304 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 128423 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 128423 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.inst 4759 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 4759 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 76063 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 76063 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 76063 # number of overall hits
< system.cpu.l2cache.overall_hits::total 76063 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 26655 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 26655 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 102279 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 102279 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 128934 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 128934 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 128934 # number of overall misses
< system.cpu.l2cache.overall_misses::total 128934 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1985312250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1985312250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7483113000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7483113000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 9468425250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 9468425250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 9468425250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 9468425250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 97959 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 97959 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 128423 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 128423 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107038 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 107038 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 204997 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 204997 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 204997 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 204997 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.272104 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.272104 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955539 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.955539 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628956 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.628956 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628956 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.628956 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74481.795160 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74481.795160 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73163.728625 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73163.728625 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73436.217367 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73436.217367 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
< system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks
< system.cpu.l2cache.writebacks::total 83951 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26584 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 26584 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102279 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 102279 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 128863 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 128863 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 128863 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 128863 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1642872250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1642872250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6184053500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6184053500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7826925750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 7826925750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7826925750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 7826925750 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.271379 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.271379 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955539 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955539 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.628609 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.628609 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61799.287165 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61799.287165 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60462.592517 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60462.592517 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.dcache.tags.replacements 156424 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4068.200974 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42664255 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 160520 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 265.787783 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 770315250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.200974 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.993213 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.993213 # Average percentage of cache occupancy
---
> system.cpu.cpi 1.631452 # CPI: cycles per instruction
> system.cpu.ipc 0.612951 # IPC: instructions per cycle
> system.cpu.tickCycles 96938261 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 18756363 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 156422 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4068.596798 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42665450 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 160518 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 265.798540 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.596798 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.993310 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.993310 # Average percentage of cache occupancy
652,653c389,390
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 750 # Occupied blocks per task id
656,661c393,398
< system.cpu.dcache.tags.tag_accesses 86013136 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 86013136 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 22988554 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 22988554 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 19643863 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 19643863 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 86015580 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 86015580 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 22989734 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 22989734 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 19643878 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 19643878 # number of WriteReq hits
666,687c403,424
< system.cpu.dcache.demand_hits::cpu.inst 42632417 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 42632417 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 42632417 # number of overall hits
< system.cpu.dcache.overall_hits::total 42632417 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 56015 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 56015 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.inst 206038 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 206038 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.inst 262053 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 262053 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 262053 # number of overall misses
< system.cpu.dcache.overall_misses::total 262053 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2150622439 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2150622439 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15250404250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 15250404250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 17401026689 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17401026689 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 17401026689 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17401026689 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 23044569 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23044569 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.inst 42633612 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 42633612 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 42633612 # number of overall hits
> system.cpu.dcache.overall_hits::total 42633612 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 56058 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 56058 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.inst 206023 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 206023 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.inst 262081 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 262081 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 262081 # number of overall misses
> system.cpu.dcache.overall_misses::total 262081 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2156088187 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2156088187 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15241867750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 15241867750 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 17397955937 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17397955937 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 17397955937 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17397955937 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 23045792 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23045792 # number of ReadReq accesses(hits+misses)
694,713c431,450
< system.cpu.dcache.demand_accesses::cpu.inst 42894470 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42894470 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 42894470 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42894470 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002431 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.002431 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010380 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.010380 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.006109 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.006109 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.006109 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.006109 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38393.688101 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 38393.688101 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 74017.434891 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74017.434891 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66402.699794 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66402.699794 # average overall miss latency
---
> system.cpu.dcache.demand_accesses::cpu.inst 42895693 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42895693 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 42895693 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42895693 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002432 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.002432 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010379 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.010379 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38461.739395 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 38461.739395 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73981.389214 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 73981.389214 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 66383.888710 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 66383.888710 # average overall miss latency
722,747c459,484
< system.cpu.dcache.writebacks::writebacks 128423 # number of writebacks
< system.cpu.dcache.writebacks::total 128423 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2533 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2533 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99000 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 99000 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 101533 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 101533 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 101533 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 101533 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53482 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 53482 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107038 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 107038 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.inst 160520 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 160520 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 160520 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 160520 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1992994061 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1992994061 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7637775000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7637775000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9630769061 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9630769061 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9630769061 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9630769061 # number of overall MSHR miss cycles
---
> system.cpu.dcache.writebacks::writebacks 128433 # number of writebacks
> system.cpu.dcache.writebacks::total 128433 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2574 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2574 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 98989 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 98989 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 101563 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 101563 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 101563 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 101563 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53484 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 53484 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107034 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.inst 160518 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 160518 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 160518 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 160518 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1995361313 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 1995361313 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7633992250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7633992250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9629353563 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9629353563 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9629353563 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9629353563 # number of overall MSHR miss cycles
756,763c493,500
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37264.763117 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37264.763117 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71355.733478 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71355.733478 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37307.630562 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37307.630562 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71323.058561 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71323.058561 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency
764a502,765
> system.cpu.icache.tags.replacements 42703 # number of replacements
> system.cpu.icache.tags.tagsinuse 1858.978148 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 25082437 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 44745 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 560.564018 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 1858.978148 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.907704 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.907704 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 804 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1118 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 50299111 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 50299111 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 25082437 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 25082437 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 25082437 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 25082437 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 25082437 # number of overall hits
> system.cpu.icache.overall_hits::total 25082437 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 44746 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 44746 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 44746 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 44746 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 44746 # number of overall misses
> system.cpu.icache.overall_misses::total 44746 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 897678738 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 897678738 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 897678738 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 897678738 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 897678738 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 897678738 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 25127183 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 25127183 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 25127183 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 25127183 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 25127183 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 25127183 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001781 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.001781 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.001781 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.001781 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.001781 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.001781 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20061.653287 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20061.653287 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20061.653287 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20061.653287 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.icache.fast_writes 0 # number of fast writes performed
> system.cpu.icache.cache_copies 0 # number of cache copies performed
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44746 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 44746 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 44746 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 44746 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 44746 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 44746 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 806263262 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 806263262 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 806263262 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 806263262 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 806263262 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 806263262 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001781 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.001781 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18018.666741 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18018.666741 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency
> system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.l2cache.tags.replacements 95732 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 29937.969910 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 99708 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 126850 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.786031 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 26706.762922 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3231.206988 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.815026 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098609 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.913634 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1136 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9726 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19542 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 2903460 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 2903460 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 71567 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 71567 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 128433 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 128433 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.inst 4753 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 4753 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 76320 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 76320 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 76320 # number of overall hits
> system.cpu.l2cache.overall_hits::total 76320 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 26663 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 26663 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 102281 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 128944 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 128944 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 128944 # number of overall misses
> system.cpu.l2cache.overall_misses::total 128944 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1987300500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1987300500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7479393750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7479393750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 9466694250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 9466694250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 9466694250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 9466694250 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 98230 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 98230 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 128433 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 128433 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107034 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 205264 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 205264 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 205264 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 205264 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271434 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.271434 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955594 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.955594 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628186 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.628186 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628186 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.628186 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74534.017177 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 74534.017177 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73125.934924 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73125.934924 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73417.097732 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73417.097732 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks
> system.cpu.l2cache.writebacks::total 83951 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26590 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 26590 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102281 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 128871 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 128871 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 128871 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 128871 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1644904750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1644904750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6188348750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6188348750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7833253500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 7833253500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7833253500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 7833253500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270691 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270691 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955594 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955594 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.627831 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.627831 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61861.780745 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61861.780745 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60503.404836 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60503.404836 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency
> system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.toL2Bus.trans_dist::ReadReq 98230 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 98229 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 128433 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89491 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449469 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 538960 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2863680 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492864 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 21356544 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 333697 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 333697 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 333697 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 295281500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 68080238 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 268447937 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
> system.membus.trans_dist::ReadReq 26589 # Transaction distribution
> system.membus.trans_dist::ReadResp 26589 # Transaction distribution
> system.membus.trans_dist::Writeback 83951 # Transaction distribution
> system.membus.trans_dist::ReadExReq 102281 # Transaction distribution
> system.membus.trans_dist::ReadExResp 102281 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341691 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 341691 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620544 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 13620544 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 212821 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 212821 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 212821 # Request fanout histogram
> system.membus.reqLayer0.occupancy 929388500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
> system.membus.respLayer1.occupancy 1213397000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 2.1 # Layer utilization (%)