3,5c3,5
< sim_seconds 0.056337 # Number of seconds simulated
< sim_ticks 56337328500 # Number of ticks simulated
< final_tick 56337328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.056374 # Number of seconds simulated
> sim_ticks 56374399500 # Number of ticks simulated
> final_tick 56374399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 184341 # Simulator instruction rate (inst/s)
< host_op_rate 235745 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 146446418 # Simulator tick rate (ticks/s)
< host_mem_usage 326872 # Number of bytes of host memory used
< host_seconds 384.70 # Real time elapsed on the host
---
> host_inst_rate 197105 # Simulator instruction rate (inst/s)
> host_op_rate 252068 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 156689619 # Simulator tick rate (ticks/s)
> host_mem_usage 315764 # Number of bytes of host memory used
> host_seconds 359.78 # Real time elapsed on the host
26,34c26,34
< system.physmem.bw_read::cpu.inst 146389050 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 146389050 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 5749367 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 5749367 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 95369520 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 95369520 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 95369520 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 146389050 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 241758570 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 146292787 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 146292787 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 5745587 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 5745587 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 95306807 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 95306807 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 95306807 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 146292787 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 241599593 # Total bandwidth to/from this memory (bytes/s)
41c41
< system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM
---
> system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
63c63
< system.physmem.perBankWrBursts::0 5182 # Per bank write bursts
---
> system.physmem.perBankWrBursts::0 5186 # Per bank write bursts
69c69
< system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 5196 # Per bank write bursts
81c81
< system.physmem.totGap 56337297000 # Total gap between requests
---
> system.physmem.totGap 56374368000 # Total gap between requests
96,97c96,97
< system.physmem.rdQLenPdf::0 126556 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2278 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 126558 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2276 # What read queue length does an incoming req see
143,148c143,148
< system.physmem.wrQLenPdf::15 610 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 624 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4267 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 651 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4263 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see
150,162c150,162
< system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5182 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5351 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5232 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5687 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5289 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5242 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5740 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5259 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
192,209c192,209
< system.physmem.bytesPerActivate::samples 38348 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 355.034109 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 215.640084 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 336.462166 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 12103 31.56% 31.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 8116 21.16% 52.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4102 10.70% 63.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2869 7.48% 70.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2471 6.44% 77.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1658 4.32% 81.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1256 3.28% 84.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1197 3.12% 88.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 4576 11.93% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 38348 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 24.976149 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 361.694607 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 38259 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 355.901827 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 215.943020 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 337.187447 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 12097 31.62% 31.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 8058 21.06% 52.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4075 10.65% 63.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2806 7.33% 70.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2532 6.62% 77.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1601 4.18% 81.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1324 3.46% 84.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1160 3.03% 87.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 4606 12.04% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 38259 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5153 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 24.995537 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 361.849882 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 5150 99.94% 99.94% # Reads before turning the bus around for writes
213,228c213,228
< system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.273415 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.256579 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.772702 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 4535 87.94% 87.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 9 0.17% 88.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 476 9.23% 97.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 113 2.19% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 16 0.31% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 5 0.10% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads
< system.physmem.totQLat 1494390000 # Total ticks spent queuing
< system.physmem.totMemAccLat 3910440000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.rdPerTurnAround::total 5153 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5153 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.286435 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.268739 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.792681 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 4505 87.42% 87.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 6 0.12% 87.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 503 9.76% 97.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 112 2.17% 99.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 16 0.31% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 4 0.08% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 5 0.10% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5153 # Writes before turning the bus around for reads
> system.physmem.totQLat 1533288750 # Total ticks spent queuing
> system.physmem.totMemAccLat 3949338750 # Total ticks spent from burst creation until serviced by the DRAM
230c230
< system.physmem.avgQLat 11597.36 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 11899.24 # Average queueing delay per DRAM burst
232,236c232,236
< system.physmem.avgMemAccLat 30347.36 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 146.38 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 95.34 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 146.39 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 95.37 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 30649.24 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 146.29 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 95.28 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 146.29 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 95.31 # Average system write bandwidth in MiByte/s
242,250c242,250
< system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing
< system.physmem.readRowHits 112251 # Number of row buffer hits during reads
< system.physmem.writeRowHits 62167 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 87.11 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.05 # Row buffer hit rate for writes
< system.physmem.avgGap 264726.76 # Average gap between requests
< system.physmem.pageHitRate 81.96 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 31175393250 # Time in different power states
< system.physmem.memoryStateTime::REF 1881100000 # Time in different power states
---
> system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing
> system.physmem.readRowHits 112227 # Number of row buffer hits during reads
> system.physmem.writeRowHits 62289 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.20 # Row buffer hit rate for writes
> system.physmem.avgGap 264900.96 # Average gap between requests
> system.physmem.pageHitRate 82.01 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 30998356250 # Time in different power states
> system.physmem.memoryStateTime::REF 1882400000 # Time in different power states
252c252
< system.physmem.memoryStateTime::ACT 23277299250 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 23491967500 # Time in different power states
254d253
< system.membus.throughput 241758570 # Throughput (bytes/s)
262,266c261,274
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 13620032 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 942262500 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 212813 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 212813 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 212813 # Request fanout histogram
> system.membus.reqLayer0.occupancy 942245500 # Layer occupancy (ticks)
268c276
< system.membus.respLayer1.occupancy 1221459500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1221409750 # Layer occupancy (ticks)
271,275c279,283
< system.cpu.branchPred.lookups 14808792 # Number of BP lookups
< system.cpu.branchPred.condPredicted 9910132 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 393085 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9534896 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 6736289 # Number of BTB hits
---
> system.cpu.branchPred.lookups 14808790 # Number of BP lookups
> system.cpu.branchPred.condPredicted 9910130 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 393084 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9534894 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 6736290 # Number of BTB hits
277c285
< system.cpu.branchPred.BTBHitPct 70.648794 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 70.648819 # BTB Hit Percentage
365c373
< system.cpu.numCycles 112674657 # number of cpu cycles simulated
---
> system.cpu.numCycles 112748799 # number of cpu cycles simulated
370c378
< system.cpu.discardedOps 1227274 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1227279 # Number of ops (including micro ops) which were discarded before commit
372,375c380,383
< system.cpu.cpi 1.588866 # CPI: cycles per instruction
< system.cpu.ipc 0.629380 # IPC: instructions per cycle
< system.cpu.tickCycles 93712970 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 18961687 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.589912 # CPI: cycles per instruction
> system.cpu.ipc 0.628966 # IPC: instructions per cycle
> system.cpu.tickCycles 93715149 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 19033650 # Total number of cycles that the object has spent stopped
377,378c385,386
< system.cpu.icache.tags.tagsinuse 1857.452171 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 24948252 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1857.503994 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 24948244 # Total number of references to valid blocks.
380c388
< system.cpu.icache.tags.avg_refs 560.937404 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 560.937225 # Average number of references to valid blocks.
382,384c390,392
< system.cpu.icache.tags.occ_blocks::cpu.inst 1857.452171 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.906959 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.906959 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1857.503994 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.906984 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.906984 # Average percentage of cache occupancy
386,387c394,395
< system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
391,398c399,406
< system.cpu.icache.tags.tag_accesses 50029934 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 50029934 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 24948252 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 24948252 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 24948252 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 24948252 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 24948252 # number of overall hits
< system.cpu.icache.overall_hits::total 24948252 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 50029918 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 50029918 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 24948244 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 24948244 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 24948244 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 24948244 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 24948244 # number of overall hits
> system.cpu.icache.overall_hits::total 24948244 # number of overall hits
405,416c413,424
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 894991489 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 894991489 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 894991489 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 894991489 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 894991489 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 894991489 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 24992729 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 24992729 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 24992729 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 24992729 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 24992729 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 24992729 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 894634739 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 894634739 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 894634739 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 894634739 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 894634739 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 894634739 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 24992721 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 24992721 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 24992721 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 24992721 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 24992721 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 24992721 # number of overall (read+write) accesses
423,428c431,436
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20122.568721 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20122.568721 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20114.547721 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20114.547721 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20114.547721 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20114.547721 # average overall miss latency
443,448c451,456
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804116511 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 804116511 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804116511 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 804116511 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804116511 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 804116511 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 803759261 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 803759261 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 803759261 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 803759261 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 803759261 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 803759261 # number of overall MSHR miss cycles
455,460c463,468
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18071.346111 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18071.346111 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
462d469
< system.cpu.toL2Bus.throughput 378768688 # Throughput (bytes/s)
471,475c478,496
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 21338816 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 333420 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 333420 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 333420 # Request fanout histogram
478c499
< system.cpu.toL2Bus.respLayer0.occupancy 67675489 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 67675739 # Layer occupancy (ticks)
480c501
< system.cpu.toL2Bus.respLayer1.occupancy 268454939 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 268453439 # Layer occupancy (ticks)
483c504
< system.cpu.l2cache.tags.tagsinuse 29924.855625 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 29925.727358 # Cycle average of tags in use
488,492c509,513
< system.cpu.l2cache.tags.occ_blocks::writebacks 26686.795429 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.060196 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.814416 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098818 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.913234 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 26686.334760 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3239.392599 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.814402 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098858 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.913261 # Average percentage of cache occupancy
494,497c515,518
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1148 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9890 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19364 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9850 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19418 # Occupied blocks per task id
520,527c541,548
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978942750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1978942750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7452442750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7452442750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 9431385500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 9431385500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 9431385500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 9431385500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1985312250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1985312250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7483113000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7483113000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 9468425250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 9468425250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 9468425250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 9468425250 # number of overall miss cycles
546,553c567,574
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74242.834365 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74242.834365 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72863.860128 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72863.860128 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73148.940543 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73148.940543 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74481.795160 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 74481.795160 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73163.728625 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73163.728625 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73436.217367 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73436.217367 # average overall miss latency
578,585c599,606
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1636163750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1636163750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6153335250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6153335250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7789499000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 7789499000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7789499000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 7789499000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1642872250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1642872250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6184053500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6184053500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7826925750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 7826925750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7826925750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 7826925750 # number of overall MSHR miss cycles
594,601c615,622
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61546.936127 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61546.936127 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60162.254715 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60162.254715 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61799.287165 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61799.287165 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60462.592517 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60462.592517 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
604,605c625,626
< system.cpu.dcache.tags.tagsinuse 4068.182682 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42664218 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4068.200974 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42664255 # Total number of references to valid blocks.
607c628
< system.cpu.dcache.tags.avg_refs 265.787553 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 265.787783 # Average number of references to valid blocks.
609,611c630,632
< system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.182682 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.993209 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.993209 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.200974 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.993213 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.993213 # Average percentage of cache occupancy
613,615c634,636
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id
617,622c638,643
< system.cpu.dcache.tags.tag_accesses 86013120 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 86013120 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 22988546 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 22988546 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 19643834 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 19643834 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 86013136 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 86013136 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 22988554 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 22988554 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 19643863 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 19643863 # number of WriteReq hits
627,630c648,651
< system.cpu.dcache.demand_hits::cpu.inst 42632380 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 42632380 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 42632380 # number of overall hits
< system.cpu.dcache.overall_hits::total 42632380 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.inst 42632417 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 42632417 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 42632417 # number of overall hits
> system.cpu.dcache.overall_hits::total 42632417 # number of overall hits
633,648c654,669
< system.cpu.dcache.WriteReq_misses::cpu.inst 206067 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 206067 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.inst 262082 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 262082 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 262082 # number of overall misses
< system.cpu.dcache.overall_misses::total 262082 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2143200689 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2143200689 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15189809250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 15189809250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 17333009939 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17333009939 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 17333009939 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17333009939 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 23044561 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23044561 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.WriteReq_misses::cpu.inst 206038 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 206038 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.inst 262053 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 262053 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 262053 # number of overall misses
> system.cpu.dcache.overall_misses::total 262053 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2150622439 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2150622439 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15250404250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 15250404250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 17401026689 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17401026689 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 17401026689 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17401026689 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 23044569 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23044569 # number of ReadReq accesses(hits+misses)
655,658c676,679
< system.cpu.dcache.demand_accesses::cpu.inst 42894462 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42894462 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 42894462 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42894462 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.inst 42894470 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42894470 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 42894470 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42894470 # number of overall (read+write) accesses
661,674c682,695
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66135.827485 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66135.827485 # average overall miss latency
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010380 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.010380 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.006109 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.006109 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.006109 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.006109 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38393.688101 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 38393.688101 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 74017.434891 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74017.434891 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 66402.699794 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 66402.699794 # average overall miss latency
687,692c708,713
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99029 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 99029 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 101562 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 101562 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 101562 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 101562 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99000 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 99000 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 101533 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 101533 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 101533 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 101533 # number of overall MSHR hits
701,708c722,729
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1986266811 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1986266811 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7607104750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7607104750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593371561 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9593371561 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593371561 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9593371561 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1992994061 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 1992994061 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7637775000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7637775000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9630769061 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9630769061 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9630769061 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9630769061 # number of overall MSHR miss cycles
717,724c738,745
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37264.763117 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37264.763117 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71355.733478 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71355.733478 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
< sim_seconds 0.056337 # Number of seconds simulated
< sim_ticks 56337328500 # Number of ticks simulated
< final_tick 56337328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.056374 # Number of seconds simulated
> sim_ticks 56374399500 # Number of ticks simulated
> final_tick 56374399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 184341 # Simulator instruction rate (inst/s)
< host_op_rate 235745 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 146446418 # Simulator tick rate (ticks/s)
< host_mem_usage 326872 # Number of bytes of host memory used
< host_seconds 384.70 # Real time elapsed on the host
---
> host_inst_rate 197105 # Simulator instruction rate (inst/s)
> host_op_rate 252068 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 156689619 # Simulator tick rate (ticks/s)
> host_mem_usage 315764 # Number of bytes of host memory used
> host_seconds 359.78 # Real time elapsed on the host
26,34c26,34
< system.physmem.bw_read::cpu.inst 146389050 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 146389050 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 5749367 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 5749367 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 95369520 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 95369520 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 95369520 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 146389050 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 241758570 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 146292787 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 146292787 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 5745587 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 5745587 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 95306807 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 95306807 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 95306807 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 146292787 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 241599593 # Total bandwidth to/from this memory (bytes/s)
41c41
< system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM
---
> system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
63c63
< system.physmem.perBankWrBursts::0 5182 # Per bank write bursts
---
> system.physmem.perBankWrBursts::0 5186 # Per bank write bursts
69c69
< system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 5196 # Per bank write bursts
81c81
< system.physmem.totGap 56337297000 # Total gap between requests
---
> system.physmem.totGap 56374368000 # Total gap between requests
96,97c96,97
< system.physmem.rdQLenPdf::0 126556 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2278 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 126558 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2276 # What read queue length does an incoming req see
143,148c143,148
< system.physmem.wrQLenPdf::15 610 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 624 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4267 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 651 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4263 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see
150,162c150,162
< system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5182 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5351 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5232 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5687 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5289 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5242 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5740 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5259 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
192,209c192,209
< system.physmem.bytesPerActivate::samples 38348 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 355.034109 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 215.640084 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 336.462166 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 12103 31.56% 31.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 8116 21.16% 52.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4102 10.70% 63.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2869 7.48% 70.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2471 6.44% 77.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1658 4.32% 81.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1256 3.28% 84.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1197 3.12% 88.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 4576 11.93% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 38348 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 24.976149 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 361.694607 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 38259 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 355.901827 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 215.943020 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 337.187447 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 12097 31.62% 31.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 8058 21.06% 52.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4075 10.65% 63.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2806 7.33% 70.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2532 6.62% 77.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1601 4.18% 81.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1324 3.46% 84.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1160 3.03% 87.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 4606 12.04% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 38259 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5153 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 24.995537 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 361.849882 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 5150 99.94% 99.94% # Reads before turning the bus around for writes
213,228c213,228
< system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.273415 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.256579 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.772702 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 4535 87.94% 87.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 9 0.17% 88.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 476 9.23% 97.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 113 2.19% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 16 0.31% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 5 0.10% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads
< system.physmem.totQLat 1494390000 # Total ticks spent queuing
< system.physmem.totMemAccLat 3910440000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.rdPerTurnAround::total 5153 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5153 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.286435 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.268739 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.792681 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 4505 87.42% 87.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 6 0.12% 87.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 503 9.76% 97.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 112 2.17% 99.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 16 0.31% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 4 0.08% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 5 0.10% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5153 # Writes before turning the bus around for reads
> system.physmem.totQLat 1533288750 # Total ticks spent queuing
> system.physmem.totMemAccLat 3949338750 # Total ticks spent from burst creation until serviced by the DRAM
230c230
< system.physmem.avgQLat 11597.36 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 11899.24 # Average queueing delay per DRAM burst
232,236c232,236
< system.physmem.avgMemAccLat 30347.36 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 146.38 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 95.34 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 146.39 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 95.37 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 30649.24 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 146.29 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 95.28 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 146.29 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 95.31 # Average system write bandwidth in MiByte/s
242,250c242,250
< system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing
< system.physmem.readRowHits 112251 # Number of row buffer hits during reads
< system.physmem.writeRowHits 62167 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 87.11 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.05 # Row buffer hit rate for writes
< system.physmem.avgGap 264726.76 # Average gap between requests
< system.physmem.pageHitRate 81.96 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 31175393250 # Time in different power states
< system.physmem.memoryStateTime::REF 1881100000 # Time in different power states
---
> system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing
> system.physmem.readRowHits 112227 # Number of row buffer hits during reads
> system.physmem.writeRowHits 62289 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.20 # Row buffer hit rate for writes
> system.physmem.avgGap 264900.96 # Average gap between requests
> system.physmem.pageHitRate 82.01 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 30998356250 # Time in different power states
> system.physmem.memoryStateTime::REF 1882400000 # Time in different power states
252c252
< system.physmem.memoryStateTime::ACT 23277299250 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 23491967500 # Time in different power states
254d253
< system.membus.throughput 241758570 # Throughput (bytes/s)
262,266c261,274
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 13620032 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 942262500 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 212813 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 212813 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 212813 # Request fanout histogram
> system.membus.reqLayer0.occupancy 942245500 # Layer occupancy (ticks)
268c276
< system.membus.respLayer1.occupancy 1221459500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1221409750 # Layer occupancy (ticks)
271,275c279,283
< system.cpu.branchPred.lookups 14808792 # Number of BP lookups
< system.cpu.branchPred.condPredicted 9910132 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 393085 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9534896 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 6736289 # Number of BTB hits
---
> system.cpu.branchPred.lookups 14808790 # Number of BP lookups
> system.cpu.branchPred.condPredicted 9910130 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 393084 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9534894 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 6736290 # Number of BTB hits
277c285
< system.cpu.branchPred.BTBHitPct 70.648794 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 70.648819 # BTB Hit Percentage
365c373
< system.cpu.numCycles 112674657 # number of cpu cycles simulated
---
> system.cpu.numCycles 112748799 # number of cpu cycles simulated
370c378
< system.cpu.discardedOps 1227274 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1227279 # Number of ops (including micro ops) which were discarded before commit
372,375c380,383
< system.cpu.cpi 1.588866 # CPI: cycles per instruction
< system.cpu.ipc 0.629380 # IPC: instructions per cycle
< system.cpu.tickCycles 93712970 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 18961687 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.589912 # CPI: cycles per instruction
> system.cpu.ipc 0.628966 # IPC: instructions per cycle
> system.cpu.tickCycles 93715149 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 19033650 # Total number of cycles that the object has spent stopped
377,378c385,386
< system.cpu.icache.tags.tagsinuse 1857.452171 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 24948252 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1857.503994 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 24948244 # Total number of references to valid blocks.
380c388
< system.cpu.icache.tags.avg_refs 560.937404 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 560.937225 # Average number of references to valid blocks.
382,384c390,392
< system.cpu.icache.tags.occ_blocks::cpu.inst 1857.452171 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.906959 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.906959 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1857.503994 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.906984 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.906984 # Average percentage of cache occupancy
386,387c394,395
< system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
391,398c399,406
< system.cpu.icache.tags.tag_accesses 50029934 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 50029934 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 24948252 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 24948252 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 24948252 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 24948252 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 24948252 # number of overall hits
< system.cpu.icache.overall_hits::total 24948252 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 50029918 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 50029918 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 24948244 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 24948244 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 24948244 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 24948244 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 24948244 # number of overall hits
> system.cpu.icache.overall_hits::total 24948244 # number of overall hits
405,416c413,424
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 894991489 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 894991489 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 894991489 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 894991489 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 894991489 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 894991489 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 24992729 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 24992729 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 24992729 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 24992729 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 24992729 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 24992729 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 894634739 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 894634739 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 894634739 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 894634739 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 894634739 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 894634739 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 24992721 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 24992721 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 24992721 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 24992721 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 24992721 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 24992721 # number of overall (read+write) accesses
423,428c431,436
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20122.568721 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20122.568721 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20114.547721 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20114.547721 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20114.547721 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20114.547721 # average overall miss latency
443,448c451,456
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804116511 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 804116511 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804116511 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 804116511 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804116511 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 804116511 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 803759261 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 803759261 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 803759261 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 803759261 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 803759261 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 803759261 # number of overall MSHR miss cycles
455,460c463,468
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18071.346111 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18071.346111 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
462d469
< system.cpu.toL2Bus.throughput 378768688 # Throughput (bytes/s)
471,475c478,496
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 21338816 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 333420 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 333420 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 333420 # Request fanout histogram
478c499
< system.cpu.toL2Bus.respLayer0.occupancy 67675489 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 67675739 # Layer occupancy (ticks)
480c501
< system.cpu.toL2Bus.respLayer1.occupancy 268454939 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 268453439 # Layer occupancy (ticks)
483c504
< system.cpu.l2cache.tags.tagsinuse 29924.855625 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 29925.727358 # Cycle average of tags in use
488,492c509,513
< system.cpu.l2cache.tags.occ_blocks::writebacks 26686.795429 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.060196 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.814416 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098818 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.913234 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 26686.334760 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3239.392599 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.814402 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098858 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.913261 # Average percentage of cache occupancy
494,497c515,518
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1148 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9890 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19364 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9850 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19418 # Occupied blocks per task id
520,527c541,548
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978942750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1978942750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7452442750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7452442750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 9431385500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 9431385500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 9431385500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 9431385500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1985312250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1985312250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7483113000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7483113000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 9468425250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 9468425250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 9468425250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 9468425250 # number of overall miss cycles
546,553c567,574
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74242.834365 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74242.834365 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72863.860128 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72863.860128 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73148.940543 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73148.940543 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74481.795160 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 74481.795160 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73163.728625 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73163.728625 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73436.217367 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73436.217367 # average overall miss latency
578,585c599,606
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1636163750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1636163750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6153335250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6153335250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7789499000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 7789499000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7789499000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 7789499000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1642872250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1642872250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6184053500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6184053500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7826925750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 7826925750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7826925750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 7826925750 # number of overall MSHR miss cycles
594,601c615,622
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61546.936127 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61546.936127 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60162.254715 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60162.254715 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61799.287165 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61799.287165 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60462.592517 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60462.592517 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
604,605c625,626
< system.cpu.dcache.tags.tagsinuse 4068.182682 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42664218 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4068.200974 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42664255 # Total number of references to valid blocks.
607c628
< system.cpu.dcache.tags.avg_refs 265.787553 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 265.787783 # Average number of references to valid blocks.
609,611c630,632
< system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.182682 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.993209 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.993209 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.200974 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.993213 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.993213 # Average percentage of cache occupancy
613,615c634,636
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id
617,622c638,643
< system.cpu.dcache.tags.tag_accesses 86013120 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 86013120 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 22988546 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 22988546 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 19643834 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 19643834 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 86013136 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 86013136 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 22988554 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 22988554 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 19643863 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 19643863 # number of WriteReq hits
627,630c648,651
< system.cpu.dcache.demand_hits::cpu.inst 42632380 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 42632380 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 42632380 # number of overall hits
< system.cpu.dcache.overall_hits::total 42632380 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.inst 42632417 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 42632417 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 42632417 # number of overall hits
> system.cpu.dcache.overall_hits::total 42632417 # number of overall hits
633,648c654,669
< system.cpu.dcache.WriteReq_misses::cpu.inst 206067 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 206067 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.inst 262082 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 262082 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 262082 # number of overall misses
< system.cpu.dcache.overall_misses::total 262082 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2143200689 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2143200689 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15189809250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 15189809250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 17333009939 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17333009939 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 17333009939 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17333009939 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 23044561 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23044561 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.WriteReq_misses::cpu.inst 206038 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 206038 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.inst 262053 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 262053 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 262053 # number of overall misses
> system.cpu.dcache.overall_misses::total 262053 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2150622439 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2150622439 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15250404250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 15250404250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 17401026689 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17401026689 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 17401026689 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17401026689 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 23044569 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23044569 # number of ReadReq accesses(hits+misses)
655,658c676,679
< system.cpu.dcache.demand_accesses::cpu.inst 42894462 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42894462 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 42894462 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42894462 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.inst 42894470 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42894470 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 42894470 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42894470 # number of overall (read+write) accesses
661,674c682,695
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66135.827485 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66135.827485 # average overall miss latency
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010380 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.010380 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.006109 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.006109 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.006109 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.006109 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38393.688101 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 38393.688101 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 74017.434891 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74017.434891 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 66402.699794 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 66402.699794 # average overall miss latency
687,692c708,713
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99029 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 99029 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 101562 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 101562 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 101562 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 101562 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99000 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 99000 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 101533 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 101533 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 101533 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 101533 # number of overall MSHR hits
701,708c722,729
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1986266811 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1986266811 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7607104750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7607104750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593371561 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9593371561 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593371561 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9593371561 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1992994061 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 1992994061 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7637775000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7637775000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9630769061 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9630769061 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9630769061 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9630769061 # number of overall MSHR miss cycles
717,724c738,745
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37264.763117 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37264.763117 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71355.733478 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71355.733478 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency