Cross Reference: /gem5/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.060131 # Number of seconds simulated
4sim_ticks 60130734500 # Number of ticks simulated
5final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.060132 # Number of seconds simulated
4sim_ticks 60131512500 # Number of ticks simulated
5final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 310652 # Simulator instruction rate (inst/s)
8host_op_rate 397278 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 263409545 # Simulator tick rate (ticks/s)
10host_mem_usage 281384 # Number of bytes of host memory used
11host_seconds 228.28 # Real time elapsed on the host

7host_inst_rate 320494 # Simulator instruction rate (inst/s)
8host_op_rate 409865 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 271758284 # Simulator tick rate (ticks/s)
10host_mem_usage 281048 # Number of bytes of host memory used
11host_seconds 221.27 # Real time elapsed on the host

12sim_insts 70915150 # Number of instructions simulated
13sim_ops 90690106 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory
19system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory
23system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory

29system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s)

29system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s)

40system.physmem.readReqs 128515 # Number of read requests accepted
41system.physmem.writeReqs 86552 # Number of write requests accepted
42system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue
43system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue
44system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM
45system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
46system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM
47system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side
48system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side
49system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
52system.physmem.perBankRdBursts::0 8086 # Per bank write bursts
53system.physmem.perBankRdBursts::1 8335 # Per bank write bursts
54system.physmem.perBankRdBursts::2 8257 # Per bank write bursts
55system.physmem.perBankRdBursts::3 8155 # Per bank write bursts
56system.physmem.perBankRdBursts::4 8301 # Per bank write bursts
57system.physmem.perBankRdBursts::5 8413 # Per bank write bursts
58system.physmem.perBankRdBursts::6 8070 # Per bank write bursts
59system.physmem.perBankRdBursts::7 7917 # Per bank write bursts
60system.physmem.perBankRdBursts::8 8054 # Per bank write bursts
61system.physmem.perBankRdBursts::9 7613 # Per bank write bursts
62system.physmem.perBankRdBursts::10 7771 # Per bank write bursts
63system.physmem.perBankRdBursts::11 7825 # Per bank write bursts
64system.physmem.perBankRdBursts::12 7888 # Per bank write bursts
65system.physmem.perBankRdBursts::13 7870 # Per bank write bursts
66system.physmem.perBankRdBursts::14 7981 # Per bank write bursts
67system.physmem.perBankRdBursts::15 7974 # Per bank write bursts
68system.physmem.perBankWrBursts::0 5400 # Per bank write bursts
69system.physmem.perBankWrBursts::1 5549 # Per bank write bursts
70system.physmem.perBankWrBursts::2 5475 # Per bank write bursts
71system.physmem.perBankWrBursts::3 5349 # Per bank write bursts
72system.physmem.perBankWrBursts::4 5387 # Per bank write bursts
73system.physmem.perBankWrBursts::5 5586 # Per bank write bursts
74system.physmem.perBankWrBursts::6 5325 # Per bank write bursts
75system.physmem.perBankWrBursts::7 5260 # Per bank write bursts
76system.physmem.perBankWrBursts::8 5187 # Per bank write bursts
77system.physmem.perBankWrBursts::9 5135 # Per bank write bursts
78system.physmem.perBankWrBursts::10 5306 # Per bank write bursts
79system.physmem.perBankWrBursts::11 5279 # Per bank write bursts
80system.physmem.perBankWrBursts::12 5541 # Per bank write bursts
81system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
82system.physmem.perBankWrBursts::14 5706 # Per bank write bursts
83system.physmem.perBankWrBursts::15 5441 # Per bank write bursts
84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

86system.physmem.totGap 60130703000 # Total gap between requests

86system.physmem.totGap 60131481000 # Total gap between requests

87system.physmem.readPktSize::0 0 # Read request sizes (log2)
88system.physmem.readPktSize::1 0 # Read request sizes (log2)
89system.physmem.readPktSize::2 0 # Read request sizes (log2)
90system.physmem.readPktSize::3 0 # Read request sizes (log2)
91system.physmem.readPktSize::4 0 # Read request sizes (log2)
92system.physmem.readPktSize::5 0 # Read request sizes (log2)
93system.physmem.readPktSize::6 128515 # Read request sizes (log2)
94system.physmem.writePktSize::0 0 # Write request sizes (log2)
95system.physmem.writePktSize::1 0 # Write request sizes (log2)
96system.physmem.writePktSize::2 0 # Write request sizes (log2)
97system.physmem.writePktSize::3 0 # Write request sizes (log2)
98system.physmem.writePktSize::4 0 # Write request sizes (log2)
99system.physmem.writePktSize::5 0 # Write request sizes (log2)
100system.physmem.writePktSize::6 86552 # Write request sizes (log2)
101system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
133system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
197system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation

199system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation

199system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation

205system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation

206system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation

206system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation

209system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation
211system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes
219system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads

230system.physmem.totQLat 3048956750 # Total ticks spent queuing
231system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM

230system.physmem.totQLat 3049168000 # Total ticks spent queuing
231system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM

232system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers

233system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst

233system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst

234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

235system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst

235system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst

236system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s
237system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s
238system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s
239system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s
240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
241system.physmem.busUtil 1.79 # Data bus utilization in percentage
242system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads
243system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes
244system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
245system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing
246system.physmem.readRowHits 112228 # Number of row buffer hits during reads
247system.physmem.writeRowHits 69923 # Number of row buffer hits during writes
248system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads
249system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes

250system.physmem.avgGap 279590.56 # Average gap between requests

250system.physmem.avgGap 279594.18 # Average gap between requests

251system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined
252system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ)
253system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ)
254system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ)
255system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ)

256system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ)
257system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ)
258system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ)
259system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ)
260system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ)
261system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ)
262system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ)
263system.physmem_0.averagePower 386.883743 # Core power per rank (mW)
264system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank
265system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states
266system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states
267system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states
268system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states
269system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states
270system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states

256system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ)
257system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ)
258system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ)
259system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ)
260system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ)
261system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ)
262system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ)
263system.physmem_0.averagePower 386.918165 # Core power per rank (mW)
264system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank
265system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states
266system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states
267system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states
268system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states
269system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states
270system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states

271system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ)
272system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ)
273system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ)
274system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ)
275system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ)

276system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ)
277system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ)
278system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ)
279system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ)
280system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ)
281system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ)
282system.physmem_1.averagePower 383.200220 # Core power per rank (mW)
283system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank
284system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states

276system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ)
277system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ)
278system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ)
279system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ)
280system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ)
281system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ)
282system.physmem_1.averagePower 383.198268 # Core power per rank (mW)
283system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank
284system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states

285system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states

286system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states
287system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states
288system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states
289system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states
290system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

286system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states
287system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states
288system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states
289system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states
290system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

291system.cpu.branchPred.lookups 14827796 # Number of BP lookups
292system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted
293system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect

294system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups

294system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups

295system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits
296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

297system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage
298system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target.

297system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage
298system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target.

299system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
300system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups.
301system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits.
302system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses.
303system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches.
304system.cpu_clk_domain.clock 500 # Clock period in ticks

305system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

305system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

306system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
314system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
315system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
316system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
317system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
318system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
319system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
322system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
323system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
324system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
325system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
326system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
327system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
328system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
329system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
330system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
331system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
332system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
333system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
334system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

335system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

335system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

336system.cpu.dtb.walker.walks 0 # Table walker walks requested
337system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
338system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
339system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
340system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
341system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
342system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
343system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
344system.cpu.dtb.inst_hits 0 # ITB inst hits
345system.cpu.dtb.inst_misses 0 # ITB inst misses
346system.cpu.dtb.read_hits 0 # DTB read hits
347system.cpu.dtb.read_misses 0 # DTB read misses
348system.cpu.dtb.write_hits 0 # DTB write hits
349system.cpu.dtb.write_misses 0 # DTB write misses
350system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
351system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
352system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
353system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
354system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
355system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
356system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
357system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
358system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
359system.cpu.dtb.read_accesses 0 # DTB read accesses
360system.cpu.dtb.write_accesses 0 # DTB write accesses
361system.cpu.dtb.inst_accesses 0 # ITB inst accesses
362system.cpu.dtb.hits 0 # DTB hits
363system.cpu.dtb.misses 0 # DTB misses
364system.cpu.dtb.accesses 0 # DTB accesses

365system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

365system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

366system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
374system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
375system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
376system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
377system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
378system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
379system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
380system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
381system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
382system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
383system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
384system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
385system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
386system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
387system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
388system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
389system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
390system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
391system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
392system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
393system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
394system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

395system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

395system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

396system.cpu.itb.walker.walks 0 # Table walker walks requested
397system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
398system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
399system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
400system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
401system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
402system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
403system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
404system.cpu.itb.inst_hits 0 # ITB inst hits
405system.cpu.itb.inst_misses 0 # ITB inst misses
406system.cpu.itb.read_hits 0 # DTB read hits
407system.cpu.itb.read_misses 0 # DTB read misses
408system.cpu.itb.write_hits 0 # DTB write hits
409system.cpu.itb.write_misses 0 # DTB write misses
410system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
411system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
412system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
413system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
414system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
415system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
416system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
417system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
418system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
419system.cpu.itb.read_accesses 0 # DTB read accesses
420system.cpu.itb.write_accesses 0 # DTB write accesses
421system.cpu.itb.inst_accesses 0 # ITB inst accesses
422system.cpu.itb.hits 0 # DTB hits
423system.cpu.itb.misses 0 # DTB misses
424system.cpu.itb.accesses 0 # DTB accesses
425system.cpu.workload.num_syscalls 1946 # Number of system calls

426system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states
427system.cpu.numCycles 120261469 # number of cpu cycles simulated

426system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states
427system.cpu.numCycles 120263025 # number of cpu cycles simulated

428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
430system.cpu.committedInsts 70915150 # Number of instructions committed
431system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
432system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit
433system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching

434system.cpu.cpi 1.695850 # CPI: cycles per instruction
435system.cpu.ipc 0.589675 # IPC: instructions per cycle

434system.cpu.cpi 1.695872 # CPI: cycles per instruction
435system.cpu.ipc 0.589667 # IPC: instructions per cycle

436system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
437system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction
438system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
439system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
440system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
441system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
442system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
443system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
444system.cpu.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction
445system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
446system.cpu.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction
447system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
448system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
449system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
450system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
451system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
452system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
453system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
454system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
455system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
456system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
457system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
458system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
459system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
460system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
461system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
462system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
463system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
464system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
465system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
466system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
467system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
468system.cpu.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction
469system.cpu.op_class_0::MemWrite 20555707 22.67% 100.00% # Class of committed instruction
470system.cpu.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction
471system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction
472system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
473system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
474system.cpu.op_class_0::total 90690106 # Class of committed instruction

475system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked
476system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped
477system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

475system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked
476system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped
477system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

478system.cpu.dcache.tags.replacements 156451 # number of replacements

479system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use
480system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks.

479system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use
480system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks.

481system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks.

482system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks.

482system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks.

483system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit.

484system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor

484system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor

485system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy
486system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy
487system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
488system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
489system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id
490system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id
491system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

492system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses
493system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses
494system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
495system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits
496system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits

492system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses
493system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses
494system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
495system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits
496system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits

497system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits
498system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits
499system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits
500system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits
501system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
502system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
503system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
504system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits

505system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits
506system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits
507system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits
508system.cpu.dcache.overall_hits::total 42605457 # number of overall hits

505system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits
506system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits
507system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits
508system.cpu.dcache.overall_hits::total 42605460 # number of overall hits

509system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses
510system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses
511system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses
512system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses
513system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses
514system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses
515system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses
516system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses
517system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses
518system.cpu.dcache.overall_misses::total 299788 # number of overall misses

519system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles
520system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles
521system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles
522system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles
523system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles
524system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles
525system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles
526system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles
527system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses)
528system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses)

519system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles
520system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles
521system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles
522system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles
523system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles
524system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles
525system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles
526system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles
527system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses)
528system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses)

529system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
530system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
531system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses)
532system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses)
533system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
534system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
535system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
536system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)

537system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses
538system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses
539system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses
540system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses

537system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses
538system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses
539system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses
540system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses

541system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses
542system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses
543system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses
544system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses
545system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses
546system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses
547system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses
548system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses
549system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses
550system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses

551system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency
552system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency
553system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency
554system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency
555system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency
556system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency
557system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency
558system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency

551system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency
552system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency
553system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency
554system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency
555system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency
556system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency
557system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency
558system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency

559system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked
560system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
561system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
562system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
563system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked
564system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
565system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks
566system.cpu.dcache.writebacks::total 128145 # number of writebacks
567system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits
568system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits
569system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits
570system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits
571system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits
572system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits
573system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits
574system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits
575system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses
576system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses
577system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses
578system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses
579system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses
580system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses
581system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses
582system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses
583system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses
584system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses

585system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles
586system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles
587system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles
588system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles
589system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles
590system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles
591system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles
592system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles
593system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles
594system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles

585system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles
586system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles
587system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles
588system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles
589system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles
590system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles
591system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles
592system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles
593system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles
594system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles

595system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
596system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
597system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
598system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
599system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187431 # mshr miss rate for SoftPFReq accesses
600system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187431 # mshr miss rate for SoftPFReq accesses
601system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses
602system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses
603system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
604system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses

605system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency
606system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency
607system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency
608system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency
609system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency
610system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency
611system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency
612system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency
613system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency
614system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency
615system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

605system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573 # average ReadReq mshr miss latency
606system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573 # average ReadReq mshr miss latency
607system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645 # average WriteReq mshr miss latency
608system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645 # average WriteReq mshr miss latency
609system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169 # average SoftPFReq mshr miss latency
610system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169 # average SoftPFReq mshr miss latency
611system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549 # average overall mshr miss latency
612system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549 # average overall mshr miss latency
613system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125 # average overall mshr miss latency
614system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125 # average overall mshr miss latency
615system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

616system.cpu.icache.tags.replacements 43545 # number of replacements

617system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use

617system.cpu.icache.tags.tagsinuse 1851.999823 # Cycle average of tags in use

618system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks.
619system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks.
620system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks.
621system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

622system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor
623system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy
624system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy

622system.cpu.icache.tags.occ_blocks::cpu.inst 1851.999823 # Average occupied blocks per requestor
623system.cpu.icache.tags.occ_percent::cpu.inst 0.904297 # Average percentage of cache occupancy
624system.cpu.icache.tags.occ_percent::total 0.904297 # Average percentage of cache occupancy

625system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
626system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
627system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
628system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
629system.cpu.icache.tags.age_task_id_blocks_1024::3 898 # Occupied blocks per task id
630system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 # Occupied blocks per task id
631system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
632system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses
633system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses

634system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

634system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

635system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits
636system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits
637system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits
638system.cpu.icache.demand_hits::total 25048343 # number of demand (read+write) hits
639system.cpu.icache.overall_hits::cpu.inst 25048343 # number of overall hits
640system.cpu.icache.overall_hits::total 25048343 # number of overall hits
641system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses
642system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses
643system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses
644system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses
645system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses
646system.cpu.icache.overall_misses::total 45588 # number of overall misses

647system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles
648system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles
649system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles
650system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles
651system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles
652system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles

647system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042263500 # number of ReadReq miss cycles
648system.cpu.icache.ReadReq_miss_latency::total 1042263500 # number of ReadReq miss cycles
649system.cpu.icache.demand_miss_latency::cpu.inst 1042263500 # number of demand (read+write) miss cycles
650system.cpu.icache.demand_miss_latency::total 1042263500 # number of demand (read+write) miss cycles
651system.cpu.icache.overall_miss_latency::cpu.inst 1042263500 # number of overall miss cycles
652system.cpu.icache.overall_miss_latency::total 1042263500 # number of overall miss cycles

653system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses)
654system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses)
655system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses
656system.cpu.icache.demand_accesses::total 25093931 # number of demand (read+write) accesses
657system.cpu.icache.overall_accesses::cpu.inst 25093931 # number of overall (read+write) accesses
658system.cpu.icache.overall_accesses::total 25093931 # number of overall (read+write) accesses
659system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses
660system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses
661system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses
662system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses
663system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses
664system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses

665system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency
666system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency
667system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
668system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency
669system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
670system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency

665system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194 # average ReadReq miss latency
666system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194 # average ReadReq miss latency
667system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency
668system.cpu.icache.demand_avg_miss_latency::total 22862.672194 # average overall miss latency
669system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency
670system.cpu.icache.overall_avg_miss_latency::total 22862.672194 # average overall miss latency

671system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
672system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
673system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
674system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
675system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
676system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
677system.cpu.icache.writebacks::writebacks 43545 # number of writebacks
678system.cpu.icache.writebacks::total 43545 # number of writebacks
679system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45588 # number of ReadReq MSHR misses
680system.cpu.icache.ReadReq_mshr_misses::total 45588 # number of ReadReq MSHR misses
681system.cpu.icache.demand_mshr_misses::cpu.inst 45588 # number of demand (read+write) MSHR misses
682system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses
683system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses
684system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses

685system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles
686system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles
687system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles
688system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles
689system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles
690system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles

685system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996676500 # number of ReadReq MSHR miss cycles
686system.cpu.icache.ReadReq_mshr_miss_latency::total 996676500 # number of ReadReq MSHR miss cycles
687system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996676500 # number of demand (read+write) MSHR miss cycles
688system.cpu.icache.demand_mshr_miss_latency::total 996676500 # number of demand (read+write) MSHR miss cycles
689system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996676500 # number of overall MSHR miss cycles
690system.cpu.icache.overall_mshr_miss_latency::total 996676500 # number of overall MSHR miss cycles

691system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses
692system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses
693system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses
694system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses
695system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses
696system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses

697system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency
698system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency
699system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
700system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
701system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
702system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
703system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

697system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.694130 # average ReadReq mshr miss latency
698system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.694130 # average ReadReq mshr miss latency
699system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency
700system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency
701system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency
702system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency
703system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

704system.cpu.l2cache.tags.replacements 97176 # number of replacements

705system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use

705system.cpu.l2cache.tags.tagsinuse 31292.341702 # Cycle average of tags in use

706system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks.
707system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks.
708system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks.

709system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit.
710system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor
711system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor
712system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor

709system.cpu.l2cache.tags.warmup_cycle 10980599000 # Cycle when the warmup percentage was hit.
710system.cpu.l2cache.tags.occ_blocks::writebacks 476.632754 # Average occupied blocks per requestor
711system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.083150 # Average occupied blocks per requestor
712system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.625798 # Average occupied blocks per requestor

713system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy
714system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy
715system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy
716system.cpu.l2cache.tags.occ_percent::total 0.954966 # Average percentage of cache occupancy
717system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
718system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
719system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
720system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12834 # Occupied blocks per task id
721system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17840 # Occupied blocks per task id
722system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id
723system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
724system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses
725system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses

726system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

726system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

727system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits
728system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits
729system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits
730system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits
731system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits
732system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits
733system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41101 # number of ReadCleanReq hits
734system.cpu.l2cache.ReadCleanReq_hits::total 41101 # number of ReadCleanReq hits
735system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits
736system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits
737system.cpu.l2cache.demand_hits::cpu.inst 41101 # number of demand (read+write) hits
738system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits
739system.cpu.l2cache.demand_hits::total 77547 # number of demand (read+write) hits
740system.cpu.l2cache.overall_hits::cpu.inst 41101 # number of overall hits
741system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits
742system.cpu.l2cache.overall_hits::total 77547 # number of overall hits
743system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses
744system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses
745system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4487 # number of ReadCleanReq misses
746system.cpu.l2cache.ReadCleanReq_misses::total 4487 # number of ReadCleanReq misses
747system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses
748system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses
749system.cpu.l2cache.demand_misses::cpu.inst 4487 # number of demand (read+write) misses
750system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses
751system.cpu.l2cache.demand_misses::total 128588 # number of demand (read+write) misses
752system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses
753system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses
754system.cpu.l2cache.overall_misses::total 128588 # number of overall misses

755system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles
756system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles
757system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles
758system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles
759system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles
760system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles
761system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles
762system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles
763system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles
764system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles
765system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles
766system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles

755system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269327500 # number of ReadExReq miss cycles
756system.cpu.l2cache.ReadExReq_miss_latency::total 9269327500 # number of ReadExReq miss cycles
757system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492863000 # number of ReadCleanReq miss cycles
758system.cpu.l2cache.ReadCleanReq_miss_latency::total 492863000 # number of ReadCleanReq miss cycles
759system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2253034500 # number of ReadSharedReq miss cycles
760system.cpu.l2cache.ReadSharedReq_miss_latency::total 2253034500 # number of ReadSharedReq miss cycles
761system.cpu.l2cache.demand_miss_latency::cpu.inst 492863000 # number of demand (read+write) miss cycles
762system.cpu.l2cache.demand_miss_latency::cpu.data 11522362000 # number of demand (read+write) miss cycles
763system.cpu.l2cache.demand_miss_latency::total 12015225000 # number of demand (read+write) miss cycles
764system.cpu.l2cache.overall_miss_latency::cpu.inst 492863000 # number of overall miss cycles
765system.cpu.l2cache.overall_miss_latency::cpu.data 11522362000 # number of overall miss cycles
766system.cpu.l2cache.overall_miss_latency::total 12015225000 # number of overall miss cycles

767system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses)
768system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses)
769system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses)
770system.cpu.l2cache.WritebackClean_accesses::total 39944 # number of WritebackClean accesses(hits+misses)
771system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses)
772system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses)
773system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45588 # number of ReadCleanReq accesses(hits+misses)
774system.cpu.l2cache.ReadCleanReq_accesses::total 45588 # number of ReadCleanReq accesses(hits+misses)
775system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses)
776system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses)
777system.cpu.l2cache.demand_accesses::cpu.inst 45588 # number of demand (read+write) accesses
778system.cpu.l2cache.demand_accesses::cpu.data 160547 # number of demand (read+write) accesses
779system.cpu.l2cache.demand_accesses::total 206135 # number of demand (read+write) accesses
780system.cpu.l2cache.overall_accesses::cpu.inst 45588 # number of overall (read+write) accesses
781system.cpu.l2cache.overall_accesses::cpu.data 160547 # number of overall (read+write) accesses
782system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses
783system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses
784system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses
785system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098425 # miss rate for ReadCleanReq accesses
786system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098425 # miss rate for ReadCleanReq accesses
787system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses
788system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses
789system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098425 # miss rate for demand accesses
790system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses
791system.cpu.l2cache.demand_miss_rate::total 0.623805 # miss rate for demand accesses
792system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses
793system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses
794system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses

795system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency
796system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency
797system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency
798system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency
799system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency
800system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency
801system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
802system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
803system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency
804system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
805system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
806system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency

795system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.207219 # average ReadExReq miss latency
796system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.207219 # average ReadExReq miss latency
797system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109842.433697 # average ReadCleanReq miss latency
798system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109842.433697 # average ReadCleanReq miss latency
799system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103426.115498 # average ReadSharedReq miss latency
800system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103426.115498 # average ReadSharedReq miss latency
801system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency
802system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency
803system.cpu.l2cache.demand_avg_miss_latency::total 93439.706660 # average overall miss latency
804system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency
805system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency
806system.cpu.l2cache.overall_avg_miss_latency::total 93439.706660 # average overall miss latency

807system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
808system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
809system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
810system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
811system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
812system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
813system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks
814system.cpu.l2cache.writebacks::total 86552 # number of writebacks
815system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits
816system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits
817system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits
818system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits
819system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
820system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
821system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
822system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
823system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
824system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
825system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
826system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
827system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses
828system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses
829system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses
830system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses
831system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses
832system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses
833system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses
834system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses
835system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses
836system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses
837system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses
838system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses

839system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles
840system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles
841system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles
842system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles
843system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles
844system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles
845system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles
846system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles
847system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles
848system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles
849system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles
850system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles

839system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246157500 # number of ReadExReq MSHR miss cycles
840system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246157500 # number of ReadExReq MSHR miss cycles
841system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446695500 # number of ReadCleanReq MSHR miss cycles
842system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446695500 # number of ReadCleanReq MSHR miss cycles
843system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029647000 # number of ReadSharedReq MSHR miss cycles
844system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029647000 # number of ReadSharedReq MSHR miss cycles
845system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446695500 # number of demand (read+write) MSHR miss cycles
846system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275804500 # number of demand (read+write) MSHR miss cycles
847system.cpu.l2cache.demand_mshr_miss_latency::total 10722500000 # number of demand (read+write) MSHR miss cycles
848system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446695500 # number of overall MSHR miss cycles
849system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275804500 # number of overall MSHR miss cycles
850system.cpu.l2cache.overall_mshr_miss_latency::total 10722500000 # number of overall MSHR miss cycles

851system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
852system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
853system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses
854system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses
855system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses
856system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses
857system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses
858system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses
859system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses
860system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses
861system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses
862system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses
863system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses
864system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses

865system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency
866system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency
867system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency
868system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency
869system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency
870system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency
871system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
872system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
873system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency
874system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
875system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
876system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency

865system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency
866system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency
867system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency
868system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency
869system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency
870system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency
871system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency
872system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency
873system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency
874system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency
875system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency
876system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency

877system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter.
878system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data.
879system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
880system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter.
881system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
882system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

883system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

883system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

884system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution
885system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution
886system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution
887system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution
888system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution
889system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution
890system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution
891system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution
892system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes)
893system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes)
894system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes)
895system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes)
896system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes)
897system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes)
898system.cpu.toL2Bus.snoops 97176 # Total snoops (count)
899system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes)
900system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram
901system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram
902system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram
903system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
904system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram
905system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram
906system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
907system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
908system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
909system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
910system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram
911system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks)
912system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
913system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks)
914system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
915system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks)
916system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
917system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter.
918system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data.
919system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
920system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
921system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
922system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

923system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states

923system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states

924system.membus.trans_dist::ReadResp 26198 # Transaction distribution
925system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution
926system.membus.trans_dist::CleanEvict 7237 # Transaction distribution
927system.membus.trans_dist::ReadExReq 102317 # Transaction distribution
928system.membus.trans_dist::ReadExResp 102317 # Transaction distribution
929system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution
930system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes)
931system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes)
932system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes)
933system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes)
934system.membus.snoops 0 # Total snoops (count)
935system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
936system.membus.snoop_fanout::samples 128515 # Request fanout histogram
937system.membus.snoop_fanout::mean 0 # Request fanout histogram
938system.membus.snoop_fanout::stdev 0 # Request fanout histogram
939system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
940system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram
941system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
942system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
943system.membus.snoop_fanout::min_value 0 # Request fanout histogram
944system.membus.snoop_fanout::max_value 0 # Request fanout histogram
945system.membus.snoop_fanout::total 128515 # Request fanout histogram

946system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks)

946system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks)

947system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)

948system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks)

948system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks)