1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.057847 # Number of seconds simulated
4sim_ticks 57847312000 # Number of ticks simulated
5final_tick 57847312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 186854 # Simulator instruction rate (inst/s)
8host_op_rate 238959 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 152421830 # Simulator tick rate (ticks/s)
10host_mem_usage 261476 # Number of bytes of host memory used
11host_seconds 379.52 # Real time elapsed on the host
12sim_insts 70915127 # Number of instructions simulated
13sim_ops 90690083 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 8247680 # Number of bytes read from this memory
17system.physmem.bytes_read::total 8247680 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory
20system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory
21system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory
22system.physmem.num_reads::cpu.inst 128870 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 128870 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 142576720 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 142576720 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 5607037 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 5607037 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_write::writebacks 92880098 # Write bandwidth from this memory (bytes/s)
31system.physmem.bw_write::total 92880098 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total::writebacks 92880098 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.bw_total::cpu.inst 142576720 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::total 235456818 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.readReqs 128870 # Number of read requests accepted
36system.physmem.writeReqs 83951 # Number of write requests accepted
37system.physmem.readBursts 128870 # Number of DRAM read bursts, including those serviced by the write queue
38system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue
39system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM
40system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
41system.physmem.bytesWritten 5370944 # Total number of bytes written to DRAM
42system.physmem.bytesReadSys 8247680 # Total read bytes from the system interface side
43system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side
44system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
47system.physmem.perBankRdBursts::0 8158 # Per bank write bursts
48system.physmem.perBankRdBursts::1 8375 # Per bank write bursts
49system.physmem.perBankRdBursts::2 8229 # Per bank write bursts
50system.physmem.perBankRdBursts::3 8171 # Per bank write bursts
51system.physmem.perBankRdBursts::4 8319 # Per bank write bursts
52system.physmem.perBankRdBursts::5 8450 # Per bank write bursts
53system.physmem.perBankRdBursts::6 8089 # Per bank write bursts
54system.physmem.perBankRdBursts::7 7970 # Per bank write bursts
55system.physmem.perBankRdBursts::8 8071 # Per bank write bursts
56system.physmem.perBankRdBursts::9 7641 # Per bank write bursts
57system.physmem.perBankRdBursts::10 7819 # Per bank write bursts
58system.physmem.perBankRdBursts::11 7830 # Per bank write bursts
59system.physmem.perBankRdBursts::12 7881 # Per bank write bursts
60system.physmem.perBankRdBursts::13 7879 # Per bank write bursts
61system.physmem.perBankRdBursts::14 7977 # Per bank write bursts
62system.physmem.perBankRdBursts::15 8006 # Per bank write bursts
63system.physmem.perBankWrBursts::0 5181 # Per bank write bursts
64system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
65system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
66system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
67system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
68system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
69system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
70system.physmem.perBankWrBursts::7 5047 # Per bank write bursts
71system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
72system.physmem.perBankWrBursts::9 5087 # Per bank write bursts
73system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
74system.physmem.perBankWrBursts::11 5143 # Per bank write bursts
75system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
76system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
77system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
78system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
81system.physmem.totGap 57847280000 # Total gap between requests
82system.physmem.readPktSize::0 0 # Read request sizes (log2)
83system.physmem.readPktSize::1 0 # Read request sizes (log2)
84system.physmem.readPktSize::2 0 # Read request sizes (log2)
85system.physmem.readPktSize::3 0 # Read request sizes (log2)
86system.physmem.readPktSize::4 0 # Read request sizes (log2)
87system.physmem.readPktSize::5 0 # Read request sizes (log2)
88system.physmem.readPktSize::6 128870 # Read request sizes (log2)
89system.physmem.writePktSize::0 0 # Write request sizes (log2)
90system.physmem.writePktSize::1 0 # Write request sizes (log2)
91system.physmem.writePktSize::2 0 # Write request sizes (log2)
92system.physmem.writePktSize::3 0 # Write request sizes (log2)
93system.physmem.writePktSize::4 0 # Write request sizes (log2)
94system.physmem.writePktSize::5 0 # Write request sizes (log2)
95system.physmem.writePktSize::6 83951 # Write request sizes (log2)
96system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
--- 29 unchanged lines hidden (view full) ---
135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::15 620 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 634 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 5143 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 5165 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 5165 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 5168 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::24 5180 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 5181 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 5171 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 5287 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 5241 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 5206 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 5744 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 5252 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::32 5160 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
--- 12 unchanged lines hidden (view full) ---
184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
192system.physmem.bytesPerActivate::samples 38379 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::mean 354.780687 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::gmean 215.561409 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::stdev 335.824723 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::0-127 12139 31.63% 31.63% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::128-255 8088 21.07% 52.70% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::256-383 4086 10.65% 63.35% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::384-511 2872 7.48% 70.83% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::512-639 2530 6.59% 77.43% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::640-767 1664 4.34% 81.76% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::768-895 1273 3.32% 85.08% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::896-1023 1227 3.20% 88.27% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1024-1151 4500 11.73% 100.00% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::total 38379 # Bytes accessed per row activation
206system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes
207system.physmem.rdPerTurnAround::mean 24.981187 # Reads before turning the bus around for writes
208system.physmem.rdPerTurnAround::stdev 361.178240 # Reads before turning the bus around for writes
209system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes
210system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes
214system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads
215system.physmem.wrPerTurnAround::mean 16.276377 # Writes before turning the bus around for reads
216system.physmem.wrPerTurnAround::gmean 16.259366 # Writes before turning the bus around for reads
217system.physmem.wrPerTurnAround::stdev 0.777117 # Writes before turning the bus around for reads
218system.physmem.wrPerTurnAround::16 4528 87.82% 87.82% # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::17 7 0.14% 87.96% # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::18 480 9.31% 97.27% # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::19 121 2.35% 99.61% # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::20 14 0.27% 99.88% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads
228system.physmem.totQLat 1539171500 # Total ticks spent queuing
229system.physmem.totMemAccLat 3955390250 # Total ticks spent from burst creation until serviced by the DRAM
230system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers
231system.physmem.avgQLat 11944.06 # Average queueing delay per DRAM burst
232system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
233system.physmem.avgMemAccLat 30694.06 # Average memory access latency per DRAM burst
234system.physmem.avgRdBW 142.57 # Average DRAM read bandwidth in MiByte/s
235system.physmem.avgWrBW 92.85 # Average achieved write bandwidth in MiByte/s
236system.physmem.avgRdBWSys 142.58 # Average system read bandwidth in MiByte/s
237system.physmem.avgWrBWSys 92.88 # Average system write bandwidth in MiByte/s
238system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
239system.physmem.busUtil 1.84 # Data bus utilization in percentage
240system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads
241system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes
242system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
243system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing
244system.physmem.readRowHits 112176 # Number of row buffer hits during reads
245system.physmem.writeRowHits 62224 # Number of row buffer hits during writes
246system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
247system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes
248system.physmem.avgGap 271811.90 # Average gap between requests
249system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined
250system.physmem.memoryStateTime::IDLE 32236826000 # Time in different power states
251system.physmem.memoryStateTime::REF 1931540000 # Time in different power states
252system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
253system.physmem.memoryStateTime::ACT 23675959000 # Time in different power states
254system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
255system.physmem.actEnergy::0 151237800 # Energy for activate commands per rank (pJ)
256system.physmem.actEnergy::1 138899880 # Energy for activate commands per rank (pJ)
257system.physmem.preEnergy::0 82520625 # Energy for precharge commands per rank (pJ)
258system.physmem.preEnergy::1 75788625 # Energy for precharge commands per rank (pJ)
259system.physmem.readEnergy::0 512678400 # Energy for read commands per rank (pJ)
260system.physmem.readEnergy::1 492078600 # Energy for read commands per rank (pJ)
261system.physmem.writeEnergy::0 272322000 # Energy for write commands per rank (pJ)
262system.physmem.writeEnergy::1 271486080 # Energy for write commands per rank (pJ)
263system.physmem.refreshEnergy::0 3778092240 # Energy for refresh commands per rank (pJ)
264system.physmem.refreshEnergy::1 3778092240 # Energy for refresh commands per rank (pJ)
265system.physmem.actBackEnergy::0 11712850200 # Energy for active background per rank (pJ)
266system.physmem.actBackEnergy::1 11277598770 # Energy for active background per rank (pJ)
267system.physmem.preBackEnergy::0 24432156750 # Energy for precharge background per rank (pJ)
268system.physmem.preBackEnergy::1 24813956250 # Energy for precharge background per rank (pJ)
269system.physmem.totalEnergy::0 40941858015 # Total energy per rank (pJ)
270system.physmem.totalEnergy::1 40847900445 # Total energy per rank (pJ)
271system.physmem.averagePower::0 707.794027 # Core power per rank (mW)
272system.physmem.averagePower::1 706.169709 # Core power per rank (mW)
273system.cpu.branchPred.lookups 14825675 # Number of BP lookups
274system.cpu.branchPred.condPredicted 9917897 # Number of conditional branches predicted
275system.cpu.branchPred.condIncorrect 395023 # Number of conditional branches incorrect
276system.cpu.branchPred.BTBLookups 9456669 # Number of BTB lookups
277system.cpu.branchPred.BTBHits 6745546 # Number of BTB hits
278system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
279system.cpu.branchPred.BTBHitPct 71.331100 # BTB Hit Percentage
280system.cpu.branchPred.usedRAS 1719567 # Number of times the RAS was used to get a target.
281system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
282system.cpu_clk_domain.clock 500 # Clock period in ticks
283system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
284system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
285system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
286system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
287system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
288system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
289system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
290system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
360system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
361system.cpu.itb.read_accesses 0 # DTB read accesses
362system.cpu.itb.write_accesses 0 # DTB write accesses
363system.cpu.itb.inst_accesses 0 # ITB inst accesses
364system.cpu.itb.hits 0 # DTB hits
365system.cpu.itb.misses 0 # DTB misses
366system.cpu.itb.accesses 0 # DTB accesses
367system.cpu.workload.num_syscalls 1946 # Number of system calls
368system.cpu.numCycles 115694624 # number of cpu cycles simulated
369system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
370system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
371system.cpu.committedInsts 70915127 # Number of instructions committed
372system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
373system.cpu.discardedOps 1146301 # Number of ops (including micro ops) which were discarded before commit
374system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
375system.cpu.cpi 1.631452 # CPI: cycles per instruction
376system.cpu.ipc 0.612951 # IPC: instructions per cycle
377system.cpu.tickCycles 96938261 # Number of cycles that the object actually ticked
378system.cpu.idleCycles 18756363 # Total number of cycles that the object has spent stopped
379system.cpu.dcache.tags.replacements 156422 # number of replacements
380system.cpu.dcache.tags.tagsinuse 4068.596798 # Cycle average of tags in use
381system.cpu.dcache.tags.total_refs 42665450 # Total number of references to valid blocks.
382system.cpu.dcache.tags.sampled_refs 160518 # Sample count of references to valid blocks.
383system.cpu.dcache.tags.avg_refs 265.798540 # Average number of references to valid blocks.
384system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit.
385system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.596798 # Average occupied blocks per requestor
386system.cpu.dcache.tags.occ_percent::cpu.inst 0.993310 # Average percentage of cache occupancy
387system.cpu.dcache.tags.occ_percent::total 0.993310 # Average percentage of cache occupancy
388system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
389system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
390system.cpu.dcache.tags.age_task_id_blocks_1024::1 750 # Occupied blocks per task id
391system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id
392system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
393system.cpu.dcache.tags.tag_accesses 86015580 # Number of tag accesses
394system.cpu.dcache.tags.data_accesses 86015580 # Number of data accesses
395system.cpu.dcache.ReadReq_hits::cpu.inst 22989734 # number of ReadReq hits
396system.cpu.dcache.ReadReq_hits::total 22989734 # number of ReadReq hits
397system.cpu.dcache.WriteReq_hits::cpu.inst 19643878 # number of WriteReq hits
398system.cpu.dcache.WriteReq_hits::total 19643878 # number of WriteReq hits
399system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits
400system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
401system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits
402system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
403system.cpu.dcache.demand_hits::cpu.inst 42633612 # number of demand (read+write) hits
404system.cpu.dcache.demand_hits::total 42633612 # number of demand (read+write) hits
405system.cpu.dcache.overall_hits::cpu.inst 42633612 # number of overall hits
406system.cpu.dcache.overall_hits::total 42633612 # number of overall hits
407system.cpu.dcache.ReadReq_misses::cpu.inst 56058 # number of ReadReq misses
408system.cpu.dcache.ReadReq_misses::total 56058 # number of ReadReq misses
409system.cpu.dcache.WriteReq_misses::cpu.inst 206023 # number of WriteReq misses
410system.cpu.dcache.WriteReq_misses::total 206023 # number of WriteReq misses
411system.cpu.dcache.demand_misses::cpu.inst 262081 # number of demand (read+write) misses
412system.cpu.dcache.demand_misses::total 262081 # number of demand (read+write) misses
413system.cpu.dcache.overall_misses::cpu.inst 262081 # number of overall misses
414system.cpu.dcache.overall_misses::total 262081 # number of overall misses
415system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2156088187 # number of ReadReq miss cycles
416system.cpu.dcache.ReadReq_miss_latency::total 2156088187 # number of ReadReq miss cycles
417system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15241867750 # number of WriteReq miss cycles
418system.cpu.dcache.WriteReq_miss_latency::total 15241867750 # number of WriteReq miss cycles
419system.cpu.dcache.demand_miss_latency::cpu.inst 17397955937 # number of demand (read+write) miss cycles
420system.cpu.dcache.demand_miss_latency::total 17397955937 # number of demand (read+write) miss cycles
421system.cpu.dcache.overall_miss_latency::cpu.inst 17397955937 # number of overall miss cycles
422system.cpu.dcache.overall_miss_latency::total 17397955937 # number of overall miss cycles
423system.cpu.dcache.ReadReq_accesses::cpu.inst 23045792 # number of ReadReq accesses(hits+misses)
424system.cpu.dcache.ReadReq_accesses::total 23045792 # number of ReadReq accesses(hits+misses)
425system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses)
426system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
427system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses)
428system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
429system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses)
430system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
431system.cpu.dcache.demand_accesses::cpu.inst 42895693 # number of demand (read+write) accesses
432system.cpu.dcache.demand_accesses::total 42895693 # number of demand (read+write) accesses
433system.cpu.dcache.overall_accesses::cpu.inst 42895693 # number of overall (read+write) accesses
434system.cpu.dcache.overall_accesses::total 42895693 # number of overall (read+write) accesses
435system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002432 # miss rate for ReadReq accesses
436system.cpu.dcache.ReadReq_miss_rate::total 0.002432 # miss rate for ReadReq accesses
437system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010379 # miss rate for WriteReq accesses
438system.cpu.dcache.WriteReq_miss_rate::total 0.010379 # miss rate for WriteReq accesses
439system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses
440system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses
441system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses
442system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses
443system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38461.739395 # average ReadReq miss latency
444system.cpu.dcache.ReadReq_avg_miss_latency::total 38461.739395 # average ReadReq miss latency
445system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73981.389214 # average WriteReq miss latency
446system.cpu.dcache.WriteReq_avg_miss_latency::total 73981.389214 # average WriteReq miss latency
447system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency
448system.cpu.dcache.demand_avg_miss_latency::total 66383.888710 # average overall miss latency
449system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency
450system.cpu.dcache.overall_avg_miss_latency::total 66383.888710 # average overall miss latency
451system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
452system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
453system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
454system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
455system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
456system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
457system.cpu.dcache.fast_writes 0 # number of fast writes performed
458system.cpu.dcache.cache_copies 0 # number of cache copies performed
459system.cpu.dcache.writebacks::writebacks 128433 # number of writebacks
460system.cpu.dcache.writebacks::total 128433 # number of writebacks
461system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2574 # number of ReadReq MSHR hits
462system.cpu.dcache.ReadReq_mshr_hits::total 2574 # number of ReadReq MSHR hits
463system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 98989 # number of WriteReq MSHR hits
464system.cpu.dcache.WriteReq_mshr_hits::total 98989 # number of WriteReq MSHR hits
465system.cpu.dcache.demand_mshr_hits::cpu.inst 101563 # number of demand (read+write) MSHR hits
466system.cpu.dcache.demand_mshr_hits::total 101563 # number of demand (read+write) MSHR hits
467system.cpu.dcache.overall_mshr_hits::cpu.inst 101563 # number of overall MSHR hits
468system.cpu.dcache.overall_mshr_hits::total 101563 # number of overall MSHR hits
469system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53484 # number of ReadReq MSHR misses
470system.cpu.dcache.ReadReq_mshr_misses::total 53484 # number of ReadReq MSHR misses
471system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107034 # number of WriteReq MSHR misses
472system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
473system.cpu.dcache.demand_mshr_misses::cpu.inst 160518 # number of demand (read+write) MSHR misses
474system.cpu.dcache.demand_mshr_misses::total 160518 # number of demand (read+write) MSHR misses
475system.cpu.dcache.overall_mshr_misses::cpu.inst 160518 # number of overall MSHR misses
476system.cpu.dcache.overall_mshr_misses::total 160518 # number of overall MSHR misses
477system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1995361313 # number of ReadReq MSHR miss cycles
478system.cpu.dcache.ReadReq_mshr_miss_latency::total 1995361313 # number of ReadReq MSHR miss cycles
479system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7633992250 # number of WriteReq MSHR miss cycles
480system.cpu.dcache.WriteReq_mshr_miss_latency::total 7633992250 # number of WriteReq MSHR miss cycles
481system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9629353563 # number of demand (read+write) MSHR miss cycles
482system.cpu.dcache.demand_mshr_miss_latency::total 9629353563 # number of demand (read+write) MSHR miss cycles
483system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9629353563 # number of overall MSHR miss cycles
484system.cpu.dcache.overall_mshr_miss_latency::total 9629353563 # number of overall MSHR miss cycles
485system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses
486system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses
487system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses
488system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
489system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for demand accesses
490system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses
491system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses
492system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
493system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37307.630562 # average ReadReq mshr miss latency
494system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37307.630562 # average ReadReq mshr miss latency
495system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71323.058561 # average WriteReq mshr miss latency
496system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71323.058561 # average WriteReq mshr miss latency
497system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency
498system.cpu.dcache.demand_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency
499system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency
500system.cpu.dcache.overall_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency
501system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
502system.cpu.icache.tags.replacements 42703 # number of replacements
503system.cpu.icache.tags.tagsinuse 1858.978148 # Cycle average of tags in use
504system.cpu.icache.tags.total_refs 25082437 # Total number of references to valid blocks.
505system.cpu.icache.tags.sampled_refs 44745 # Sample count of references to valid blocks.
506system.cpu.icache.tags.avg_refs 560.564018 # Average number of references to valid blocks.
507system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
508system.cpu.icache.tags.occ_blocks::cpu.inst 1858.978148 # Average occupied blocks per requestor
509system.cpu.icache.tags.occ_percent::cpu.inst 0.907704 # Average percentage of cache occupancy
510system.cpu.icache.tags.occ_percent::total 0.907704 # Average percentage of cache occupancy
511system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
512system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
513system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
514system.cpu.icache.tags.age_task_id_blocks_1024::3 804 # Occupied blocks per task id
515system.cpu.icache.tags.age_task_id_blocks_1024::4 1118 # Occupied blocks per task id
516system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
517system.cpu.icache.tags.tag_accesses 50299111 # Number of tag accesses
518system.cpu.icache.tags.data_accesses 50299111 # Number of data accesses
519system.cpu.icache.ReadReq_hits::cpu.inst 25082437 # number of ReadReq hits
520system.cpu.icache.ReadReq_hits::total 25082437 # number of ReadReq hits
521system.cpu.icache.demand_hits::cpu.inst 25082437 # number of demand (read+write) hits
522system.cpu.icache.demand_hits::total 25082437 # number of demand (read+write) hits
523system.cpu.icache.overall_hits::cpu.inst 25082437 # number of overall hits
524system.cpu.icache.overall_hits::total 25082437 # number of overall hits
525system.cpu.icache.ReadReq_misses::cpu.inst 44746 # number of ReadReq misses
526system.cpu.icache.ReadReq_misses::total 44746 # number of ReadReq misses
527system.cpu.icache.demand_misses::cpu.inst 44746 # number of demand (read+write) misses
528system.cpu.icache.demand_misses::total 44746 # number of demand (read+write) misses
529system.cpu.icache.overall_misses::cpu.inst 44746 # number of overall misses
530system.cpu.icache.overall_misses::total 44746 # number of overall misses
531system.cpu.icache.ReadReq_miss_latency::cpu.inst 897678738 # number of ReadReq miss cycles
532system.cpu.icache.ReadReq_miss_latency::total 897678738 # number of ReadReq miss cycles
533system.cpu.icache.demand_miss_latency::cpu.inst 897678738 # number of demand (read+write) miss cycles
534system.cpu.icache.demand_miss_latency::total 897678738 # number of demand (read+write) miss cycles
535system.cpu.icache.overall_miss_latency::cpu.inst 897678738 # number of overall miss cycles
536system.cpu.icache.overall_miss_latency::total 897678738 # number of overall miss cycles
537system.cpu.icache.ReadReq_accesses::cpu.inst 25127183 # number of ReadReq accesses(hits+misses)
538system.cpu.icache.ReadReq_accesses::total 25127183 # number of ReadReq accesses(hits+misses)
539system.cpu.icache.demand_accesses::cpu.inst 25127183 # number of demand (read+write) accesses
540system.cpu.icache.demand_accesses::total 25127183 # number of demand (read+write) accesses
541system.cpu.icache.overall_accesses::cpu.inst 25127183 # number of overall (read+write) accesses
542system.cpu.icache.overall_accesses::total 25127183 # number of overall (read+write) accesses
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544system.cpu.icache.ReadReq_miss_rate::total 0.001781 # miss rate for ReadReq accesses
545system.cpu.icache.demand_miss_rate::cpu.inst 0.001781 # miss rate for demand accesses
546system.cpu.icache.demand_miss_rate::total 0.001781 # miss rate for demand accesses
547system.cpu.icache.overall_miss_rate::cpu.inst 0.001781 # miss rate for overall accesses
548system.cpu.icache.overall_miss_rate::total 0.001781 # miss rate for overall accesses
549system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20061.653287 # average ReadReq miss latency
550system.cpu.icache.ReadReq_avg_miss_latency::total 20061.653287 # average ReadReq miss latency
551system.cpu.icache.demand_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency
552system.cpu.icache.demand_avg_miss_latency::total 20061.653287 # average overall miss latency
553system.cpu.icache.overall_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency
554system.cpu.icache.overall_avg_miss_latency::total 20061.653287 # average overall miss latency
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556system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
557system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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559system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
560system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
561system.cpu.icache.fast_writes 0 # number of fast writes performed
562system.cpu.icache.cache_copies 0 # number of cache copies performed
563system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44746 # number of ReadReq MSHR misses
564system.cpu.icache.ReadReq_mshr_misses::total 44746 # number of ReadReq MSHR misses
565system.cpu.icache.demand_mshr_misses::cpu.inst 44746 # number of demand (read+write) MSHR misses
566system.cpu.icache.demand_mshr_misses::total 44746 # number of demand (read+write) MSHR misses
567system.cpu.icache.overall_mshr_misses::cpu.inst 44746 # number of overall MSHR misses
568system.cpu.icache.overall_mshr_misses::total 44746 # number of overall MSHR misses
569system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 806263262 # number of ReadReq MSHR miss cycles
570system.cpu.icache.ReadReq_mshr_miss_latency::total 806263262 # number of ReadReq MSHR miss cycles
571system.cpu.icache.demand_mshr_miss_latency::cpu.inst 806263262 # number of demand (read+write) MSHR miss cycles
572system.cpu.icache.demand_mshr_miss_latency::total 806263262 # number of demand (read+write) MSHR miss cycles
573system.cpu.icache.overall_mshr_miss_latency::cpu.inst 806263262 # number of overall MSHR miss cycles
574system.cpu.icache.overall_mshr_miss_latency::total 806263262 # number of overall MSHR miss cycles
575system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for ReadReq accesses
576system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001781 # mshr miss rate for ReadReq accesses
577system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for demand accesses
578system.cpu.icache.demand_mshr_miss_rate::total 0.001781 # mshr miss rate for demand accesses
579system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for overall accesses
580system.cpu.icache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses
581system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18018.666741 # average ReadReq mshr miss latency
582system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18018.666741 # average ReadReq mshr miss latency
583system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency
584system.cpu.icache.demand_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency
585system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency
586system.cpu.icache.overall_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency
587system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
588system.cpu.l2cache.tags.replacements 95732 # number of replacements
589system.cpu.l2cache.tags.tagsinuse 29937.969910 # Cycle average of tags in use
590system.cpu.l2cache.tags.total_refs 99708 # Total number of references to valid blocks.
591system.cpu.l2cache.tags.sampled_refs 126850 # Sample count of references to valid blocks.
592system.cpu.l2cache.tags.avg_refs 0.786031 # Average number of references to valid blocks.
593system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
594system.cpu.l2cache.tags.occ_blocks::writebacks 26706.762922 # Average occupied blocks per requestor
595system.cpu.l2cache.tags.occ_blocks::cpu.inst 3231.206988 # Average occupied blocks per requestor
596system.cpu.l2cache.tags.occ_percent::writebacks 0.815026 # Average percentage of cache occupancy
597system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098609 # Average percentage of cache occupancy
598system.cpu.l2cache.tags.occ_percent::total 0.913634 # Average percentage of cache occupancy
599system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
600system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
601system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1136 # Occupied blocks per task id
602system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9726 # Occupied blocks per task id
603system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19542 # Occupied blocks per task id
604system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id
605system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
606system.cpu.l2cache.tags.tag_accesses 2903460 # Number of tag accesses
607system.cpu.l2cache.tags.data_accesses 2903460 # Number of data accesses
608system.cpu.l2cache.ReadReq_hits::cpu.inst 71567 # number of ReadReq hits
609system.cpu.l2cache.ReadReq_hits::total 71567 # number of ReadReq hits
610system.cpu.l2cache.Writeback_hits::writebacks 128433 # number of Writeback hits
611system.cpu.l2cache.Writeback_hits::total 128433 # number of Writeback hits
612system.cpu.l2cache.ReadExReq_hits::cpu.inst 4753 # number of ReadExReq hits
613system.cpu.l2cache.ReadExReq_hits::total 4753 # number of ReadExReq hits
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615system.cpu.l2cache.demand_hits::total 76320 # number of demand (read+write) hits
616system.cpu.l2cache.overall_hits::cpu.inst 76320 # number of overall hits
617system.cpu.l2cache.overall_hits::total 76320 # number of overall hits
618system.cpu.l2cache.ReadReq_misses::cpu.inst 26663 # number of ReadReq misses
619system.cpu.l2cache.ReadReq_misses::total 26663 # number of ReadReq misses
620system.cpu.l2cache.ReadExReq_misses::cpu.inst 102281 # number of ReadExReq misses
621system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses
622system.cpu.l2cache.demand_misses::cpu.inst 128944 # number of demand (read+write) misses
623system.cpu.l2cache.demand_misses::total 128944 # number of demand (read+write) misses
624system.cpu.l2cache.overall_misses::cpu.inst 128944 # number of overall misses
625system.cpu.l2cache.overall_misses::total 128944 # number of overall misses
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627system.cpu.l2cache.ReadReq_miss_latency::total 1987300500 # number of ReadReq miss cycles
628system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7479393750 # number of ReadExReq miss cycles
629system.cpu.l2cache.ReadExReq_miss_latency::total 7479393750 # number of ReadExReq miss cycles
630system.cpu.l2cache.demand_miss_latency::cpu.inst 9466694250 # number of demand (read+write) miss cycles
631system.cpu.l2cache.demand_miss_latency::total 9466694250 # number of demand (read+write) miss cycles
632system.cpu.l2cache.overall_miss_latency::cpu.inst 9466694250 # number of overall miss cycles
633system.cpu.l2cache.overall_miss_latency::total 9466694250 # number of overall miss cycles
634system.cpu.l2cache.ReadReq_accesses::cpu.inst 98230 # number of ReadReq accesses(hits+misses)
635system.cpu.l2cache.ReadReq_accesses::total 98230 # number of ReadReq accesses(hits+misses)
636system.cpu.l2cache.Writeback_accesses::writebacks 128433 # number of Writeback accesses(hits+misses)
637system.cpu.l2cache.Writeback_accesses::total 128433 # number of Writeback accesses(hits+misses)
638system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107034 # number of ReadExReq accesses(hits+misses)
639system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
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641system.cpu.l2cache.demand_accesses::total 205264 # number of demand (read+write) accesses
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643system.cpu.l2cache.overall_accesses::total 205264 # number of overall (read+write) accesses
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645system.cpu.l2cache.ReadReq_miss_rate::total 0.271434 # miss rate for ReadReq accesses
646system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955594 # miss rate for ReadExReq accesses
647system.cpu.l2cache.ReadExReq_miss_rate::total 0.955594 # miss rate for ReadExReq accesses
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649system.cpu.l2cache.demand_miss_rate::total 0.628186 # miss rate for demand accesses
650system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628186 # miss rate for overall accesses
651system.cpu.l2cache.overall_miss_rate::total 0.628186 # miss rate for overall accesses
652system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74534.017177 # average ReadReq miss latency
653system.cpu.l2cache.ReadReq_avg_miss_latency::total 74534.017177 # average ReadReq miss latency
654system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73125.934924 # average ReadExReq miss latency
655system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73125.934924 # average ReadExReq miss latency
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657system.cpu.l2cache.demand_avg_miss_latency::total 73417.097732 # average overall miss latency
658system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency
659system.cpu.l2cache.overall_avg_miss_latency::total 73417.097732 # average overall miss latency
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664system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
665system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
666system.cpu.l2cache.fast_writes 0 # number of fast writes performed
667system.cpu.l2cache.cache_copies 0 # number of cache copies performed
668system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks
669system.cpu.l2cache.writebacks::total 83951 # number of writebacks
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671system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
672system.cpu.l2cache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
673system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
674system.cpu.l2cache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
675system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
676system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26590 # number of ReadReq MSHR misses
677system.cpu.l2cache.ReadReq_mshr_misses::total 26590 # number of ReadReq MSHR misses
678system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102281 # number of ReadExReq MSHR misses
679system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses
680system.cpu.l2cache.demand_mshr_misses::cpu.inst 128871 # number of demand (read+write) MSHR misses
681system.cpu.l2cache.demand_mshr_misses::total 128871 # number of demand (read+write) MSHR misses
682system.cpu.l2cache.overall_mshr_misses::cpu.inst 128871 # number of overall MSHR misses
683system.cpu.l2cache.overall_mshr_misses::total 128871 # number of overall MSHR misses
684system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1644904750 # number of ReadReq MSHR miss cycles
685system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1644904750 # number of ReadReq MSHR miss cycles
686system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6188348750 # number of ReadExReq MSHR miss cycles
687system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6188348750 # number of ReadExReq MSHR miss cycles
688system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7833253500 # number of demand (read+write) MSHR miss cycles
689system.cpu.l2cache.demand_mshr_miss_latency::total 7833253500 # number of demand (read+write) MSHR miss cycles
690system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7833253500 # number of overall MSHR miss cycles
691system.cpu.l2cache.overall_mshr_miss_latency::total 7833253500 # number of overall MSHR miss cycles
692system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270691 # mshr miss rate for ReadReq accesses
693system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270691 # mshr miss rate for ReadReq accesses
694system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955594 # mshr miss rate for ReadExReq accesses
695system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955594 # mshr miss rate for ReadExReq accesses
696system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for demand accesses
697system.cpu.l2cache.demand_mshr_miss_rate::total 0.627831 # mshr miss rate for demand accesses
698system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for overall accesses
699system.cpu.l2cache.overall_mshr_miss_rate::total 0.627831 # mshr miss rate for overall accesses
700system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61861.780745 # average ReadReq mshr miss latency
701system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61861.780745 # average ReadReq mshr miss latency
702system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60503.404836 # average ReadExReq mshr miss latency
703system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60503.404836 # average ReadExReq mshr miss latency
704system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency
705system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency
706system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency
707system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency
708system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
709system.cpu.toL2Bus.trans_dist::ReadReq 98230 # Transaction distribution
710system.cpu.toL2Bus.trans_dist::ReadResp 98229 # Transaction distribution
711system.cpu.toL2Bus.trans_dist::Writeback 128433 # Transaction distribution
712system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
713system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
714system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89491 # Packet count per connected master and slave (bytes)
715system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449469 # Packet count per connected master and slave (bytes)
716system.cpu.toL2Bus.pkt_count::total 538960 # Packet count per connected master and slave (bytes)
717system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2863680 # Cumulative packet size per connected master and slave (bytes)
718system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492864 # Cumulative packet size per connected master and slave (bytes)
719system.cpu.toL2Bus.pkt_size::total 21356544 # Cumulative packet size per connected master and slave (bytes)
720system.cpu.toL2Bus.snoops 0 # Total snoops (count)
721system.cpu.toL2Bus.snoop_fanout::samples 333697 # Request fanout histogram
722system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
723system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
724system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
725system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
726system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
727system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
728system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
729system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
730system.cpu.toL2Bus.snoop_fanout::5 333697 100.00% 100.00% # Request fanout histogram
731system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
732system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
733system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
734system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
735system.cpu.toL2Bus.snoop_fanout::total 333697 # Request fanout histogram
736system.cpu.toL2Bus.reqLayer0.occupancy 295281500 # Layer occupancy (ticks)
737system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
738system.cpu.toL2Bus.respLayer0.occupancy 68080238 # Layer occupancy (ticks)
739system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
740system.cpu.toL2Bus.respLayer1.occupancy 268447937 # Layer occupancy (ticks)
741system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
742system.membus.trans_dist::ReadReq 26589 # Transaction distribution
743system.membus.trans_dist::ReadResp 26589 # Transaction distribution
744system.membus.trans_dist::Writeback 83951 # Transaction distribution
745system.membus.trans_dist::ReadExReq 102281 # Transaction distribution
746system.membus.trans_dist::ReadExResp 102281 # Transaction distribution
747system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341691 # Packet count per connected master and slave (bytes)
748system.membus.pkt_count::total 341691 # Packet count per connected master and slave (bytes)
749system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620544 # Cumulative packet size per connected master and slave (bytes)
750system.membus.pkt_size::total 13620544 # Cumulative packet size per connected master and slave (bytes)
751system.membus.snoops 0 # Total snoops (count)
752system.membus.snoop_fanout::samples 212821 # Request fanout histogram
753system.membus.snoop_fanout::mean 0 # Request fanout histogram
754system.membus.snoop_fanout::stdev 0 # Request fanout histogram
755system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
756system.membus.snoop_fanout::0 212821 100.00% 100.00% # Request fanout histogram
757system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
758system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
759system.membus.snoop_fanout::min_value 0 # Request fanout histogram
760system.membus.snoop_fanout::max_value 0 # Request fanout histogram
761system.membus.snoop_fanout::total 212821 # Request fanout histogram
762system.membus.reqLayer0.occupancy 929388500 # Layer occupancy (ticks)
763system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
764system.membus.respLayer1.occupancy 1213397000 # Layer occupancy (ticks)
765system.membus.respLayer1.utilization 2.1 # Layer utilization (%)
766
767---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.057847 # Number of seconds simulated
4sim_ticks 57847312000 # Number of ticks simulated
5final_tick 57847312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 186854 # Simulator instruction rate (inst/s)
8host_op_rate 238959 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 152421830 # Simulator tick rate (ticks/s)
10host_mem_usage 261476 # Number of bytes of host memory used
11host_seconds 379.52 # Real time elapsed on the host
12sim_insts 70915127 # Number of instructions simulated
13sim_ops 90690083 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 8247680 # Number of bytes read from this memory
17system.physmem.bytes_read::total 8247680 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory
20system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory
21system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory
22system.physmem.num_reads::cpu.inst 128870 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 128870 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 142576720 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 142576720 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 5607037 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 5607037 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_write::writebacks 92880098 # Write bandwidth from this memory (bytes/s)
31system.physmem.bw_write::total 92880098 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total::writebacks 92880098 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.bw_total::cpu.inst 142576720 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::total 235456818 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.readReqs 128870 # Number of read requests accepted
36system.physmem.writeReqs 83951 # Number of write requests accepted
37system.physmem.readBursts 128870 # Number of DRAM read bursts, including those serviced by the write queue
38system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue
39system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM
40system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
41system.physmem.bytesWritten 5370944 # Total number of bytes written to DRAM
42system.physmem.bytesReadSys 8247680 # Total read bytes from the system interface side
43system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side
44system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
47system.physmem.perBankRdBursts::0 8158 # Per bank write bursts
48system.physmem.perBankRdBursts::1 8375 # Per bank write bursts
49system.physmem.perBankRdBursts::2 8229 # Per bank write bursts
50system.physmem.perBankRdBursts::3 8171 # Per bank write bursts
51system.physmem.perBankRdBursts::4 8319 # Per bank write bursts
52system.physmem.perBankRdBursts::5 8450 # Per bank write bursts
53system.physmem.perBankRdBursts::6 8089 # Per bank write bursts
54system.physmem.perBankRdBursts::7 7970 # Per bank write bursts
55system.physmem.perBankRdBursts::8 8071 # Per bank write bursts
56system.physmem.perBankRdBursts::9 7641 # Per bank write bursts
57system.physmem.perBankRdBursts::10 7819 # Per bank write bursts
58system.physmem.perBankRdBursts::11 7830 # Per bank write bursts
59system.physmem.perBankRdBursts::12 7881 # Per bank write bursts
60system.physmem.perBankRdBursts::13 7879 # Per bank write bursts
61system.physmem.perBankRdBursts::14 7977 # Per bank write bursts
62system.physmem.perBankRdBursts::15 8006 # Per bank write bursts
63system.physmem.perBankWrBursts::0 5181 # Per bank write bursts
64system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
65system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
66system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
67system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
68system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
69system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
70system.physmem.perBankWrBursts::7 5047 # Per bank write bursts
71system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
72system.physmem.perBankWrBursts::9 5087 # Per bank write bursts
73system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
74system.physmem.perBankWrBursts::11 5143 # Per bank write bursts
75system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
76system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
77system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
78system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
81system.physmem.totGap 57847280000 # Total gap between requests
82system.physmem.readPktSize::0 0 # Read request sizes (log2)
83system.physmem.readPktSize::1 0 # Read request sizes (log2)
84system.physmem.readPktSize::2 0 # Read request sizes (log2)
85system.physmem.readPktSize::3 0 # Read request sizes (log2)
86system.physmem.readPktSize::4 0 # Read request sizes (log2)
87system.physmem.readPktSize::5 0 # Read request sizes (log2)
88system.physmem.readPktSize::6 128870 # Read request sizes (log2)
89system.physmem.writePktSize::0 0 # Write request sizes (log2)
90system.physmem.writePktSize::1 0 # Write request sizes (log2)
91system.physmem.writePktSize::2 0 # Write request sizes (log2)
92system.physmem.writePktSize::3 0 # Write request sizes (log2)
93system.physmem.writePktSize::4 0 # Write request sizes (log2)
94system.physmem.writePktSize::5 0 # Write request sizes (log2)
95system.physmem.writePktSize::6 83951 # Write request sizes (log2)
96system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
--- 29 unchanged lines hidden (view full) ---
135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::15 620 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 634 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 5143 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 5165 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 5165 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 5168 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::24 5180 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 5181 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 5171 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 5287 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 5241 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 5206 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 5744 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 5252 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::32 5160 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
192system.physmem.bytesPerActivate::samples 38379 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::mean 354.780687 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::gmean 215.561409 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::stdev 335.824723 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::0-127 12139 31.63% 31.63% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::128-255 8088 21.07% 52.70% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::256-383 4086 10.65% 63.35% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::384-511 2872 7.48% 70.83% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::512-639 2530 6.59% 77.43% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::640-767 1664 4.34% 81.76% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::768-895 1273 3.32% 85.08% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::896-1023 1227 3.20% 88.27% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1024-1151 4500 11.73% 100.00% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::total 38379 # Bytes accessed per row activation
206system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes
207system.physmem.rdPerTurnAround::mean 24.981187 # Reads before turning the bus around for writes
208system.physmem.rdPerTurnAround::stdev 361.178240 # Reads before turning the bus around for writes
209system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes
210system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes
214system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads
215system.physmem.wrPerTurnAround::mean 16.276377 # Writes before turning the bus around for reads
216system.physmem.wrPerTurnAround::gmean 16.259366 # Writes before turning the bus around for reads
217system.physmem.wrPerTurnAround::stdev 0.777117 # Writes before turning the bus around for reads
218system.physmem.wrPerTurnAround::16 4528 87.82% 87.82% # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::17 7 0.14% 87.96% # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::18 480 9.31% 97.27% # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::19 121 2.35% 99.61% # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::20 14 0.27% 99.88% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads
228system.physmem.totQLat 1539171500 # Total ticks spent queuing
229system.physmem.totMemAccLat 3955390250 # Total ticks spent from burst creation until serviced by the DRAM
230system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers
231system.physmem.avgQLat 11944.06 # Average queueing delay per DRAM burst
232system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
233system.physmem.avgMemAccLat 30694.06 # Average memory access latency per DRAM burst
234system.physmem.avgRdBW 142.57 # Average DRAM read bandwidth in MiByte/s
235system.physmem.avgWrBW 92.85 # Average achieved write bandwidth in MiByte/s
236system.physmem.avgRdBWSys 142.58 # Average system read bandwidth in MiByte/s
237system.physmem.avgWrBWSys 92.88 # Average system write bandwidth in MiByte/s
238system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
239system.physmem.busUtil 1.84 # Data bus utilization in percentage
240system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads
241system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes
242system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
243system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing
244system.physmem.readRowHits 112176 # Number of row buffer hits during reads
245system.physmem.writeRowHits 62224 # Number of row buffer hits during writes
246system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
247system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes
248system.physmem.avgGap 271811.90 # Average gap between requests
249system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined
250system.physmem.memoryStateTime::IDLE 32236826000 # Time in different power states
251system.physmem.memoryStateTime::REF 1931540000 # Time in different power states
252system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
253system.physmem.memoryStateTime::ACT 23675959000 # Time in different power states
254system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
255system.physmem.actEnergy::0 151237800 # Energy for activate commands per rank (pJ)
256system.physmem.actEnergy::1 138899880 # Energy for activate commands per rank (pJ)
257system.physmem.preEnergy::0 82520625 # Energy for precharge commands per rank (pJ)
258system.physmem.preEnergy::1 75788625 # Energy for precharge commands per rank (pJ)
259system.physmem.readEnergy::0 512678400 # Energy for read commands per rank (pJ)
260system.physmem.readEnergy::1 492078600 # Energy for read commands per rank (pJ)
261system.physmem.writeEnergy::0 272322000 # Energy for write commands per rank (pJ)
262system.physmem.writeEnergy::1 271486080 # Energy for write commands per rank (pJ)
263system.physmem.refreshEnergy::0 3778092240 # Energy for refresh commands per rank (pJ)
264system.physmem.refreshEnergy::1 3778092240 # Energy for refresh commands per rank (pJ)
265system.physmem.actBackEnergy::0 11712850200 # Energy for active background per rank (pJ)
266system.physmem.actBackEnergy::1 11277598770 # Energy for active background per rank (pJ)
267system.physmem.preBackEnergy::0 24432156750 # Energy for precharge background per rank (pJ)
268system.physmem.preBackEnergy::1 24813956250 # Energy for precharge background per rank (pJ)
269system.physmem.totalEnergy::0 40941858015 # Total energy per rank (pJ)
270system.physmem.totalEnergy::1 40847900445 # Total energy per rank (pJ)
271system.physmem.averagePower::0 707.794027 # Core power per rank (mW)
272system.physmem.averagePower::1 706.169709 # Core power per rank (mW)
273system.cpu.branchPred.lookups 14825675 # Number of BP lookups
274system.cpu.branchPred.condPredicted 9917897 # Number of conditional branches predicted
275system.cpu.branchPred.condIncorrect 395023 # Number of conditional branches incorrect
276system.cpu.branchPred.BTBLookups 9456669 # Number of BTB lookups
277system.cpu.branchPred.BTBHits 6745546 # Number of BTB hits
278system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
279system.cpu.branchPred.BTBHitPct 71.331100 # BTB Hit Percentage
280system.cpu.branchPred.usedRAS 1719567 # Number of times the RAS was used to get a target.
281system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
282system.cpu_clk_domain.clock 500 # Clock period in ticks
283system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
284system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
285system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
286system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
287system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
288system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
289system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
290system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
360system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
361system.cpu.itb.read_accesses 0 # DTB read accesses
362system.cpu.itb.write_accesses 0 # DTB write accesses
363system.cpu.itb.inst_accesses 0 # ITB inst accesses
364system.cpu.itb.hits 0 # DTB hits
365system.cpu.itb.misses 0 # DTB misses
366system.cpu.itb.accesses 0 # DTB accesses
367system.cpu.workload.num_syscalls 1946 # Number of system calls
368system.cpu.numCycles 115694624 # number of cpu cycles simulated
369system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
370system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
371system.cpu.committedInsts 70915127 # Number of instructions committed
372system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
373system.cpu.discardedOps 1146301 # Number of ops (including micro ops) which were discarded before commit
374system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
375system.cpu.cpi 1.631452 # CPI: cycles per instruction
376system.cpu.ipc 0.612951 # IPC: instructions per cycle
377system.cpu.tickCycles 96938261 # Number of cycles that the object actually ticked
378system.cpu.idleCycles 18756363 # Total number of cycles that the object has spent stopped
379system.cpu.dcache.tags.replacements 156422 # number of replacements
380system.cpu.dcache.tags.tagsinuse 4068.596798 # Cycle average of tags in use
381system.cpu.dcache.tags.total_refs 42665450 # Total number of references to valid blocks.
382system.cpu.dcache.tags.sampled_refs 160518 # Sample count of references to valid blocks.
383system.cpu.dcache.tags.avg_refs 265.798540 # Average number of references to valid blocks.
384system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit.
385system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.596798 # Average occupied blocks per requestor
386system.cpu.dcache.tags.occ_percent::cpu.inst 0.993310 # Average percentage of cache occupancy
387system.cpu.dcache.tags.occ_percent::total 0.993310 # Average percentage of cache occupancy
388system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
389system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
390system.cpu.dcache.tags.age_task_id_blocks_1024::1 750 # Occupied blocks per task id
391system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id
392system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
393system.cpu.dcache.tags.tag_accesses 86015580 # Number of tag accesses
394system.cpu.dcache.tags.data_accesses 86015580 # Number of data accesses
395system.cpu.dcache.ReadReq_hits::cpu.inst 22989734 # number of ReadReq hits
396system.cpu.dcache.ReadReq_hits::total 22989734 # number of ReadReq hits
397system.cpu.dcache.WriteReq_hits::cpu.inst 19643878 # number of WriteReq hits
398system.cpu.dcache.WriteReq_hits::total 19643878 # number of WriteReq hits
399system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits
400system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
401system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits
402system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
403system.cpu.dcache.demand_hits::cpu.inst 42633612 # number of demand (read+write) hits
404system.cpu.dcache.demand_hits::total 42633612 # number of demand (read+write) hits
405system.cpu.dcache.overall_hits::cpu.inst 42633612 # number of overall hits
406system.cpu.dcache.overall_hits::total 42633612 # number of overall hits
407system.cpu.dcache.ReadReq_misses::cpu.inst 56058 # number of ReadReq misses
408system.cpu.dcache.ReadReq_misses::total 56058 # number of ReadReq misses
409system.cpu.dcache.WriteReq_misses::cpu.inst 206023 # number of WriteReq misses
410system.cpu.dcache.WriteReq_misses::total 206023 # number of WriteReq misses
411system.cpu.dcache.demand_misses::cpu.inst 262081 # number of demand (read+write) misses
412system.cpu.dcache.demand_misses::total 262081 # number of demand (read+write) misses
413system.cpu.dcache.overall_misses::cpu.inst 262081 # number of overall misses
414system.cpu.dcache.overall_misses::total 262081 # number of overall misses
415system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2156088187 # number of ReadReq miss cycles
416system.cpu.dcache.ReadReq_miss_latency::total 2156088187 # number of ReadReq miss cycles
417system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15241867750 # number of WriteReq miss cycles
418system.cpu.dcache.WriteReq_miss_latency::total 15241867750 # number of WriteReq miss cycles
419system.cpu.dcache.demand_miss_latency::cpu.inst 17397955937 # number of demand (read+write) miss cycles
420system.cpu.dcache.demand_miss_latency::total 17397955937 # number of demand (read+write) miss cycles
421system.cpu.dcache.overall_miss_latency::cpu.inst 17397955937 # number of overall miss cycles
422system.cpu.dcache.overall_miss_latency::total 17397955937 # number of overall miss cycles
423system.cpu.dcache.ReadReq_accesses::cpu.inst 23045792 # number of ReadReq accesses(hits+misses)
424system.cpu.dcache.ReadReq_accesses::total 23045792 # number of ReadReq accesses(hits+misses)
425system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses)
426system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
427system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses)
428system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
429system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses)
430system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
431system.cpu.dcache.demand_accesses::cpu.inst 42895693 # number of demand (read+write) accesses
432system.cpu.dcache.demand_accesses::total 42895693 # number of demand (read+write) accesses
433system.cpu.dcache.overall_accesses::cpu.inst 42895693 # number of overall (read+write) accesses
434system.cpu.dcache.overall_accesses::total 42895693 # number of overall (read+write) accesses
435system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002432 # miss rate for ReadReq accesses
436system.cpu.dcache.ReadReq_miss_rate::total 0.002432 # miss rate for ReadReq accesses
437system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010379 # miss rate for WriteReq accesses
438system.cpu.dcache.WriteReq_miss_rate::total 0.010379 # miss rate for WriteReq accesses
439system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses
440system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses
441system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses
442system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses
443system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38461.739395 # average ReadReq miss latency
444system.cpu.dcache.ReadReq_avg_miss_latency::total 38461.739395 # average ReadReq miss latency
445system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73981.389214 # average WriteReq miss latency
446system.cpu.dcache.WriteReq_avg_miss_latency::total 73981.389214 # average WriteReq miss latency
447system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency
448system.cpu.dcache.demand_avg_miss_latency::total 66383.888710 # average overall miss latency
449system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency
450system.cpu.dcache.overall_avg_miss_latency::total 66383.888710 # average overall miss latency
451system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
452system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
453system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
454system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
455system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
456system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
457system.cpu.dcache.fast_writes 0 # number of fast writes performed
458system.cpu.dcache.cache_copies 0 # number of cache copies performed
459system.cpu.dcache.writebacks::writebacks 128433 # number of writebacks
460system.cpu.dcache.writebacks::total 128433 # number of writebacks
461system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2574 # number of ReadReq MSHR hits
462system.cpu.dcache.ReadReq_mshr_hits::total 2574 # number of ReadReq MSHR hits
463system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 98989 # number of WriteReq MSHR hits
464system.cpu.dcache.WriteReq_mshr_hits::total 98989 # number of WriteReq MSHR hits
465system.cpu.dcache.demand_mshr_hits::cpu.inst 101563 # number of demand (read+write) MSHR hits
466system.cpu.dcache.demand_mshr_hits::total 101563 # number of demand (read+write) MSHR hits
467system.cpu.dcache.overall_mshr_hits::cpu.inst 101563 # number of overall MSHR hits
468system.cpu.dcache.overall_mshr_hits::total 101563 # number of overall MSHR hits
469system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53484 # number of ReadReq MSHR misses
470system.cpu.dcache.ReadReq_mshr_misses::total 53484 # number of ReadReq MSHR misses
471system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107034 # number of WriteReq MSHR misses
472system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
473system.cpu.dcache.demand_mshr_misses::cpu.inst 160518 # number of demand (read+write) MSHR misses
474system.cpu.dcache.demand_mshr_misses::total 160518 # number of demand (read+write) MSHR misses
475system.cpu.dcache.overall_mshr_misses::cpu.inst 160518 # number of overall MSHR misses
476system.cpu.dcache.overall_mshr_misses::total 160518 # number of overall MSHR misses
477system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1995361313 # number of ReadReq MSHR miss cycles
478system.cpu.dcache.ReadReq_mshr_miss_latency::total 1995361313 # number of ReadReq MSHR miss cycles
479system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7633992250 # number of WriteReq MSHR miss cycles
480system.cpu.dcache.WriteReq_mshr_miss_latency::total 7633992250 # number of WriteReq MSHR miss cycles
481system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9629353563 # number of demand (read+write) MSHR miss cycles
482system.cpu.dcache.demand_mshr_miss_latency::total 9629353563 # number of demand (read+write) MSHR miss cycles
483system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9629353563 # number of overall MSHR miss cycles
484system.cpu.dcache.overall_mshr_miss_latency::total 9629353563 # number of overall MSHR miss cycles
485system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses
486system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses
487system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses
488system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
489system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for demand accesses
490system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses
491system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses
492system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
493system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37307.630562 # average ReadReq mshr miss latency
494system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37307.630562 # average ReadReq mshr miss latency
495system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71323.058561 # average WriteReq mshr miss latency
496system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71323.058561 # average WriteReq mshr miss latency
497system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency
498system.cpu.dcache.demand_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency
499system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency
500system.cpu.dcache.overall_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency
501system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
502system.cpu.icache.tags.replacements 42703 # number of replacements
503system.cpu.icache.tags.tagsinuse 1858.978148 # Cycle average of tags in use
504system.cpu.icache.tags.total_refs 25082437 # Total number of references to valid blocks.
505system.cpu.icache.tags.sampled_refs 44745 # Sample count of references to valid blocks.
506system.cpu.icache.tags.avg_refs 560.564018 # Average number of references to valid blocks.
507system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
508system.cpu.icache.tags.occ_blocks::cpu.inst 1858.978148 # Average occupied blocks per requestor
509system.cpu.icache.tags.occ_percent::cpu.inst 0.907704 # Average percentage of cache occupancy
510system.cpu.icache.tags.occ_percent::total 0.907704 # Average percentage of cache occupancy
511system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
512system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
513system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
514system.cpu.icache.tags.age_task_id_blocks_1024::3 804 # Occupied blocks per task id
515system.cpu.icache.tags.age_task_id_blocks_1024::4 1118 # Occupied blocks per task id
516system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
517system.cpu.icache.tags.tag_accesses 50299111 # Number of tag accesses
518system.cpu.icache.tags.data_accesses 50299111 # Number of data accesses
519system.cpu.icache.ReadReq_hits::cpu.inst 25082437 # number of ReadReq hits
520system.cpu.icache.ReadReq_hits::total 25082437 # number of ReadReq hits
521system.cpu.icache.demand_hits::cpu.inst 25082437 # number of demand (read+write) hits
522system.cpu.icache.demand_hits::total 25082437 # number of demand (read+write) hits
523system.cpu.icache.overall_hits::cpu.inst 25082437 # number of overall hits
524system.cpu.icache.overall_hits::total 25082437 # number of overall hits
525system.cpu.icache.ReadReq_misses::cpu.inst 44746 # number of ReadReq misses
526system.cpu.icache.ReadReq_misses::total 44746 # number of ReadReq misses
527system.cpu.icache.demand_misses::cpu.inst 44746 # number of demand (read+write) misses
528system.cpu.icache.demand_misses::total 44746 # number of demand (read+write) misses
529system.cpu.icache.overall_misses::cpu.inst 44746 # number of overall misses
530system.cpu.icache.overall_misses::total 44746 # number of overall misses
531system.cpu.icache.ReadReq_miss_latency::cpu.inst 897678738 # number of ReadReq miss cycles
532system.cpu.icache.ReadReq_miss_latency::total 897678738 # number of ReadReq miss cycles
533system.cpu.icache.demand_miss_latency::cpu.inst 897678738 # number of demand (read+write) miss cycles
534system.cpu.icache.demand_miss_latency::total 897678738 # number of demand (read+write) miss cycles
535system.cpu.icache.overall_miss_latency::cpu.inst 897678738 # number of overall miss cycles
536system.cpu.icache.overall_miss_latency::total 897678738 # number of overall miss cycles
537system.cpu.icache.ReadReq_accesses::cpu.inst 25127183 # number of ReadReq accesses(hits+misses)
538system.cpu.icache.ReadReq_accesses::total 25127183 # number of ReadReq accesses(hits+misses)
539system.cpu.icache.demand_accesses::cpu.inst 25127183 # number of demand (read+write) accesses
540system.cpu.icache.demand_accesses::total 25127183 # number of demand (read+write) accesses
541system.cpu.icache.overall_accesses::cpu.inst 25127183 # number of overall (read+write) accesses
542system.cpu.icache.overall_accesses::total 25127183 # number of overall (read+write) accesses
543system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001781 # miss rate for ReadReq accesses
544system.cpu.icache.ReadReq_miss_rate::total 0.001781 # miss rate for ReadReq accesses
545system.cpu.icache.demand_miss_rate::cpu.inst 0.001781 # miss rate for demand accesses
546system.cpu.icache.demand_miss_rate::total 0.001781 # miss rate for demand accesses
547system.cpu.icache.overall_miss_rate::cpu.inst 0.001781 # miss rate for overall accesses
548system.cpu.icache.overall_miss_rate::total 0.001781 # miss rate for overall accesses
549system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20061.653287 # average ReadReq miss latency
550system.cpu.icache.ReadReq_avg_miss_latency::total 20061.653287 # average ReadReq miss latency
551system.cpu.icache.demand_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency
552system.cpu.icache.demand_avg_miss_latency::total 20061.653287 # average overall miss latency
553system.cpu.icache.overall_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency
554system.cpu.icache.overall_avg_miss_latency::total 20061.653287 # average overall miss latency
555system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
556system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
557system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
558system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
559system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
560system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
561system.cpu.icache.fast_writes 0 # number of fast writes performed
562system.cpu.icache.cache_copies 0 # number of cache copies performed
563system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44746 # number of ReadReq MSHR misses
564system.cpu.icache.ReadReq_mshr_misses::total 44746 # number of ReadReq MSHR misses
565system.cpu.icache.demand_mshr_misses::cpu.inst 44746 # number of demand (read+write) MSHR misses
566system.cpu.icache.demand_mshr_misses::total 44746 # number of demand (read+write) MSHR misses
567system.cpu.icache.overall_mshr_misses::cpu.inst 44746 # number of overall MSHR misses
568system.cpu.icache.overall_mshr_misses::total 44746 # number of overall MSHR misses
569system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 806263262 # number of ReadReq MSHR miss cycles
570system.cpu.icache.ReadReq_mshr_miss_latency::total 806263262 # number of ReadReq MSHR miss cycles
571system.cpu.icache.demand_mshr_miss_latency::cpu.inst 806263262 # number of demand (read+write) MSHR miss cycles
572system.cpu.icache.demand_mshr_miss_latency::total 806263262 # number of demand (read+write) MSHR miss cycles
573system.cpu.icache.overall_mshr_miss_latency::cpu.inst 806263262 # number of overall MSHR miss cycles
574system.cpu.icache.overall_mshr_miss_latency::total 806263262 # number of overall MSHR miss cycles
575system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for ReadReq accesses
576system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001781 # mshr miss rate for ReadReq accesses
577system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for demand accesses
578system.cpu.icache.demand_mshr_miss_rate::total 0.001781 # mshr miss rate for demand accesses
579system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for overall accesses
580system.cpu.icache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses
581system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18018.666741 # average ReadReq mshr miss latency
582system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18018.666741 # average ReadReq mshr miss latency
583system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency
584system.cpu.icache.demand_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency
585system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency
586system.cpu.icache.overall_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency
587system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
588system.cpu.l2cache.tags.replacements 95732 # number of replacements
589system.cpu.l2cache.tags.tagsinuse 29937.969910 # Cycle average of tags in use
590system.cpu.l2cache.tags.total_refs 99708 # Total number of references to valid blocks.
591system.cpu.l2cache.tags.sampled_refs 126850 # Sample count of references to valid blocks.
592system.cpu.l2cache.tags.avg_refs 0.786031 # Average number of references to valid blocks.
593system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
594system.cpu.l2cache.tags.occ_blocks::writebacks 26706.762922 # Average occupied blocks per requestor
595system.cpu.l2cache.tags.occ_blocks::cpu.inst 3231.206988 # Average occupied blocks per requestor
596system.cpu.l2cache.tags.occ_percent::writebacks 0.815026 # Average percentage of cache occupancy
597system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098609 # Average percentage of cache occupancy
598system.cpu.l2cache.tags.occ_percent::total 0.913634 # Average percentage of cache occupancy
599system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
600system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
601system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1136 # Occupied blocks per task id
602system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9726 # Occupied blocks per task id
603system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19542 # Occupied blocks per task id
604system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id
605system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
606system.cpu.l2cache.tags.tag_accesses 2903460 # Number of tag accesses
607system.cpu.l2cache.tags.data_accesses 2903460 # Number of data accesses
608system.cpu.l2cache.ReadReq_hits::cpu.inst 71567 # number of ReadReq hits
609system.cpu.l2cache.ReadReq_hits::total 71567 # number of ReadReq hits
610system.cpu.l2cache.Writeback_hits::writebacks 128433 # number of Writeback hits
611system.cpu.l2cache.Writeback_hits::total 128433 # number of Writeback hits
612system.cpu.l2cache.ReadExReq_hits::cpu.inst 4753 # number of ReadExReq hits
613system.cpu.l2cache.ReadExReq_hits::total 4753 # number of ReadExReq hits
614system.cpu.l2cache.demand_hits::cpu.inst 76320 # number of demand (read+write) hits
615system.cpu.l2cache.demand_hits::total 76320 # number of demand (read+write) hits
616system.cpu.l2cache.overall_hits::cpu.inst 76320 # number of overall hits
617system.cpu.l2cache.overall_hits::total 76320 # number of overall hits
618system.cpu.l2cache.ReadReq_misses::cpu.inst 26663 # number of ReadReq misses
619system.cpu.l2cache.ReadReq_misses::total 26663 # number of ReadReq misses
620system.cpu.l2cache.ReadExReq_misses::cpu.inst 102281 # number of ReadExReq misses
621system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses
622system.cpu.l2cache.demand_misses::cpu.inst 128944 # number of demand (read+write) misses
623system.cpu.l2cache.demand_misses::total 128944 # number of demand (read+write) misses
624system.cpu.l2cache.overall_misses::cpu.inst 128944 # number of overall misses
625system.cpu.l2cache.overall_misses::total 128944 # number of overall misses
626system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1987300500 # number of ReadReq miss cycles
627system.cpu.l2cache.ReadReq_miss_latency::total 1987300500 # number of ReadReq miss cycles
628system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7479393750 # number of ReadExReq miss cycles
629system.cpu.l2cache.ReadExReq_miss_latency::total 7479393750 # number of ReadExReq miss cycles
630system.cpu.l2cache.demand_miss_latency::cpu.inst 9466694250 # number of demand (read+write) miss cycles
631system.cpu.l2cache.demand_miss_latency::total 9466694250 # number of demand (read+write) miss cycles
632system.cpu.l2cache.overall_miss_latency::cpu.inst 9466694250 # number of overall miss cycles
633system.cpu.l2cache.overall_miss_latency::total 9466694250 # number of overall miss cycles
634system.cpu.l2cache.ReadReq_accesses::cpu.inst 98230 # number of ReadReq accesses(hits+misses)
635system.cpu.l2cache.ReadReq_accesses::total 98230 # number of ReadReq accesses(hits+misses)
636system.cpu.l2cache.Writeback_accesses::writebacks 128433 # number of Writeback accesses(hits+misses)
637system.cpu.l2cache.Writeback_accesses::total 128433 # number of Writeback accesses(hits+misses)
638system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107034 # number of ReadExReq accesses(hits+misses)
639system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
640system.cpu.l2cache.demand_accesses::cpu.inst 205264 # number of demand (read+write) accesses
641system.cpu.l2cache.demand_accesses::total 205264 # number of demand (read+write) accesses
642system.cpu.l2cache.overall_accesses::cpu.inst 205264 # number of overall (read+write) accesses
643system.cpu.l2cache.overall_accesses::total 205264 # number of overall (read+write) accesses
644system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271434 # miss rate for ReadReq accesses
645system.cpu.l2cache.ReadReq_miss_rate::total 0.271434 # miss rate for ReadReq accesses
646system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955594 # miss rate for ReadExReq accesses
647system.cpu.l2cache.ReadExReq_miss_rate::total 0.955594 # miss rate for ReadExReq accesses
648system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628186 # miss rate for demand accesses
649system.cpu.l2cache.demand_miss_rate::total 0.628186 # miss rate for demand accesses
650system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628186 # miss rate for overall accesses
651system.cpu.l2cache.overall_miss_rate::total 0.628186 # miss rate for overall accesses
652system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74534.017177 # average ReadReq miss latency
653system.cpu.l2cache.ReadReq_avg_miss_latency::total 74534.017177 # average ReadReq miss latency
654system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73125.934924 # average ReadExReq miss latency
655system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73125.934924 # average ReadExReq miss latency
656system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency
657system.cpu.l2cache.demand_avg_miss_latency::total 73417.097732 # average overall miss latency
658system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency
659system.cpu.l2cache.overall_avg_miss_latency::total 73417.097732 # average overall miss latency
660system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
661system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
662system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
663system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
664system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
665system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
666system.cpu.l2cache.fast_writes 0 # number of fast writes performed
667system.cpu.l2cache.cache_copies 0 # number of cache copies performed
668system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks
669system.cpu.l2cache.writebacks::total 83951 # number of writebacks
670system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
671system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
672system.cpu.l2cache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
673system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
674system.cpu.l2cache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
675system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
676system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26590 # number of ReadReq MSHR misses
677system.cpu.l2cache.ReadReq_mshr_misses::total 26590 # number of ReadReq MSHR misses
678system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102281 # number of ReadExReq MSHR misses
679system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses
680system.cpu.l2cache.demand_mshr_misses::cpu.inst 128871 # number of demand (read+write) MSHR misses
681system.cpu.l2cache.demand_mshr_misses::total 128871 # number of demand (read+write) MSHR misses
682system.cpu.l2cache.overall_mshr_misses::cpu.inst 128871 # number of overall MSHR misses
683system.cpu.l2cache.overall_mshr_misses::total 128871 # number of overall MSHR misses
684system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1644904750 # number of ReadReq MSHR miss cycles
685system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1644904750 # number of ReadReq MSHR miss cycles
686system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6188348750 # number of ReadExReq MSHR miss cycles
687system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6188348750 # number of ReadExReq MSHR miss cycles
688system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7833253500 # number of demand (read+write) MSHR miss cycles
689system.cpu.l2cache.demand_mshr_miss_latency::total 7833253500 # number of demand (read+write) MSHR miss cycles
690system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7833253500 # number of overall MSHR miss cycles
691system.cpu.l2cache.overall_mshr_miss_latency::total 7833253500 # number of overall MSHR miss cycles
692system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270691 # mshr miss rate for ReadReq accesses
693system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270691 # mshr miss rate for ReadReq accesses
694system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955594 # mshr miss rate for ReadExReq accesses
695system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955594 # mshr miss rate for ReadExReq accesses
696system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for demand accesses
697system.cpu.l2cache.demand_mshr_miss_rate::total 0.627831 # mshr miss rate for demand accesses
698system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for overall accesses
699system.cpu.l2cache.overall_mshr_miss_rate::total 0.627831 # mshr miss rate for overall accesses
700system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61861.780745 # average ReadReq mshr miss latency
701system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61861.780745 # average ReadReq mshr miss latency
702system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60503.404836 # average ReadExReq mshr miss latency
703system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60503.404836 # average ReadExReq mshr miss latency
704system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency
705system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency
706system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency
707system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency
708system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
709system.cpu.toL2Bus.trans_dist::ReadReq 98230 # Transaction distribution
710system.cpu.toL2Bus.trans_dist::ReadResp 98229 # Transaction distribution
711system.cpu.toL2Bus.trans_dist::Writeback 128433 # Transaction distribution
712system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
713system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
714system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89491 # Packet count per connected master and slave (bytes)
715system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449469 # Packet count per connected master and slave (bytes)
716system.cpu.toL2Bus.pkt_count::total 538960 # Packet count per connected master and slave (bytes)
717system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2863680 # Cumulative packet size per connected master and slave (bytes)
718system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492864 # Cumulative packet size per connected master and slave (bytes)
719system.cpu.toL2Bus.pkt_size::total 21356544 # Cumulative packet size per connected master and slave (bytes)
720system.cpu.toL2Bus.snoops 0 # Total snoops (count)
721system.cpu.toL2Bus.snoop_fanout::samples 333697 # Request fanout histogram
722system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
723system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
724system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
725system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
726system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
727system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
728system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
729system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
730system.cpu.toL2Bus.snoop_fanout::5 333697 100.00% 100.00% # Request fanout histogram
731system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
732system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
733system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
734system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
735system.cpu.toL2Bus.snoop_fanout::total 333697 # Request fanout histogram
736system.cpu.toL2Bus.reqLayer0.occupancy 295281500 # Layer occupancy (ticks)
737system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
738system.cpu.toL2Bus.respLayer0.occupancy 68080238 # Layer occupancy (ticks)
739system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
740system.cpu.toL2Bus.respLayer1.occupancy 268447937 # Layer occupancy (ticks)
741system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
742system.membus.trans_dist::ReadReq 26589 # Transaction distribution
743system.membus.trans_dist::ReadResp 26589 # Transaction distribution
744system.membus.trans_dist::Writeback 83951 # Transaction distribution
745system.membus.trans_dist::ReadExReq 102281 # Transaction distribution
746system.membus.trans_dist::ReadExResp 102281 # Transaction distribution
747system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341691 # Packet count per connected master and slave (bytes)
748system.membus.pkt_count::total 341691 # Packet count per connected master and slave (bytes)
749system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620544 # Cumulative packet size per connected master and slave (bytes)
750system.membus.pkt_size::total 13620544 # Cumulative packet size per connected master and slave (bytes)
751system.membus.snoops 0 # Total snoops (count)
752system.membus.snoop_fanout::samples 212821 # Request fanout histogram
753system.membus.snoop_fanout::mean 0 # Request fanout histogram
754system.membus.snoop_fanout::stdev 0 # Request fanout histogram
755system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
756system.membus.snoop_fanout::0 212821 100.00% 100.00% # Request fanout histogram
757system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
758system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
759system.membus.snoop_fanout::min_value 0 # Request fanout histogram
760system.membus.snoop_fanout::max_value 0 # Request fanout histogram
761system.membus.snoop_fanout::total 212821 # Request fanout histogram
762system.membus.reqLayer0.occupancy 929388500 # Layer occupancy (ticks)
763system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
764system.membus.respLayer1.occupancy 1213397000 # Layer occupancy (ticks)
765system.membus.respLayer1.utilization 2.1 # Layer utilization (%)
766
767---------- End Simulation Statistics ----------