| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 137 unchanged lines hidden (view full) --- 146localHistoryTableSize=2048 147localPredictorSize=2048 148numThreads=1 149useIndirect=true 150 151[system.cpu.dcache] 152type=Cache 153children=tags | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 137 unchanged lines hidden (view full) --- 146localHistoryTableSize=2048 147localPredictorSize=2048 148numThreads=1 149useIndirect=true 150 151[system.cpu.dcache] 152type=Cache 153children=tags |
| 154addr_ranges=0:18446744073709551615 | 154addr_ranges=0:18446744073709551615:0:0:0:0 |
| 155assoc=2 156clk_domain=system.cpu_clk_domain 157clusivity=mostly_incl 158default_p_state=UNDEFINED 159demand_mshr_reserve=1 160eventq_index=0 161hit_latency=2 162is_read_only=false --- 463 unchanged lines hidden (view full) --- 626[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] 627type=MinorOpClass 628eventq_index=0 629opClass=InstPrefetch 630 631[system.cpu.icache] 632type=Cache 633children=tags | 155assoc=2 156clk_domain=system.cpu_clk_domain 157clusivity=mostly_incl 158default_p_state=UNDEFINED 159demand_mshr_reserve=1 160eventq_index=0 161hit_latency=2 162is_read_only=false --- 463 unchanged lines hidden (view full) --- 626[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] 627type=MinorOpClass 628eventq_index=0 629opClass=InstPrefetch 630 631[system.cpu.icache] 632type=Cache 633children=tags |
| 634addr_ranges=0:18446744073709551615 | 634addr_ranges=0:18446744073709551615:0:0:0:0 |
| 635assoc=2 636clk_domain=system.cpu_clk_domain 637clusivity=mostly_incl 638default_p_state=UNDEFINED 639demand_mshr_reserve=1 640eventq_index=0 641hit_latency=2 642is_read_only=true --- 43 unchanged lines hidden (view full) --- 686id_aa64afr0_el1=0 687id_aa64afr1_el1=0 688id_aa64dfr0_el1=1052678 689id_aa64dfr1_el1=0 690id_aa64isar0_el1=0 691id_aa64isar1_el1=0 692id_aa64mmfr0_el1=15728642 693id_aa64mmfr1_el1=0 | 635assoc=2 636clk_domain=system.cpu_clk_domain 637clusivity=mostly_incl 638default_p_state=UNDEFINED 639demand_mshr_reserve=1 640eventq_index=0 641hit_latency=2 642is_read_only=true --- 43 unchanged lines hidden (view full) --- 686id_aa64afr0_el1=0 687id_aa64afr1_el1=0 688id_aa64dfr0_el1=1052678 689id_aa64dfr1_el1=0 690id_aa64isar0_el1=0 691id_aa64isar1_el1=0 692id_aa64mmfr0_el1=15728642 693id_aa64mmfr1_el1=0 |
| 694id_aa64pfr0_el1=17 | 694id_aa64pfr0_el1=34 |
| 695id_aa64pfr1_el1=0 696id_isar0=34607377 697id_isar1=34677009 698id_isar2=555950401 699id_isar3=17899825 700id_isar4=268501314 701id_isar5=0 702id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 758p_state_clk_gate_min=1000 759power_model=Null 760sys=system 761port=system.cpu.toL2Bus.slave[2] 762 763[system.cpu.l2cache] 764type=Cache 765children=tags | 695id_aa64pfr1_el1=0 696id_isar0=34607377 697id_isar1=34677009 698id_isar2=555950401 699id_isar3=17899825 700id_isar4=268501314 701id_isar5=0 702id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 758p_state_clk_gate_min=1000 759power_model=Null 760sys=system 761port=system.cpu.toL2Bus.slave[2] 762 763[system.cpu.l2cache] 764type=Cache 765children=tags |
| 766addr_ranges=0:18446744073709551615 | 766addr_ranges=0:18446744073709551615:0:0:0:0 |
| 767assoc=8 768clk_domain=system.cpu_clk_domain 769clusivity=mostly_incl 770default_p_state=UNDEFINED 771demand_mshr_reserve=1 772eventq_index=0 773hit_latency=20 774is_read_only=false --- 100 unchanged lines hidden (view full) --- 875domains= 876enable=false 877eventq_index=0 878sys_clk_domain=system.clk_domain 879transition_latency=100000000 880 881[system.membus] 882type=CoherentXBar | 767assoc=8 768clk_domain=system.cpu_clk_domain 769clusivity=mostly_incl 770default_p_state=UNDEFINED 771demand_mshr_reserve=1 772eventq_index=0 773hit_latency=20 774is_read_only=false --- 100 unchanged lines hidden (view full) --- 875domains= 876enable=false 877eventq_index=0 878sys_clk_domain=system.clk_domain 879transition_latency=100000000 880 881[system.membus] 882type=CoherentXBar |
| 883children=snoop_filter |
|
| 883clk_domain=system.clk_domain 884default_p_state=UNDEFINED 885eventq_index=0 886forward_latency=4 887frontend_latency=3 888p_state_clk_gate_bins=20 889p_state_clk_gate_max=1000000000000 890p_state_clk_gate_min=1000 891point_of_coherency=true 892power_model=Null 893response_latency=2 | 884clk_domain=system.clk_domain 885default_p_state=UNDEFINED 886eventq_index=0 887forward_latency=4 888frontend_latency=3 889p_state_clk_gate_bins=20 890p_state_clk_gate_max=1000000000000 891p_state_clk_gate_min=1000 892point_of_coherency=true 893power_model=Null 894response_latency=2 |
| 894snoop_filter=Null | 895snoop_filter=system.membus.snoop_filter |
| 895snoop_response_latency=4 896system=system 897use_default_range=false 898width=16 899master=system.physmem.port 900slave=system.system_port system.cpu.l2cache.mem_side 901 | 896snoop_response_latency=4 897system=system 898use_default_range=false 899width=16 900master=system.physmem.port 901slave=system.system_port system.cpu.l2cache.mem_side 902 |
| 903[system.membus.snoop_filter] 904type=SnoopFilter 905eventq_index=0 906lookup_latency=1 907max_capacity=8388608 908system=system 909 |
|
| 902[system.physmem] 903type=DRAMCtrl | 910[system.physmem] 911type=DRAMCtrl |
| 904IDD0=0.075000 | 912IDD0=0.055000 |
| 905IDD02=0.000000 | 913IDD02=0.000000 |
| 906IDD2N=0.050000 | 914IDD2N=0.032000 |
| 907IDD2N2=0.000000 908IDD2P0=0.000000 909IDD2P02=0.000000 | 915IDD2N2=0.000000 916IDD2P0=0.000000 917IDD2P02=0.000000 |
| 910IDD2P1=0.000000 | 918IDD2P1=0.032000 |
| 911IDD2P12=0.000000 | 919IDD2P12=0.000000 |
| 912IDD3N=0.057000 | 920IDD3N=0.038000 |
| 913IDD3N2=0.000000 914IDD3P0=0.000000 915IDD3P02=0.000000 | 921IDD3N2=0.000000 922IDD3P0=0.000000 923IDD3P02=0.000000 |
| 916IDD3P1=0.000000 | 924IDD3P1=0.038000 |
| 917IDD3P12=0.000000 | 925IDD3P12=0.000000 |
| 918IDD4R=0.187000 | 926IDD4R=0.157000 |
| 919IDD4R2=0.000000 | 927IDD4R2=0.000000 |
| 920IDD4W=0.165000 | 928IDD4W=0.125000 |
| 921IDD4W2=0.000000 | 929IDD4W2=0.000000 |
| 922IDD5=0.220000 | 930IDD5=0.235000 |
| 923IDD52=0.000000 | 931IDD52=0.000000 |
| 924IDD6=0.000000 | 932IDD6=0.020000 |
| 925IDD62=0.000000 926VDD=1.500000 927VDD2=0.000000 928activation_limit=4 929addr_mapping=RoRaBaCoCh 930bank_groups_per_rank=0 931banks_per_rank=8 932burst_length=8 933channels=1 934clk_domain=system.clk_domain 935conf_table_reported=true 936default_p_state=UNDEFINED 937device_bus_width=8 938device_rowbuffer_size=1024 939device_size=536870912 940devices_per_rank=8 941dll=true 942eventq_index=0 943in_addr_map=true | 933IDD62=0.000000 934VDD=1.500000 935VDD2=0.000000 936activation_limit=4 937addr_mapping=RoRaBaCoCh 938bank_groups_per_rank=0 939banks_per_rank=8 940burst_length=8 941channels=1 942clk_domain=system.clk_domain 943conf_table_reported=true 944default_p_state=UNDEFINED 945device_bus_width=8 946device_rowbuffer_size=1024 947device_size=536870912 948devices_per_rank=8 949dll=true 950eventq_index=0 951in_addr_map=true |
| 952kvm_map=true |
|
| 944max_accesses_per_row=16 945mem_sched_policy=frfcfs 946min_writes_per_switch=16 947null=false 948p_state_clk_gate_bins=20 949p_state_clk_gate_max=1000000000000 950p_state_clk_gate_min=1000 951page_policy=open_adaptive 952power_model=Null | 953max_accesses_per_row=16 954mem_sched_policy=frfcfs 955min_writes_per_switch=16 956null=false 957p_state_clk_gate_bins=20 958p_state_clk_gate_max=1000000000000 959p_state_clk_gate_min=1000 960page_policy=open_adaptive 961power_model=Null |
| 953range=0:134217727 | 962range=0:134217727:0:0:0:0 |
| 954ranks_per_channel=2 955read_buffer_size=32 956static_backend_latency=10000 957static_frontend_latency=10000 958tBURST=5000 959tCCD_L=0 960tCK=1250 961tCL=13750 --- 5 unchanged lines hidden (view full) --- 967tRP=13750 968tRRD=6000 969tRRD_L=0 970tRTP=7500 971tRTW=2500 972tWR=15000 973tWTR=7500 974tXAW=30000 | 963ranks_per_channel=2 964read_buffer_size=32 965static_backend_latency=10000 966static_frontend_latency=10000 967tBURST=5000 968tCCD_L=0 969tCK=1250 970tCL=13750 --- 5 unchanged lines hidden (view full) --- 976tRP=13750 977tRRD=6000 978tRRD_L=0 979tRTP=7500 980tRTW=2500 981tWR=15000 982tWTR=7500 983tXAW=30000 |
| 975tXP=0 | 984tXP=6000 |
| 976tXPDLL=0 | 985tXPDLL=0 |
| 977tXS=0 | 986tXS=270000 |
| 978tXSDLL=0 979write_buffer_size=64 980write_high_thresh_perc=85 981write_low_thresh_perc=50 982port=system.membus.master[0] 983 984[system.voltage_domain] 985type=VoltageDomain 986eventq_index=0 987voltage=1.000000 988 | 987tXSDLL=0 988write_buffer_size=64 989write_high_thresh_perc=85 990write_low_thresh_perc=50 991port=system.membus.master[0] 992 993[system.voltage_domain] 994type=VoltageDomain 995eventq_index=0 996voltage=1.000000 997 |