Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 1.045756 # Number of seconds simulated
4sim_ticks 1045756396500 # Number of ticks simulated
5final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 1.046047 # Number of seconds simulated
4sim_ticks 1046047111500 # Number of ticks simulated
5final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 546786 # Simulator instruction rate (inst/s)
8host_op_rate 671760 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 894330624 # Simulator tick rate (ticks/s)
10host_mem_usage 273552 # Number of bytes of host memory used
11host_seconds 1169.32 # Real time elapsed on the host

7host_inst_rate 666714 # Simulator instruction rate (inst/s)
8host_op_rate 819099 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1090788712 # Simulator tick rate (ticks/s)
10host_mem_usage 278188 # Number of bytes of host memory used
11host_seconds 958.98 # Real time elapsed on the host

12sim_insts 639366787 # Number of instructions simulated
13sim_ops 785501035 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory
19system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory
19system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory

20system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
23system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory

25system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory

25system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory

27system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory

29system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

29system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

41system.cpu_clk_domain.clock 500 # Clock period in ticks

42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

73system.cpu.dtb.walker.walks 0 # Table walker walks requested
74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
96system.cpu.dtb.read_accesses 0 # DTB read accesses
97system.cpu.dtb.write_accesses 0 # DTB write accesses
98system.cpu.dtb.inst_accesses 0 # ITB inst accesses
99system.cpu.dtb.hits 0 # DTB hits
100system.cpu.dtb.misses 0 # DTB misses
101system.cpu.dtb.accesses 0 # DTB accesses

102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

133system.cpu.itb.walker.walks 0 # Table walker walks requested
134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
156system.cpu.itb.read_accesses 0 # DTB read accesses
157system.cpu.itb.write_accesses 0 # DTB write accesses
158system.cpu.itb.inst_accesses 0 # ITB inst accesses
159system.cpu.itb.hits 0 # DTB hits
160system.cpu.itb.misses 0 # DTB misses
161system.cpu.itb.accesses 0 # DTB accesses
162system.cpu.workload.num_syscalls 673 # Number of system calls

163system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states
164system.cpu.numCycles 2091512793 # number of cpu cycles simulated

163system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states
164system.cpu.numCycles 2092094223 # number of cpu cycles simulated

165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
167system.cpu.committedInsts 639366787 # Number of instructions committed
168system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed
169system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
170system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
171system.cpu.num_func_calls 37261296 # number of times a function call or return occured
172system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

177system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
178system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
179system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read
180system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
181system.cpu.num_mem_refs 381221435 # number of memory refs
182system.cpu.num_load_insts 252240938 # Number of load instructions
183system.cpu.num_store_insts 128980497 # Number of store instructions
184system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

185system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles

185system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles

186system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
187system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
188system.cpu.Branches 137364860 # Number of branches fetched
189system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
190system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
191system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
192system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
193system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction

--- 22 unchanged lines hidden (view full) ---

216system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
217system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
218system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
219system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
220system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
221system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
222system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
223system.cpu.op_class::total 788730744 # Class of executed instruction

224system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

224system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

225system.cpu.dcache.tags.replacements 778046 # number of replacements

226system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use

226system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use

227system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
228system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
229system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.

230system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit.
231system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor
232system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy
233system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy

230system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit.
231system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor
232system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy
233system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy

234system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
235system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
236system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
237system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id
238system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id
239system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id
240system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
241system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses
242system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses

243system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

243system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

244system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits
245system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits
246system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits
247system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits
248system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits
249system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits
250system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
251system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits

--- 8 unchanged lines hidden (view full) ---

260system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses
261system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses
262system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses
263system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses
264system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses
265system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
266system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
267system.cpu.dcache.overall_misses::total 782143 # number of overall misses

268system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles
269system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles
270system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles
271system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles
272system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles
273system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles
274system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles
275system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles

268system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles
269system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles
270system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles
271system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles
272system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles
273system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles
274system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles
275system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles

276system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
277system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
278system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
279system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
280system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses)
281system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses)
282system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
283system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

292system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses
293system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses
294system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses
295system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses
296system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses
297system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
298system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
299system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses

300system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency
301system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency
302system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency
303system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency
304system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency
305system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency
306system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency
307system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency

300system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency
301system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency
302system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency
303system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency
304system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency
305system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency
306system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency
307system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency

308system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
309system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
310system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
311system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
312system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
313system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

314system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks
315system.cpu.dcache.writebacks::total 88995 # number of writebacks

314system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks
315system.cpu.dcache.writebacks::total 88967 # number of writebacks

316system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
317system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
318system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
319system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
320system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
321system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
322system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses
323system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses
324system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses
325system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
326system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
327system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
328system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses
329system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
330system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
331system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses

332system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles
333system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles
334system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles
335system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles
336system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles
337system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles
338system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles
339system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles
340system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles
341system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles

332system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles
333system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles
334system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles
335system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles
336system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles
337system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles
338system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles
339system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles
340system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles
341system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles

342system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
343system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
344system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
345system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
346system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses
347system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses
348system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
349system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
350system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
351system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses

352system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency
353system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency
354system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency
355system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency
356system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency
357system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency
358system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency
359system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
360system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
361system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
362system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

352system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency
353system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency
354system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency
355system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency
356system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency
357system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency
358system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency
359system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency
360system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency
361system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency
362system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

363system.cpu.icache.tags.replacements 8769 # number of replacements

364system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use

364system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use

365system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
366system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
367system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks.
368system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

369system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor
370system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy
371system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy

369system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor
370system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy
371system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy

372system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
373system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
374system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
375system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
376system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
377system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses
378system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses

379system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

379system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

380system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits
381system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits
382system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits
383system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits
384system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits
385system.cpu.icache.overall_hits::total 643367692 # number of overall hits
386system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
387system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
388system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
389system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
390system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
391system.cpu.icache.overall_misses::total 10208 # number of overall misses

392system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles
393system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles
394system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles
395system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles
396system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles
397system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles

392system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles
393system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles
394system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles
395system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles
396system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles
397system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles

398system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses)
399system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses)
400system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses
401system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses
402system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses
403system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses
404system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
405system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
406system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
407system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
408system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
409system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses

410system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency
411system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency
412system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
413system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency
414system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
415system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency

410system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency
411system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency
412system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency
413system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency
414system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency
415system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency

416system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
417system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
418system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
419system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
420system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
421system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
422system.cpu.icache.writebacks::writebacks 8769 # number of writebacks
423system.cpu.icache.writebacks::total 8769 # number of writebacks
424system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses
425system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses
426system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses
427system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
428system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
429system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses

430system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles
431system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles
432system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles
433system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles
434system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles
435system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles

430system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210621500 # number of ReadReq MSHR miss cycles
431system.cpu.icache.ReadReq_mshr_miss_latency::total 210621500 # number of ReadReq MSHR miss cycles
432system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210621500 # number of demand (read+write) MSHR miss cycles
433system.cpu.icache.demand_mshr_miss_latency::total 210621500 # number of demand (read+write) MSHR miss cycles
434system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210621500 # number of overall MSHR miss cycles
435system.cpu.icache.overall_mshr_miss_latency::total 210621500 # number of overall MSHR miss cycles

436system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
437system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
438system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
439system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
440system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
441system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses

442system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency
443system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency
444system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
445system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
446system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
447system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
448system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
449system.cpu.l2cache.tags.replacements 257772 # number of replacements
450system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
451system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
452system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks.
453system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks.
454system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
455system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor
456system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor
457system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor
458system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy
459system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy
460system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy
461system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy
462system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id

442system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20632.983934 # average ReadReq mshr miss latency
443system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20632.983934 # average ReadReq mshr miss latency
444system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency
445system.cpu.icache.demand_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency
446system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency
447system.cpu.icache.overall_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency
448system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
449system.cpu.l2cache.tags.replacements 257791 # number of replacements
450system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use
451system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks.
452system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks.
453system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks.
454system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit.
455system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor
456system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor
457system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor
458system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy
459system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy
460system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy
461system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy
462system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id

463system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id

464system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id

464system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id

465system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id
466system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id

467system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id
468system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
469system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses
470system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses
471system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
472system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits
473system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits

467system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id
468system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
469system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses
470system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses
471system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
472system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits
473system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits

474system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits
475system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits
476system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits
477system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits
478system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits
479system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits

480system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits
481system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits

480system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490296 # number of ReadSharedReq hits
481system.cpu.l2cache.ReadSharedReq_hits::total 490296 # number of ReadSharedReq hits

482system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits

483system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits
484system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits

483system.cpu.l2cache.demand_hits::cpu.data 493526 # number of demand (read+write) hits
484system.cpu.l2cache.demand_hits::total 501975 # number of demand (read+write) hits

485system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits

486system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits
487system.cpu.l2cache.overall_hits::total 501982 # number of overall hits

486system.cpu.l2cache.overall_hits::cpu.data 493526 # number of overall hits
487system.cpu.l2cache.overall_hits::total 501975 # number of overall hits

488system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses
489system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses
490system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses
491system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses

492system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses
493system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses

492system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222523 # number of ReadSharedReq misses
493system.cpu.l2cache.ReadSharedReq_misses::total 222523 # number of ReadSharedReq misses

494system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses

495system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses
496system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses

495system.cpu.l2cache.demand_misses::cpu.data 288616 # number of demand (read+write) misses
496system.cpu.l2cache.demand_misses::total 290375 # number of demand (read+write) misses

497system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses

498system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses
499system.cpu.l2cache.overall_misses::total 290368 # number of overall misses
500system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles
501system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles
502system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles
503system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles
504system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles
505system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles
506system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles
507system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles
508system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles
509system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles
510system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles
511system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles
512system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses)
513system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses)

498system.cpu.l2cache.overall_misses::cpu.data 288616 # number of overall misses
499system.cpu.l2cache.overall_misses::total 290375 # number of overall misses
500system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500 # number of ReadExReq miss cycles
501system.cpu.l2cache.ReadExReq_miss_latency::total 3998679500 # number of ReadExReq miss cycles
502system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles
503system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles
504system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles
505system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles
506system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles
507system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles
508system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles
509system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles
510system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles
511system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles
512system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses)
513system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses)

514system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses)
515system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses)
516system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses)
517system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses)
518system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses)
519system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses)
520system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses)
521system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses)
522system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses
523system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses
524system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses
525system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses
526system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses
527system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses
528system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses
529system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses
530system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses
531system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses

532system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses
533system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses

532system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses
533system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses

534system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses

535system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses
536system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses

535system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses
536system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses

537system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses

538system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses
539system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses
540system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency
541system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency
542system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency
543system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency
544system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency
545system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency
546system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
547system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
548system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency
549system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
550system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
551system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency

538system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses
539system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses
540system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency
541system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency
542system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency
543system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency
544system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency
545system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency
546system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency
547system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency
548system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency
549system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency
550system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency
551system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency

552system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
553system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
554system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
555system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
556system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
557system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
558system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
559system.cpu.l2cache.writebacks::total 66098 # number of writebacks
560system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses
561system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses
562system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses
563system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses

564system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses
565system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses

564system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses
565system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses

566system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses

567system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses
568system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses

567system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses
568system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses

569system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses

570system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses
571system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses
572system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles
573system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles
574system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles
575system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles
576system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles
577system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles
578system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles
579system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles
580system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles
581system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles
582system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles
583system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles

570system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses
571system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses
572system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles
573system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles
574system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles
575system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles
576system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles
577system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles
578system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles
579system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles
580system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles
581system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles
582system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles
583system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles

584system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
585system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses
586system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses
587system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses

588system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses
589system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses

588system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses
589system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses

590system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses

591system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses
592system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses

591system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses
592system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses

593system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses

594system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses
595system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses
596system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency
597system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency
598system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency
599system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency
600system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency
601system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency
602system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
603system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
604system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
605system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
606system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
607system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency

594system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses
595system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses
596system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency
597system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency
598system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency
599system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency
600system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency
601system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency
602system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency
603system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency
604system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency
605system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency
606system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency
607system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency

608system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
609system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
610system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

611system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
612system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

611system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter.
612system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

613system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

614system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states

614system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states

615system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution

616system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution

616system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution

617system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution

618system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution

618system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution

619system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
620system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
621system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution
622system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution
623system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes)
624system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes)
625system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes)
626system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes)

627system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes)
628system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes)
629system.cpu.toL2Bus.snoops 257772 # Total snoops (count)

627system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes)
628system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes)
629system.cpu.toL2Bus.snoops 257791 # Total snoops (count)

630system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes)

631system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram
632system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram
633system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram

631system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram
632system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram
633system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram

634system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

635system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram
636system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram

635system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram
636system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram

637system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram
638system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
639system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
640system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

641system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram
642system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks)

641system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram
642system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks)

643system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
644system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
645system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
646system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
647system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)

648system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
649system.membus.trans_dist::ReadResp 224275 # Transaction distribution

648system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter.
649system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data.
650system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
651system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
652system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
653system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
654system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
655system.membus.trans_dist::ReadResp 224282 # Transaction distribution

650system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution

656system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution

651system.membus.trans_dist::CleanEvict 190094 # Transaction distribution

657system.membus.trans_dist::CleanEvict 190103 # Transaction distribution

652system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
653system.membus.trans_dist::ReadExResp 66093 # Transaction distribution

658system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
659system.membus.trans_dist::ReadExResp 66093 # Transaction distribution

654system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution
655system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes)
656system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes)
657system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes)
658system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes)

660system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution
661system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes)
662system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes)
663system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes)
664system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes)

659system.membus.snoops 0 # Total snoops (count)
660system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

665system.membus.snoops 0 # Total snoops (count)
666system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

661system.membus.snoop_fanout::samples 546561 # Request fanout histogram

667system.membus.snoop_fanout::samples 290376 # Request fanout histogram

662system.membus.snoop_fanout::mean 0 # Request fanout histogram
663system.membus.snoop_fanout::stdev 0 # Request fanout histogram
664system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

668system.membus.snoop_fanout::mean 0 # Request fanout histogram
669system.membus.snoop_fanout::stdev 0 # Request fanout histogram
670system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

665system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram

671system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram

666system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
667system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
668system.membus.snoop_fanout::min_value 0 # Request fanout histogram
669system.membus.snoop_fanout::max_value 0 # Request fanout histogram

672system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
673system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
674system.membus.snoop_fanout::min_value 0 # Request fanout histogram
675system.membus.snoop_fanout::max_value 0 # Request fanout histogram

670system.membus.snoop_fanout::total 546561 # Request fanout histogram
671system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks)

676system.membus.snoop_fanout::total 290376 # Request fanout histogram
677system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks)

672system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)

678system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)

673system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks)

679system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks)