| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.045756 # Number of seconds simulated 4sim_ticks 1045756396500 # Number of ticks simulated 5final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.045756 # Number of seconds simulated 4sim_ticks 1045756396500 # Number of ticks simulated 5final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 725560 # Simulator instruction rate (inst/s) 8host_op_rate 891395 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1186735876 # Simulator tick rate (ticks/s) 10host_mem_usage 325196 # Number of bytes of host memory used 11host_seconds 881.20 # Real time elapsed on the host | 7host_inst_rate 744148 # Simulator instruction rate (inst/s) 8host_op_rate 914231 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1217137628 # Simulator tick rate (ticks/s) 10host_mem_usage 277972 # Number of bytes of host memory used 11host_seconds 859.19 # Real time elapsed on the host |
| 12sim_insts 639366787 # Number of instructions simulated 13sim_ops 785501035 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory --- 277 unchanged lines hidden (view full) --- 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 639366787 # Number of instructions simulated 13sim_ops 785501035 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory --- 277 unchanged lines hidden (view full) --- 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 305system.cpu.dcache.fast_writes 0 # number of fast writes performed 306system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 307system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks 308system.cpu.dcache.writebacks::total 88995 # number of writebacks 309system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 310system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 311system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 312system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 313system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 314system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency 348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency 349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency 350system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency 351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency 352system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency 353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency 354system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency | 305system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks 306system.cpu.dcache.writebacks::total 88995 # number of writebacks 307system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 308system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 309system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 310system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 311system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 312system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits --- 32 unchanged lines hidden (view full) --- 345system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency 346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency 347system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency |
| 355system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 356system.cpu.icache.tags.replacements 8769 # number of replacements 357system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use 358system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. 359system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. 360system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. 361system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 362system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor 363system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 406system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency 407system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency 408system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 409system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 410system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 411system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 412system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 413system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 353system.cpu.icache.tags.replacements 8769 # number of replacements 354system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use 355system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. 356system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. 357system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. 358system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 359system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor 360system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 403system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency 404system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency 405system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 406system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 407system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 409system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 410system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 414system.cpu.icache.fast_writes 0 # number of fast writes performed 415system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 416system.cpu.icache.writebacks::writebacks 8769 # number of writebacks 417system.cpu.icache.writebacks::total 8769 # number of writebacks 418system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses 419system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses 420system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses 421system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses 422system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses 423system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 434system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 435system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 436system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency 437system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency 438system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency 439system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency 440system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency 441system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency | 411system.cpu.icache.writebacks::writebacks 8769 # number of writebacks 412system.cpu.icache.writebacks::total 8769 # number of writebacks 413system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses 414system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses 415system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses 416system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses 417system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses 418system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 429system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 430system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency 432system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency 434system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency 436system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency |
| 442system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 443system.cpu.l2cache.tags.replacements 257772 # number of replacements 444system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use 445system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. 446system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks. 447system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks. 448system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 449system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor 450system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 543system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency 544system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency 545system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 546system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 549system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 550system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 437system.cpu.l2cache.tags.replacements 257772 # number of replacements 438system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use 439system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. 440system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks. 441system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks. 442system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 443system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 537system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency 538system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency 539system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 542system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 544system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 551system.cpu.l2cache.fast_writes 0 # number of fast writes performed 552system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 553system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 554system.cpu.l2cache.writebacks::total 66098 # number of writebacks 555system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses 556system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses 557system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses 558system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses 559system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses 560system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses --- 34 unchanged lines hidden (view full) --- 595system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency 596system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency 597system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency 598system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency 599system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency 600system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency 601system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency 602system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency | 545system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 546system.cpu.l2cache.writebacks::total 66098 # number of writebacks 547system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses 548system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses 549system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses 550system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses 551system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses 552system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses --- 34 unchanged lines hidden (view full) --- 587system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency 588system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency 591system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency 594system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency |
| 603system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 604system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. 605system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. 606system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 607system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. 608system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 609system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 610system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution --- 57 unchanged lines hidden --- | 595system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. 596system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. 597system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 598system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. 599system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 600system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 601system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution --- 57 unchanged lines hidden --- |