Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 1.043722 # Number of seconds simulated
4sim_ticks 1043722398500 # Number of ticks simulated
5final_tick 1043722398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 1.043724 # Number of seconds simulated
4sim_ticks 1043723537500 # Number of ticks simulated
5final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 921530 # Simulator instruction rate (inst/s)
8host_op_rate 1132156 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1504334297 # Simulator tick rate (ticks/s)
10host_mem_usage 320916 # Number of bytes of host memory used
11host_seconds 693.81 # Real time elapsed on the host

7host_inst_rate 832063 # Simulator instruction rate (inst/s)
8host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1358287943 # Simulator tick rate (ticks/s)
10host_mem_usage 323064 # Number of bytes of host memory used
11host_seconds 768.41 # Real time elapsed on the host

12sim_insts 639366787 # Number of instructions simulated
13sim_ops 785501035 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 113216 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 18469760 # Number of bytes read from this memory
18system.physmem.bytes_read::total 18582976 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 113216 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 113216 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 1769 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 288590 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 290359 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s)

29system.physmem.bw_read::cpu.data 17696046 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 17804520 # Total read bandwidth from this memory (bytes/s)

29system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s)

31system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s)

33system.physmem.bw_write::writebacks 4053062 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 4053062 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 4053062 # Total bandwidth to/from this memory (bytes/s)

33system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s)

36system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.bw_total::cpu.data 17696046 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21857582 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s)

39system.cpu_clk_domain.clock 500 # Clock period in ticks
40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
150system.cpu.itb.read_accesses 0 # DTB read accesses
151system.cpu.itb.write_accesses 0 # DTB write accesses
152system.cpu.itb.inst_accesses 0 # ITB inst accesses
153system.cpu.itb.hits 0 # DTB hits
154system.cpu.itb.misses 0 # DTB misses
155system.cpu.itb.accesses 0 # DTB accesses
156system.cpu.workload.num_syscalls 673 # Number of system calls

157system.cpu.numCycles 2087444797 # number of cpu cycles simulated

157system.cpu.numCycles 2087447075 # number of cpu cycles simulated

158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 639366787 # Number of instructions committed
161system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
164system.cpu.num_func_calls 37261296 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

170system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
174system.cpu.num_mem_refs 381221435 # number of memory refs
175system.cpu.num_load_insts 252240938 # Number of load instructions
176system.cpu.num_store_insts 128980497 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

178system.cpu.num_busy_cycles 2087444796.998000 # Number of busy cycles

178system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles

179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 137364860 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
184system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction

--- 23 unchanged lines hidden (view full) ---

210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
212system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
213system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 788730744 # Class of executed instruction
217system.cpu.dcache.tags.replacements 778046 # number of replacements

218system.cpu.dcache.tags.tagsinuse 4093.640641 # Cycle average of tags in use

218system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use

219system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.

222system.cpu.dcache.tags.warmup_cycle 996416500 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640641 # Average occupied blocks per requestor

222system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor

224system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy
225system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
227system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id

--- 19 unchanged lines hidden (view full) ---

251system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses
252system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses
253system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses
254system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses
255system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses
256system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
257system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
258system.cpu.dcache.overall_misses::total 782143 # number of overall misses

259system.cpu.dcache.ReadReq_miss_latency::cpu.data 18609964000 # number of ReadReq miss cycles
260system.cpu.dcache.ReadReq_miss_latency::total 18609964000 # number of ReadReq miss cycles

259system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles
260system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles

261system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles
262system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles

263system.cpu.dcache.demand_miss_latency::cpu.data 22287133000 # number of demand (read+write) miss cycles
264system.cpu.dcache.demand_miss_latency::total 22287133000 # number of demand (read+write) miss cycles
265system.cpu.dcache.overall_miss_latency::cpu.data 22287133000 # number of overall miss cycles
266system.cpu.dcache.overall_miss_latency::total 22287133000 # number of overall miss cycles

263system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles
264system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles
265system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles
266system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles

267system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
268system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
269system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
270system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
271system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses)
272system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses)
273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
274system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses
284system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses
285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses
286system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses
287system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses
288system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
289system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
290system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses

291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199 # average ReadReq miss latency
292system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199 # average ReadReq miss latency

291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency
292system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency

293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency
294system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency

295system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297 # average overall miss latency
296system.cpu.dcache.demand_avg_miss_latency::total 28500.024297 # average overall miss latency
297system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362 # average overall miss latency
298system.cpu.dcache.overall_avg_miss_latency::total 28494.959362 # average overall miss latency

295system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency
296system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency
297system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency
298system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency

299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
305system.cpu.dcache.fast_writes 0 # number of fast writes performed
306system.cpu.dcache.cache_copies 0 # number of cache copies performed

--- 10 unchanged lines hidden (view full) ---

317system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses
318system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
319system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
320system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
321system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses
322system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
323system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
324system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses

325system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17897244000 # number of ReadReq MSHR miss cycles
326system.cpu.dcache.ReadReq_mshr_miss_latency::total 17897244000 # number of ReadReq MSHR miss cycles

325system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles
326system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles

327system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles
328system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles
329system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles
330system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles

331system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21505090000 # number of demand (read+write) MSHR miss cycles
332system.cpu.dcache.demand_mshr_miss_latency::total 21505090000 # number of demand (read+write) MSHR miss cycles
333system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21506842000 # number of overall MSHR miss cycles
334system.cpu.dcache.overall_mshr_miss_latency::total 21506842000 # number of overall MSHR miss cycles

331system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles
332system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles
333system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles
334system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles

335system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
336system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
337system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
338system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
339system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses
340system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses
341system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
342system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
343system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
344system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses

345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713 # average ReadReq mshr miss latency
346system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713 # average ReadReq mshr miss latency

345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency
346system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency

347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency
348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency
349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency
350system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency

351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591 # average overall mshr miss latency
352system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591 # average overall mshr miss latency
353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372 # average overall mshr miss latency
354system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372 # average overall mshr miss latency

351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency
352system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency
353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency
354system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency

355system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
356system.cpu.icache.tags.replacements 8769 # number of replacements

357system.cpu.icache.tags.tagsinuse 1391.464534 # Cycle average of tags in use

357system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use

358system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
359system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
360system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks.
361system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

362system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464534 # Average occupied blocks per requestor

362system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor

363system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
364system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
365system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
366system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
367system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
368system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
369system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
370system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses

--- 5 unchanged lines hidden (view full) ---

376system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits
377system.cpu.icache.overall_hits::total 643367692 # number of overall hits
378system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
379system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
380system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
381system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
382system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
383system.cpu.icache.overall_misses::total 10208 # number of overall misses

384system.cpu.icache.ReadReq_miss_latency::cpu.inst 207153000 # number of ReadReq miss cycles
385system.cpu.icache.ReadReq_miss_latency::total 207153000 # number of ReadReq miss cycles
386system.cpu.icache.demand_miss_latency::cpu.inst 207153000 # number of demand (read+write) miss cycles
387system.cpu.icache.demand_miss_latency::total 207153000 # number of demand (read+write) miss cycles
388system.cpu.icache.overall_miss_latency::cpu.inst 207153000 # number of overall miss cycles
389system.cpu.icache.overall_miss_latency::total 207153000 # number of overall miss cycles

384system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles
385system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles
386system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles
387system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles
388system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles
389system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles

390system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses)
391system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses)
392system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses
393system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses
394system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses
395system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses
396system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
397system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
398system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
399system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
400system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
401system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses

402system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411 # average ReadReq miss latency
403system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411 # average ReadReq miss latency
404system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency
405system.cpu.icache.demand_avg_miss_latency::total 20293.201411 # average overall miss latency
406system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency
407system.cpu.icache.overall_avg_miss_latency::total 20293.201411 # average overall miss latency

402system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency
403system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency
404system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
405system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency
406system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
407system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency

408system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
409system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
410system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
411system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
412system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
413system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
414system.cpu.icache.fast_writes 0 # number of fast writes performed
415system.cpu.icache.cache_copies 0 # number of cache copies performed
416system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses
417system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses
418system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses
419system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
420system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
421system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses

422system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196945000 # number of ReadReq MSHR miss cycles
423system.cpu.icache.ReadReq_mshr_miss_latency::total 196945000 # number of ReadReq MSHR miss cycles
424system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196945000 # number of demand (read+write) MSHR miss cycles
425system.cpu.icache.demand_mshr_miss_latency::total 196945000 # number of demand (read+write) MSHR miss cycles
426system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196945000 # number of overall MSHR miss cycles
427system.cpu.icache.overall_mshr_miss_latency::total 196945000 # number of overall MSHR miss cycles

422system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles
423system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles
424system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles
425system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles
426system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles
427system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles

428system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
429system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
430system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
431system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
432system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
433system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses

434system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19293.201411 # average ReadReq mshr miss latency
435system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19293.201411 # average ReadReq mshr miss latency
436system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency
437system.cpu.icache.demand_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency
438system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency
439system.cpu.icache.overall_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency

434system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency
435system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency
436system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
437system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency
438system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
439system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency

440system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
441system.cpu.l2cache.tags.replacements 257579 # number of replacements

442system.cpu.l2cache.tags.tagsinuse 32626.732272 # Cycle average of tags in use

442system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use

443system.cpu.l2cache.tags.total_refs 1218059 # Total number of references to valid blocks.
444system.cpu.l2cache.tags.sampled_refs 290322 # Sample count of references to valid blocks.
445system.cpu.l2cache.tags.avg_refs 4.195545 # Average number of references to valid blocks.
446system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

447system.cpu.l2cache.tags.occ_blocks::writebacks 2506.606006 # Average occupied blocks per requestor
448system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754528 # Average occupied blocks per requestor
449system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738 # Average occupied blocks per requestor

447system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor
448system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor
449system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor

450system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy
451system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy
452system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy
453system.cpu.l2cache.tags.occ_percent::total 0.995689 # Average percentage of cache occupancy
454system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
455system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
456system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
457system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id

--- 27 unchanged lines hidden (view full) ---

485system.cpu.l2cache.demand_misses::total 290359 # number of demand (read+write) misses
486system.cpu.l2cache.overall_misses::cpu.inst 1769 # number of overall misses
487system.cpu.l2cache.overall_misses::cpu.data 288590 # number of overall misses
488system.cpu.l2cache.overall_misses::total 290359 # number of overall misses
489system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469946000 # number of ReadExReq miss cycles
490system.cpu.l2cache.ReadExReq_miss_latency::total 3469946000 # number of ReadExReq miss cycles
491system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 93021000 # number of ReadCleanReq miss cycles
492system.cpu.l2cache.ReadCleanReq_miss_latency::total 93021000 # number of ReadCleanReq miss cycles

493system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681386500 # number of ReadSharedReq miss cycles
494system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681386500 # number of ReadSharedReq miss cycles

493system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles
494system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles

495system.cpu.l2cache.demand_miss_latency::cpu.inst 93021000 # number of demand (read+write) miss cycles

496system.cpu.l2cache.demand_miss_latency::cpu.data 15151332500 # number of demand (read+write) miss cycles
497system.cpu.l2cache.demand_miss_latency::total 15244353500 # number of demand (read+write) miss cycles

496system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles
497system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles

498system.cpu.l2cache.overall_miss_latency::cpu.inst 93021000 # number of overall miss cycles

499system.cpu.l2cache.overall_miss_latency::cpu.data 15151332500 # number of overall miss cycles
500system.cpu.l2cache.overall_miss_latency::total 15244353500 # number of overall miss cycles

499system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles
500system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles

501system.cpu.l2cache.Writeback_accesses::writebacks 89072 # number of Writeback accesses(hits+misses)
502system.cpu.l2cache.Writeback_accesses::total 89072 # number of Writeback accesses(hits+misses)
503system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses)
504system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses)
505system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses)
506system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses)
507system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses)
508system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses)

--- 14 unchanged lines hidden (view full) ---

523system.cpu.l2cache.demand_miss_rate::total 0.366453 # miss rate for demand accesses
524system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173295 # miss rate for overall accesses
525system.cpu.l2cache.overall_miss_rate::cpu.data 0.368974 # miss rate for overall accesses
526system.cpu.l2cache.overall_miss_rate::total 0.366453 # miss rate for overall accesses
527system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767 # average ReadExReq miss latency
528system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767 # average ReadExReq miss latency
529system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732 # average ReadCleanReq miss latency
530system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732 # average ReadCleanReq miss latency

531system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.321366 # average ReadSharedReq miss latency
532system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.321366 # average ReadSharedReq miss latency

531system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency
532system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency

533system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency

534system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency
535system.cpu.l2cache.demand_avg_miss_latency::total 52501.742670 # average overall miss latency

534system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
535system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency

536system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency

537system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency
538system.cpu.l2cache.overall_avg_miss_latency::total 52501.742670 # average overall miss latency

537system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
538system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency

539system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
540system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
541system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
542system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
543system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
544system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
545system.cpu.l2cache.fast_writes 0 # number of fast writes performed
546system.cpu.l2cache.cache_copies 0 # number of cache copies performed

--- 12 unchanged lines hidden (view full) ---

559system.cpu.l2cache.demand_mshr_misses::total 290359 # number of demand (read+write) MSHR misses
560system.cpu.l2cache.overall_mshr_misses::cpu.inst 1769 # number of overall MSHR misses
561system.cpu.l2cache.overall_mshr_misses::cpu.data 288590 # number of overall MSHR misses
562system.cpu.l2cache.overall_mshr_misses::total 290359 # number of overall MSHR misses
563system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000 # number of ReadExReq MSHR miss cycles
564system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles
565system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles
566system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles

567system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456416500 # number of ReadSharedReq MSHR miss cycles
568system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456416500 # number of ReadSharedReq MSHR miss cycles

567system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles
568system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles

569system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles

570system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265432500 # number of demand (read+write) MSHR miss cycles
571system.cpu.l2cache.demand_mshr_miss_latency::total 12340763500 # number of demand (read+write) MSHR miss cycles

570system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles
571system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles

572system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles

573system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265432500 # number of overall MSHR miss cycles
574system.cpu.l2cache.overall_mshr_miss_latency::total 12340763500 # number of overall MSHR miss cycles

573system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles
574system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles

575system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
576system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
577system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
578system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses
579system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadCleanReq accesses
580system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.173295 # mshr miss rate for ReadCleanReq accesses
581system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312137 # mshr miss rate for ReadSharedReq accesses
582system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312137 # mshr miss rate for ReadSharedReq accesses
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for demand accesses
584system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for demand accesses
585system.cpu.l2cache.demand_mshr_miss_rate::total 0.366453 # mshr miss rate for demand accesses
586system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for overall accesses
587system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for overall accesses
588system.cpu.l2cache.overall_mshr_miss_rate::total 0.366453 # mshr miss rate for overall accesses
589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767 # average ReadExReq mshr miss latency
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency
591system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency
592system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency

593system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366 # average ReadSharedReq mshr miss latency
594system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366 # average ReadSharedReq mshr miss latency

593system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency
594system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency

595system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency

596system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency
597system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency

596system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
597system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency

598system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency

599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency
600system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency

599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
600system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency

601system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

602system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
603system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
604system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
605system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
606system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
607system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

602system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution
609system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes)
610system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes)
611system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes)
612system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
613system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55757696 # Cumulative packet size per connected master and slave (bytes)
614system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes)
615system.cpu.toL2Bus.snoops 257579 # Total snoops (count)
616system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram

608system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution
611system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
612system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
613system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution
614system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution
615system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes)
616system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes)
617system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes)
618system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
619system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55757696 # Cumulative packet size per connected master and slave (bytes)
620system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes)
621system.cpu.toL2Bus.snoops 257579 # Total snoops (count)
622system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram

617system.cpu.toL2Bus.snoop_fanout::mean 1.140237 # Request fanout histogram
618system.cpu.toL2Bus.snoop_fanout::stdev 0.347233 # Request fanout histogram

623system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram
624system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram

619system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

625system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

620system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
621system.cpu.toL2Bus.snoop_fanout::1 1579165 85.98% 85.98% # Request fanout histogram
622system.cpu.toL2Bus.snoop_fanout::2 257579 14.02% 100.00% # Request fanout histogram

626system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram
627system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram
628system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram

623system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

629system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

624system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram

630system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram