| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.043695 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.043695 # Number of seconds simulated |
| 4sim_ticks 1043695084000 # Number of ticks simulated 5final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 1043695077500 # Number of ticks simulated 5final_tick 1043695077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 894518 # Simulator instruction rate (inst/s) 8host_op_rate 1098969 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1460200235 # Simulator tick rate (ticks/s) 10host_mem_usage 317628 # Number of bytes of host memory used 11host_seconds 714.76 # Real time elapsed on the host | 7host_inst_rate 877071 # Simulator instruction rate (inst/s) 8host_op_rate 1077535 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1431720298 # Simulator tick rate (ticks/s) 10host_mem_usage 317788 # Number of bytes of host memory used 11host_seconds 728.98 # Real time elapsed on the host |
| 12sim_insts 639366786 # Number of instructions simulated 13sim_ops 785501034 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory --- 129 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 673 # Number of system calls | 12sim_insts 639366786 # Number of instructions simulated 13sim_ops 785501034 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory --- 129 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 673 # Number of system calls |
| 157system.cpu.numCycles 2087390168 # number of cpu cycles simulated | 157system.cpu.numCycles 2087390155 # number of cpu cycles simulated |
| 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 639366786 # Number of instructions committed 161system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses 164system.cpu.num_func_calls 37261296 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 170system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written 174system.cpu.num_mem_refs 381221435 # number of memory refs 175system.cpu.num_load_insts 252240938 # Number of load instructions 176system.cpu.num_store_insts 128980497 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 639366786 # Number of instructions committed 161system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses 164system.cpu.num_func_calls 37261296 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 170system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written 174system.cpu.num_mem_refs 381221435 # number of memory refs 175system.cpu.num_load_insts 252240938 # Number of load instructions 176system.cpu.num_store_insts 128980497 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 178system.cpu.num_busy_cycles 2087390167.998000 # Number of busy cycles | 178system.cpu.num_busy_cycles 2087390154.998000 # Number of busy cycles |
| 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 137364859 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction 184system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction 212system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction 213system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 788730743 # Class of executed instruction 217system.cpu.dcache.tags.replacements 778046 # number of replacements | 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 137364859 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction 184system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction 212system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction 213system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 788730743 # Class of executed instruction 217system.cpu.dcache.tags.replacements 778046 # number of replacements |
| 218system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use | 218system.cpu.dcache.tags.tagsinuse 4093.640588 # Cycle average of tags in use |
| 219system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. | 219system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. |
| 222system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor | 222system.cpu.dcache.tags.warmup_cycle 996414000 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640588 # Average occupied blocks per requestor |
| 224system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id --- 85 unchanged lines hidden (view full) --- 317system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses 318system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses 319system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 320system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 321system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses 322system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses 323system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses 324system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses | 224system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id --- 85 unchanged lines hidden (view full) --- 317system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses 318system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses 319system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 320system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 321system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses 322system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses 323system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses 324system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses |
| 325system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles 326system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles 327system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles 328system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles 329system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles 330system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles 331system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles 332system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles 333system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles 334system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles | 325system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513638000 # number of ReadReq MSHR miss cycles 326system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513638000 # number of ReadReq MSHR miss cycles 327system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles 328system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles 329system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles 330system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles 331system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086805500 # number of demand (read+write) MSHR miss cycles 332system.cpu.dcache.demand_mshr_miss_latency::total 21086805500 # number of demand (read+write) MSHR miss cycles 333system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088488000 # number of overall MSHR miss cycles 334system.cpu.dcache.overall_mshr_miss_latency::total 21088488000 # number of overall MSHR miss cycles |
| 335system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 336system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 337system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 338system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 339system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses 340system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses 341system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 342system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 343system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 344system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses | 335system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 336system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 337system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 338system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 339system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses 340system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses 341system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 342system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 343system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 344system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses |
| 345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency 346system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency 348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency 349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency 350system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency 351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency 352system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency 353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency 354system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency | 345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.336308 # average ReadReq mshr miss latency 346system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.336308 # average ReadReq mshr miss latency 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency 348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency 349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency 350system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency 351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.120978 # average overall mshr miss latency 352system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.120978 # average overall mshr miss latency 353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.479959 # average overall mshr miss latency 354system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.479959 # average overall mshr miss latency |
| 355system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 356system.cpu.icache.tags.replacements 8769 # number of replacements | 355system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 356system.cpu.icache.tags.replacements 8769 # number of replacements |
| 357system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use | 357system.cpu.icache.tags.tagsinuse 1391.464503 # Cycle average of tags in use |
| 358system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. 359system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. 360system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. 361system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 358system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. 359system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. 360system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. 361system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 362system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor | 362system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464503 # Average occupied blocks per requestor |
| 363system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy 365system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 368system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id 369system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id 370system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 376system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits 377system.cpu.icache.overall_hits::total 643367691 # number of overall hits 378system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses 379system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses 380system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses 381system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses 382system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses 383system.cpu.icache.overall_misses::total 10208 # number of overall misses | 363system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy 365system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 368system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id 369system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id 370system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 376system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits 377system.cpu.icache.overall_hits::total 643367691 # number of overall hits 378system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses 379system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses 380system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses 381system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses 382system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses 383system.cpu.icache.overall_misses::total 10208 # number of overall misses |
| 384system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles 385system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles 386system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles 387system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles 388system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles 389system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles | 384system.cpu.icache.ReadReq_miss_latency::cpu.inst 207116000 # number of ReadReq miss cycles 385system.cpu.icache.ReadReq_miss_latency::total 207116000 # number of ReadReq miss cycles 386system.cpu.icache.demand_miss_latency::cpu.inst 207116000 # number of demand (read+write) miss cycles 387system.cpu.icache.demand_miss_latency::total 207116000 # number of demand (read+write) miss cycles 388system.cpu.icache.overall_miss_latency::cpu.inst 207116000 # number of overall miss cycles 389system.cpu.icache.overall_miss_latency::total 207116000 # number of overall miss cycles |
| 390system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) 391system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) 392system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses 393system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses 394system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses 395system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses 396system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses 397system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses 398system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses 399system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses 400system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses 401system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses | 390system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) 391system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) 392system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses 393system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses 394system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses 395system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses 396system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses 397system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses 398system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses 399system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses 400system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses 401system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses |
| 402system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency 403system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency 404system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency 405system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency 406system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency 407system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency | 402system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20289.576803 # average ReadReq miss latency 403system.cpu.icache.ReadReq_avg_miss_latency::total 20289.576803 # average ReadReq miss latency 404system.cpu.icache.demand_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency 405system.cpu.icache.demand_avg_miss_latency::total 20289.576803 # average overall miss latency 406system.cpu.icache.overall_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency 407system.cpu.icache.overall_avg_miss_latency::total 20289.576803 # average overall miss latency |
| 408system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 409system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 410system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 411system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 412system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 413system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 414system.cpu.icache.fast_writes 0 # number of fast writes performed 415system.cpu.icache.cache_copies 0 # number of cache copies performed 416system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses 417system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses 418system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses 419system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses 420system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses 421system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses | 408system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 409system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 410system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 411system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 412system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 413system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 414system.cpu.icache.fast_writes 0 # number of fast writes performed 415system.cpu.icache.cache_copies 0 # number of cache copies performed 416system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses 417system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses 418system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses 419system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses 420system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses 421system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses |
| 422system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186706500 # number of ReadReq MSHR miss cycles 423system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles 424system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles 425system.cpu.icache.demand_mshr_miss_latency::total 186706500 # number of demand (read+write) MSHR miss cycles 426system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles 427system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles | 422system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191804000 # number of ReadReq MSHR miss cycles 423system.cpu.icache.ReadReq_mshr_miss_latency::total 191804000 # number of ReadReq MSHR miss cycles 424system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191804000 # number of demand (read+write) MSHR miss cycles 425system.cpu.icache.demand_mshr_miss_latency::total 191804000 # number of demand (read+write) MSHR miss cycles 426system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191804000 # number of overall MSHR miss cycles 427system.cpu.icache.overall_mshr_miss_latency::total 191804000 # number of overall MSHR miss cycles |
| 428system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses 429system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses 430system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses 431system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses 432system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 433system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses | 428system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses 429system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses 430system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses 431system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses 432system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 433system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses |
| 434system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency 436system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency 438system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency | 434system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18789.576803 # average ReadReq mshr miss latency 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18789.576803 # average ReadReq mshr miss latency 436system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency 438system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency |
| 440system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 441system.cpu.l2cache.tags.replacements 256932 # number of replacements | 440system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 441system.cpu.l2cache.tags.replacements 256932 # number of replacements |
| 442system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use | 442system.cpu.l2cache.tags.tagsinuse 32626.698188 # Cycle average of tags in use |
| 443system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. 444system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. 445system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. 446system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 443system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. 444system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. 445system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. 446system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 447system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505475 # Average occupied blocks per requestor | 447system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505447 # Average occupied blocks per requestor |
| 448system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor | 448system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor |
| 449system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.111953 # Average occupied blocks per requestor | 449system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.112078 # Average occupied blocks per requestor |
| 450system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy 451system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy 452system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy 453system.cpu.l2cache.tags.occ_percent::total 0.995688 # Average percentage of cache occupancy 454system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id 455system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 456system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 457system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id --- 21 unchanged lines hidden (view full) --- 479system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses 480system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses 481system.cpu.l2cache.demand_misses::cpu.inst 1770 # number of demand (read+write) misses 482system.cpu.l2cache.demand_misses::cpu.data 287942 # number of demand (read+write) misses 483system.cpu.l2cache.demand_misses::total 289712 # number of demand (read+write) misses 484system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses 485system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses 486system.cpu.l2cache.overall_misses::total 289712 # number of overall misses | 450system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy 451system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy 452system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy 453system.cpu.l2cache.tags.occ_percent::total 0.995688 # Average percentage of cache occupancy 454system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id 455system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 456system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 457system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id --- 21 unchanged lines hidden (view full) --- 479system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses 480system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses 481system.cpu.l2cache.demand_misses::cpu.inst 1770 # number of demand (read+write) misses 482system.cpu.l2cache.demand_misses::cpu.data 287942 # number of demand (read+write) misses 483system.cpu.l2cache.demand_misses::total 289712 # number of demand (read+write) misses 484system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses 485system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses 486system.cpu.l2cache.overall_misses::total 289712 # number of overall misses |
| 487system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92118500 # number of ReadReq miss cycles 488system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11536392000 # number of ReadReq miss cycles 489system.cpu.l2cache.ReadReq_miss_latency::total 11628510500 # number of ReadReq miss cycles 490system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436883000 # number of ReadExReq miss cycles 491system.cpu.l2cache.ReadExReq_miss_latency::total 3436883000 # number of ReadExReq miss cycles 492system.cpu.l2cache.demand_miss_latency::cpu.inst 92118500 # number of demand (read+write) miss cycles 493system.cpu.l2cache.demand_miss_latency::cpu.data 14973275000 # number of demand (read+write) miss cycles 494system.cpu.l2cache.demand_miss_latency::total 15065393500 # number of demand (read+write) miss cycles 495system.cpu.l2cache.overall_miss_latency::cpu.inst 92118500 # number of overall miss cycles 496system.cpu.l2cache.overall_miss_latency::cpu.data 14973275000 # number of overall miss cycles 497system.cpu.l2cache.overall_miss_latency::total 15065393500 # number of overall miss cycles | 487system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92997000 # number of ReadReq miss cycles 488system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11647316500 # number of ReadReq miss cycles 489system.cpu.l2cache.ReadReq_miss_latency::total 11740313500 # number of ReadReq miss cycles 490system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469929500 # number of ReadExReq miss cycles 491system.cpu.l2cache.ReadExReq_miss_latency::total 3469929500 # number of ReadExReq miss cycles 492system.cpu.l2cache.demand_miss_latency::cpu.inst 92997000 # number of demand (read+write) miss cycles 493system.cpu.l2cache.demand_miss_latency::cpu.data 15117246000 # number of demand (read+write) miss cycles 494system.cpu.l2cache.demand_miss_latency::total 15210243000 # number of demand (read+write) miss cycles 495system.cpu.l2cache.overall_miss_latency::cpu.inst 92997000 # number of overall miss cycles 496system.cpu.l2cache.overall_miss_latency::cpu.data 15117246000 # number of overall miss cycles 497system.cpu.l2cache.overall_miss_latency::total 15210243000 # number of overall miss cycles |
| 498system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses) 499system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses) 500system.cpu.l2cache.ReadReq_accesses::total 723027 # number of ReadReq accesses(hits+misses) 501system.cpu.l2cache.Writeback_accesses::writebacks 91561 # number of Writeback accesses(hits+misses) 502system.cpu.l2cache.Writeback_accesses::total 91561 # number of Writeback accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) 505system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 514system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses 515system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses 516system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173393 # miss rate for demand accesses 517system.cpu.l2cache.demand_miss_rate::cpu.data 0.368145 # miss rate for demand accesses 518system.cpu.l2cache.demand_miss_rate::total 0.365636 # miss rate for demand accesses 519system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses 520system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses 521system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses | 498system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses) 499system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses) 500system.cpu.l2cache.ReadReq_accesses::total 723027 # number of ReadReq accesses(hits+misses) 501system.cpu.l2cache.Writeback_accesses::writebacks 91561 # number of Writeback accesses(hits+misses) 502system.cpu.l2cache.Writeback_accesses::total 91561 # number of Writeback accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) 505system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 514system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses 515system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses 516system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173393 # miss rate for demand accesses 517system.cpu.l2cache.demand_miss_rate::cpu.data 0.368145 # miss rate for demand accesses 518system.cpu.l2cache.demand_miss_rate::total 0.365636 # miss rate for demand accesses 519system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses 520system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses 521system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses |
| 522system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52044.350282 # average ReadReq miss latency 523system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.099847 # average ReadReq miss latency 524system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.442185 # average ReadReq miss latency 525system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.711119 # average ReadExReq miss latency 526system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.711119 # average ReadExReq miss latency 527system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency 528system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency 529system.cpu.l2cache.demand_avg_miss_latency::total 52001.275405 # average overall miss latency 530system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency 531system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency 532system.cpu.l2cache.overall_avg_miss_latency::total 52001.275405 # average overall miss latency | 522system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.677966 # average ReadReq miss latency 523system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099847 # average ReadReq miss latency 524system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118 # average ReadReq miss latency 525system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119 # average ReadExReq miss latency 526system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency 527system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency 528system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency 529system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency 530system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency 531system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency 532system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency |
| 533system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 534system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 537system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 539system.cpu.l2cache.fast_writes 0 # number of fast writes performed 540system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 546system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses 547system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses 548system.cpu.l2cache.demand_mshr_misses::cpu.inst 1770 # number of demand (read+write) MSHR misses 549system.cpu.l2cache.demand_mshr_misses::cpu.data 287942 # number of demand (read+write) MSHR misses 550system.cpu.l2cache.demand_mshr_misses::total 289712 # number of demand (read+write) MSHR misses 551system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses 552system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses 553system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses | 533system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 534system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 537system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 539system.cpu.l2cache.fast_writes 0 # number of fast writes performed 540system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 546system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses 547system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses 548system.cpu.l2cache.demand_mshr_misses::cpu.inst 1770 # number of demand (read+write) MSHR misses 549system.cpu.l2cache.demand_mshr_misses::cpu.data 287942 # number of demand (read+write) MSHR misses 550system.cpu.l2cache.demand_mshr_misses::total 289712 # number of demand (read+write) MSHR misses 551system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses 552system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses 553system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses |
| 554system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70811000 # number of ReadReq MSHR miss cycles 555system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8873960000 # number of ReadReq MSHR miss cycles 556system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8944771000 # number of ReadReq MSHR miss cycles 557system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles 558system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles 559system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70811000 # number of demand (read+write) MSHR miss cycles 560system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11517680000 # number of demand (read+write) MSHR miss cycles 561system.cpu.l2cache.demand_mshr_miss_latency::total 11588491000 # number of demand (read+write) MSHR miss cycles 562system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70811000 # number of overall MSHR miss cycles 563system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11517680000 # number of overall MSHR miss cycles 564system.cpu.l2cache.overall_mshr_miss_latency::total 11588491000 # number of overall MSHR miss cycles | 554system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71689000 # number of ReadReq MSHR miss cycles 555system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984884500 # number of ReadReq MSHR miss cycles 556system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles 557system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles 558system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles 559system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71689000 # number of demand (read+write) MSHR miss cycles 560system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661651000 # number of demand (read+write) MSHR miss cycles 561system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles 562system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71689000 # number of overall MSHR miss cycles 563system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661651000 # number of overall MSHR miss cycles 564system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles |
| 565system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses 566system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses 567system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses 568system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses 569system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses 570system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for demand accesses 571system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for demand accesses 572system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses 573system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses 574system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses 575system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses | 565system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses 566system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses 567system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses 568system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses 569system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses 570system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for demand accesses 571system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for demand accesses 572system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses 573system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses 574system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses 575system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses |
| 576system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.214689 # average ReadReq mshr miss latency 577system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 578system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.049191 # average ReadReq mshr miss latency 579system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 580system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 581system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency 582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 583system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 586system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency | 576system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.259887 # average ReadReq mshr miss latency 577system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 578system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency 579system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 580system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 581system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency 582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 583system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 586system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency |
| 587system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution 590system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution 591system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution 592system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution 593system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) 594system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) 595system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) 596system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) 597system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) 598system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) 599system.cpu.toL2Bus.snoops 0 # Total snoops (count) 600system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram | 587system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution 590system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution 591system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution 592system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution 593system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) 594system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) 595system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) 596system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) 597system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) 598system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) 599system.cpu.toL2Bus.snoops 0 # Total snoops (count) 600system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram |
| 601system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram | 601system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram |
| 602system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 602system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 607system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 608system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 609system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram 610system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram | 607system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram 608system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| 611system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 609system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 612system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 613system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram | 610system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 611system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram |
| 614system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram 615system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) 616system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 617system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) 618system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 619system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) 620system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 621system.membus.trans_dist::ReadReq 223619 # Transaction distribution --- 11 unchanged lines hidden (view full) --- 633system.membus.snoop_fanout::stdev 0 # Request fanout histogram 634system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 635system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram 636system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 637system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 638system.membus.snoop_fanout::min_value 0 # Request fanout histogram 639system.membus.snoop_fanout::max_value 0 # Request fanout histogram 640system.membus.snoop_fanout::total 355811 # Request fanout histogram | 612system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram 613system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) 614system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 615system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) 616system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 617system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) 618system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 619system.membus.trans_dist::ReadReq 223619 # Transaction distribution --- 11 unchanged lines hidden (view full) --- 631system.membus.snoop_fanout::stdev 0 # Request fanout histogram 632system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 633system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram 634system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 635system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 636system.membus.snoop_fanout::min_value 0 # Request fanout histogram 637system.membus.snoop_fanout::max_value 0 # Request fanout histogram 638system.membus.snoop_fanout::total 355811 # Request fanout histogram |
| 641system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) | 639system.membus.reqLayer0.occupancy 632634000 # Layer occupancy (ticks) |
| 642system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 640system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 643system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) 644system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 641system.membus.respLayer1.occupancy 1448919000 # Layer occupancy (ticks) 642system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 645 646---------- End Simulation Statistics ---------- | 643 644---------- End Simulation Statistics ---------- |