| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.043695 # Number of seconds simulated 4sim_ticks 1043695084000 # Number of ticks simulated 5final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.043695 # Number of seconds simulated 4sim_ticks 1043695084000 # Number of ticks simulated 5final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 974812 # Simulator instruction rate (inst/s) 8host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1591272225 # Simulator tick rate (ticks/s) 10host_mem_usage 314196 # Number of bytes of host memory used 11host_seconds 655.89 # Real time elapsed on the host | 7host_inst_rate 894518 # Simulator instruction rate (inst/s) 8host_op_rate 1098969 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1460200235 # Simulator tick rate (ticks/s) 10host_mem_usage 317628 # Number of bytes of host memory used 11host_seconds 714.76 # Real time elapsed on the host |
| 12sim_insts 639366786 # Number of instructions simulated 13sim_ops 785501034 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory --- 11 unchanged lines hidden (view full) --- 31system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 639366786 # Number of instructions simulated 13sim_ops 785501034 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory --- 11 unchanged lines hidden (view full) --- 31system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) |
| 39system.membus.trans_dist::ReadReq 223619 # Transaction distribution 40system.membus.trans_dist::ReadResp 223619 # Transaction distribution 41system.membus.trans_dist::Writeback 66098 # Transaction distribution 42system.membus.trans_dist::ReadExReq 66093 # Transaction distribution 43system.membus.trans_dist::ReadExResp 66093 # Transaction distribution 44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) 46system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) 47system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) 48system.membus.snoops 0 # Total snoops (count) 49system.membus.snoop_fanout::samples 355811 # Request fanout histogram 50system.membus.snoop_fanout::mean 0 # Request fanout histogram 51system.membus.snoop_fanout::stdev 0 # Request fanout histogram 52system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 53system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram 54system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 55system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 56system.membus.snoop_fanout::min_value 0 # Request fanout histogram 57system.membus.snoop_fanout::max_value 0 # Request fanout histogram 58system.membus.snoop_fanout::total 355811 # Request fanout histogram 59system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) 60system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 61system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) 62system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | |
| 63system.cpu_clk_domain.clock 500 # Clock period in ticks | 39system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 64system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 65system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 66system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 67system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 68system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 69system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 70system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 71system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 77system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 78system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 79system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 80system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 81system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 82system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 83system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 84system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 85system.cpu.dtb.inst_hits 0 # ITB inst hits 86system.cpu.dtb.inst_misses 0 # ITB inst misses 87system.cpu.dtb.read_hits 0 # DTB read hits 88system.cpu.dtb.read_misses 0 # DTB read misses 89system.cpu.dtb.write_hits 0 # DTB write hits 90system.cpu.dtb.write_misses 0 # DTB write misses 91system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 92system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 98system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 99system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 100system.cpu.dtb.read_accesses 0 # DTB read accesses 101system.cpu.dtb.write_accesses 0 # DTB write accesses 102system.cpu.dtb.inst_accesses 0 # ITB inst accesses 103system.cpu.dtb.hits 0 # DTB hits 104system.cpu.dtb.misses 0 # DTB misses 105system.cpu.dtb.accesses 0 # DTB accesses | 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses |
| 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 127system.cpu.itb.inst_hits 0 # ITB inst hits 128system.cpu.itb.inst_misses 0 # ITB inst misses 129system.cpu.itb.read_hits 0 # DTB read hits 130system.cpu.itb.read_misses 0 # DTB read misses 131system.cpu.itb.write_hits 0 # DTB write hits 132system.cpu.itb.write_misses 0 # DTB write misses 133system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 134system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 66 unchanged lines hidden (view full) --- 201system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction 202system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction 203system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction 204system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction 205system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction 206system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 207system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::total 788730743 # Class of executed instruction | 135system.cpu.itb.inst_hits 0 # ITB inst hits 136system.cpu.itb.inst_misses 0 # ITB inst misses 137system.cpu.itb.read_hits 0 # DTB read hits 138system.cpu.itb.read_misses 0 # DTB read misses 139system.cpu.itb.write_hits 0 # DTB write hits 140system.cpu.itb.write_misses 0 # DTB write misses 141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 66 unchanged lines hidden (view full) --- 209system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction 212system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction 213system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 788730743 # Class of executed instruction |
| 217system.cpu.dcache.tags.replacements 778046 # number of replacements 218system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use 219system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor 224system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses 235system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits 236system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits 237system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits 238system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits 239system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits 240system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits 241system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 242system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 243system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 244system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 245system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits 246system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits 247system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits 248system.cpu.dcache.overall_hits::total 378498833 # number of overall hits 249system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses 250system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses 251system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses 252system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses 253system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses 254system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses 255system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses 256system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses 257system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses 258system.cpu.dcache.overall_misses::total 782143 # number of overall misses 259system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles 260system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles 261system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles 262system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles 263system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles 264system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles 265system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles 266system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles 267system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) 268system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) 269system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 270system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 271system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) 272system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) 273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 274system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 275system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 276system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 277system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses 278system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses 279system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses 280system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses 281system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses 282system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses 283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses 284system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses 285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses 286system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses 287system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses 288system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses 289system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses 290system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses 291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency 292system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency 293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency 294system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency 295system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency 296system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu.dcache.fast_writes 0 # number of fast writes performed 306system.cpu.dcache.cache_copies 0 # number of cache copies performed 307system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks 308system.cpu.dcache.writebacks::total 91561 # number of writebacks 309system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 310system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 311system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 312system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 313system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 314system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 315system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses 316system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses 317system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses 318system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses 319system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 320system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 321system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses 322system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses 323system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses 324system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses 325system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles 326system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles 327system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles 328system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles 329system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles 330system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles 331system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles 332system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles 333system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles 334system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles 335system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 336system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 337system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 338system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 339system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses 340system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses 341system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 342system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 343system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 344system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency 346system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency 348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency 349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency 350system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency 351system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency 352system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency 353system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency 354system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency 355system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 209system.cpu.icache.tags.replacements 8769 # number of replacements 210system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use 211system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. 212system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. 213system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. 214system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 215system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor 216system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy --- 216 unchanged lines hidden (view full) --- 433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 434system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency 435system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 436system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency 437system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency 438system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 439system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency 440system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 356system.cpu.icache.tags.replacements 8769 # number of replacements 357system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use 358system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. 359system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. 360system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. 361system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 362system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor 363system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy --- 216 unchanged lines hidden (view full) --- 580system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 581system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency 582system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 583system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 586system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency 587system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 441system.cpu.dcache.tags.replacements 778046 # number of replacements 442system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use 443system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. 444system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. 445system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. 446system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. 447system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor 448system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy 449system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy 450system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 451system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 452system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 453system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id 454system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id 455system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id 456system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 457system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses 458system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses 459system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits 460system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits 461system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits 462system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits 463system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits 464system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits 465system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 466system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 467system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 468system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 469system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits 470system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits 471system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits 472system.cpu.dcache.overall_hits::total 378498833 # number of overall hits 473system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses 474system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses 475system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses 476system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses 477system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses 478system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses 479system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses 480system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses 481system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses 482system.cpu.dcache.overall_misses::total 782143 # number of overall misses 483system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles 484system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles 485system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles 486system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles 487system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles 488system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles 489system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles 490system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles 491system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) 492system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) 493system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 494system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 495system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) 496system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) 497system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 498system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 499system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 500system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 501system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses 502system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses 503system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses 504system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses 505system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses 506system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses 507system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses 508system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses 509system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses 510system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses 511system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses 512system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses 513system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses 514system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses 515system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency 516system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency 517system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency 518system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency 519system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency 520system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency 521system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency 522system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency 523system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 524system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 525system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 526system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 527system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 528system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 529system.cpu.dcache.fast_writes 0 # number of fast writes performed 530system.cpu.dcache.cache_copies 0 # number of cache copies performed 531system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks 532system.cpu.dcache.writebacks::total 91561 # number of writebacks 533system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 534system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 535system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 536system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 537system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 538system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 539system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses 540system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses 541system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses 542system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses 543system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 544system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 545system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses 546system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses 547system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses 548system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses 549system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles 550system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles 551system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles 552system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles 553system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles 554system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles 555system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles 556system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles 557system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles 558system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles 559system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 560system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 561system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 562system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 563system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses 564system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses 565system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 566system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 567system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 568system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 569system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency 570system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency 571system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency 572system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency 573system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency 574system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency 575system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency 576system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency 577system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency 578system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency 579system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 580system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution 581system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution 583system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution 584system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution 585system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) 586system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) 587system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) --- 17 unchanged lines hidden (view full) --- 605system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram 607system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) 608system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 609system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) 610system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 611system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) 612system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 588system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution 590system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution 591system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution 592system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution 593system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) 594system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) 595system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) --- 17 unchanged lines hidden (view full) --- 613system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 614system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram 615system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) 616system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 617system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) 618system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 619system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) 620system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 621system.membus.trans_dist::ReadReq 223619 # Transaction distribution 622system.membus.trans_dist::ReadResp 223619 # Transaction distribution 623system.membus.trans_dist::Writeback 66098 # Transaction distribution 624system.membus.trans_dist::ReadExReq 66093 # Transaction distribution 625system.membus.trans_dist::ReadExResp 66093 # Transaction distribution 626system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) 627system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) 628system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) 629system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) 630system.membus.snoops 0 # Total snoops (count) 631system.membus.snoop_fanout::samples 355811 # Request fanout histogram 632system.membus.snoop_fanout::mean 0 # Request fanout histogram 633system.membus.snoop_fanout::stdev 0 # Request fanout histogram 634system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 635system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram 636system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 637system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 638system.membus.snoop_fanout::min_value 0 # Request fanout histogram 639system.membus.snoop_fanout::max_value 0 # Request fanout histogram 640system.membus.snoop_fanout::total 355811 # Request fanout histogram 641system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) 642system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 643system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) 644system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
|
| 613 614---------- End Simulation Statistics ---------- | 645 646---------- End Simulation Statistics ---------- |