3,5c3,5
< sim_seconds 1.045756 # Number of seconds simulated
< sim_ticks 1045756396500 # Number of ticks simulated
< final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.046047 # Number of seconds simulated
> sim_ticks 1046047111500 # Number of ticks simulated
> final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 546786 # Simulator instruction rate (inst/s)
< host_op_rate 671760 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 894330624 # Simulator tick rate (ticks/s)
< host_mem_usage 273552 # Number of bytes of host memory used
< host_seconds 1169.32 # Real time elapsed on the host
---
> host_inst_rate 666714 # Simulator instruction rate (inst/s)
> host_op_rate 819099 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1090788712 # Simulator tick rate (ticks/s)
> host_mem_usage 278188 # Number of bytes of host memory used
> host_seconds 958.98 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory
< system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory
> system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory
25,26c25,26
< system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory
29,40c29,40
< system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
42c42
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
72c72
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
102c102
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
132c132
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
163,164c163,164
< system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 2091512793 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 2092094223 # number of cpu cycles simulated
185c185
< system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles
224c224
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
226c226
< system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use
230,233c230,233
< system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy
243c243
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
268,275c268,275
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles
300,307c300,307
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency
314,315c314,315
< system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks
< system.cpu.dcache.writebacks::total 88995 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks
> system.cpu.dcache.writebacks::total 88967 # number of writebacks
332,341c332,341
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles
352,362c352,362
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
364c364
< system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use
369,371c369,371
< system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy
379c379
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
392,397c392,397
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles
410,415c410,415
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency
430,435c430,435
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210621500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 210621500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210621500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 210621500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210621500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 210621500 # number of overall MSHR miss cycles
442,462c442,462
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 257772 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20632.983934 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20632.983934 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 257791 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
464c464
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
467,473c467,473
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits
480,481c480,481
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490296 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 490296 # number of ReadSharedReq hits
483,484c483,484
< system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 493526 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 501975 # number of demand (read+write) hits
486,487c486,487
< system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits
< system.cpu.l2cache.overall_hits::total 501982 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 493526 # number of overall hits
> system.cpu.l2cache.overall_hits::total 501975 # number of overall hits
492,493c492,493
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222523 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 222523 # number of ReadSharedReq misses
495,496c495,496
< system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 288616 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 290375 # number of demand (read+write) misses
498,513c498,513
< system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses
< system.cpu.l2cache.overall_misses::total 290368 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 288616 # number of overall misses
> system.cpu.l2cache.overall_misses::total 290375 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3998679500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses)
532,533c532,533
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses
535,536c535,536
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses
538,551c538,551
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency
564,565c564,565
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses
567,568c567,568
< system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses
570,583c570,583
< system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles
588,589c588,589
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses
591,592c591,592
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses
594,607c594,607
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency
611,612c611,612
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
614c614
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
616c616
< system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution
618c618
< system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution
627,629c627,629
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 257772 # Total snoops (count)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 257791 # Total snoops (count)
631,633c631,633
< system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram
635,636c635,636
< system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram
641,642c641,642
< system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks)
648,649c648,655
< system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 224275 # Transaction distribution
---
> system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 224282 # Transaction distribution
651c657
< system.membus.trans_dist::CleanEvict 190094 # Transaction distribution
---
> system.membus.trans_dist::CleanEvict 190103 # Transaction distribution
654,658c660,664
< system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes)
661c667
< system.membus.snoop_fanout::samples 546561 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 290376 # Request fanout histogram
665c671
< system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram
670,671c676,677
< system.membus.snoop_fanout::total 546561 # Request fanout histogram
< system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 290376 # Request fanout histogram
> system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks)
673c679
< system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks)
< sim_seconds 1.045756 # Number of seconds simulated
< sim_ticks 1045756396500 # Number of ticks simulated
< final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.046047 # Number of seconds simulated
> sim_ticks 1046047111500 # Number of ticks simulated
> final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 546786 # Simulator instruction rate (inst/s)
< host_op_rate 671760 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 894330624 # Simulator tick rate (ticks/s)
< host_mem_usage 273552 # Number of bytes of host memory used
< host_seconds 1169.32 # Real time elapsed on the host
---
> host_inst_rate 666714 # Simulator instruction rate (inst/s)
> host_op_rate 819099 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1090788712 # Simulator tick rate (ticks/s)
> host_mem_usage 278188 # Number of bytes of host memory used
> host_seconds 958.98 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory
< system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory
> system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory
25,26c25,26
< system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory
29,40c29,40
< system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
42c42
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
72c72
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
102c102
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
132c132
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
163,164c163,164
< system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 2091512793 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 2092094223 # number of cpu cycles simulated
185c185
< system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles
224c224
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
226c226
< system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use
230,233c230,233
< system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy
243c243
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
268,275c268,275
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles
300,307c300,307
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency
314,315c314,315
< system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks
< system.cpu.dcache.writebacks::total 88995 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks
> system.cpu.dcache.writebacks::total 88967 # number of writebacks
332,341c332,341
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles
352,362c352,362
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
364c364
< system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use
369,371c369,371
< system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy
379c379
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
392,397c392,397
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles
410,415c410,415
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency
430,435c430,435
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210621500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 210621500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210621500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 210621500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210621500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 210621500 # number of overall MSHR miss cycles
442,462c442,462
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 257772 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20632.983934 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20632.983934 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 257791 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
464c464
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
467,473c467,473
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits
480,481c480,481
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490296 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 490296 # number of ReadSharedReq hits
483,484c483,484
< system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 493526 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 501975 # number of demand (read+write) hits
486,487c486,487
< system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits
< system.cpu.l2cache.overall_hits::total 501982 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 493526 # number of overall hits
> system.cpu.l2cache.overall_hits::total 501975 # number of overall hits
492,493c492,493
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222523 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 222523 # number of ReadSharedReq misses
495,496c495,496
< system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 288616 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 290375 # number of demand (read+write) misses
498,513c498,513
< system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses
< system.cpu.l2cache.overall_misses::total 290368 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 288616 # number of overall misses
> system.cpu.l2cache.overall_misses::total 290375 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3998679500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses)
532,533c532,533
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses
535,536c535,536
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses
538,551c538,551
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency
564,565c564,565
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses
567,568c567,568
< system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses
570,583c570,583
< system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles
588,589c588,589
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses
591,592c591,592
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses
594,607c594,607
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency
611,612c611,612
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
614c614
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
616c616
< system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution
618c618
< system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution
627,629c627,629
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 257772 # Total snoops (count)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 257791 # Total snoops (count)
631,633c631,633
< system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram
635,636c635,636
< system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram
641,642c641,642
< system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks)
648,649c648,655
< system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 224275 # Transaction distribution
---
> system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 224282 # Transaction distribution
651c657
< system.membus.trans_dist::CleanEvict 190094 # Transaction distribution
---
> system.membus.trans_dist::CleanEvict 190103 # Transaction distribution
654,658c660,664
< system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes)
661c667
< system.membus.snoop_fanout::samples 546561 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 290376 # Request fanout histogram
665c671
< system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram
670,671c676,677
< system.membus.snoop_fanout::total 546561 # Request fanout histogram
< system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 290376 # Request fanout histogram
> system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks)
673c679
< system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks)