3,5c3,5
< sim_seconds 1.043722 # Number of seconds simulated
< sim_ticks 1043722398500 # Number of ticks simulated
< final_tick 1043722398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.043724 # Number of seconds simulated
> sim_ticks 1043723537500 # Number of ticks simulated
> final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 921530 # Simulator instruction rate (inst/s)
< host_op_rate 1132156 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1504334297 # Simulator tick rate (ticks/s)
< host_mem_usage 320916 # Number of bytes of host memory used
< host_seconds 693.81 # Real time elapsed on the host
---
> host_inst_rate 832063 # Simulator instruction rate (inst/s)
> host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1358287943 # Simulator tick rate (ticks/s)
> host_mem_usage 323064 # Number of bytes of host memory used
> host_seconds 768.41 # Real time elapsed on the host
29,30c29,30
< system.physmem.bw_read::cpu.data 17696046 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 17804520 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s)
33,35c33,35
< system.physmem.bw_write::writebacks 4053062 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4053062 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4053062 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s)
37,38c37,38
< system.physmem.bw_total::cpu.data 17696046 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21857582 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 2087444797 # number of cpu cycles simulated
---
> system.cpu.numCycles 2087447075 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 2087444796.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4093.640641 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 996416500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640641 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor
259,260c259,260
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 18609964000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 18609964000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles
263,266c263,266
< system.cpu.dcache.demand_miss_latency::cpu.data 22287133000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 22287133000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 22287133000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 22287133000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles
291,292c291,292
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency
295,298c295,298
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 28500.024297 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 28494.959362 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency
325,326c325,326
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17897244000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 17897244000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles
331,334c331,334
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21505090000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 21505090000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21506842000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 21506842000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles
345,346c345,346
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency
351,354c351,354
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency
357c357
< system.cpu.icache.tags.tagsinuse 1391.464534 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use
362c362
< system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464534 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor
384,389c384,389
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 207153000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 207153000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 207153000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 207153000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 207153000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 207153000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles
402,407c402,407
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20293.201411 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20293.201411 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency
422,427c422,427
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196945000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 196945000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196945000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 196945000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196945000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 196945000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles
434,439c434,439
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19293.201411 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19293.201411 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency
442c442
< system.cpu.l2cache.tags.tagsinuse 32626.732272 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use
447,449c447,449
< system.cpu.l2cache.tags.occ_blocks::writebacks 2506.606006 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754528 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor
493,494c493,494
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681386500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681386500 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles
496,497c496,497
< system.cpu.l2cache.demand_miss_latency::cpu.data 15151332500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 15244353500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles
499,500c499,500
< system.cpu.l2cache.overall_miss_latency::cpu.data 15151332500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 15244353500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles
531,532c531,532
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.321366 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.321366 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency
534,535c534,535
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52501.742670 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency
537,538c537,538
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52501.742670 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency
567,568c567,568
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456416500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456416500 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles
570,571c570,571
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265432500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 12340763500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles
573,574c573,574
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265432500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 12340763500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles
593,594c593,594
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency
596,597c596,597
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency
599,600c599,600
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency
601a602,607
> system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
617,618c623,624
< system.cpu.toL2Bus.snoop_fanout::mean 1.140237 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.347233 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram
620,622c626,628
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1579165 85.98% 85.98% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 257579 14.02% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram
624c630
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_seconds 1.043722 # Number of seconds simulated
< sim_ticks 1043722398500 # Number of ticks simulated
< final_tick 1043722398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.043724 # Number of seconds simulated
> sim_ticks 1043723537500 # Number of ticks simulated
> final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 921530 # Simulator instruction rate (inst/s)
< host_op_rate 1132156 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1504334297 # Simulator tick rate (ticks/s)
< host_mem_usage 320916 # Number of bytes of host memory used
< host_seconds 693.81 # Real time elapsed on the host
---
> host_inst_rate 832063 # Simulator instruction rate (inst/s)
> host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1358287943 # Simulator tick rate (ticks/s)
> host_mem_usage 323064 # Number of bytes of host memory used
> host_seconds 768.41 # Real time elapsed on the host
29,30c29,30
< system.physmem.bw_read::cpu.data 17696046 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 17804520 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s)
33,35c33,35
< system.physmem.bw_write::writebacks 4053062 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4053062 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4053062 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s)
37,38c37,38
< system.physmem.bw_total::cpu.data 17696046 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 21857582 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 2087444797 # number of cpu cycles simulated
---
> system.cpu.numCycles 2087447075 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 2087444796.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4093.640641 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 996416500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640641 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor
259,260c259,260
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 18609964000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 18609964000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles
263,266c263,266
< system.cpu.dcache.demand_miss_latency::cpu.data 22287133000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 22287133000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 22287133000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 22287133000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles
291,292c291,292
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency
295,298c295,298
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 28500.024297 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 28494.959362 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency
325,326c325,326
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17897244000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 17897244000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles
331,334c331,334
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21505090000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 21505090000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21506842000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 21506842000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles
345,346c345,346
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency
351,354c351,354
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency
357c357
< system.cpu.icache.tags.tagsinuse 1391.464534 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use
362c362
< system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464534 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor
384,389c384,389
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 207153000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 207153000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 207153000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 207153000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 207153000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 207153000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles
402,407c402,407
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20293.201411 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20293.201411 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency
422,427c422,427
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196945000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 196945000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196945000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 196945000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196945000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 196945000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles
434,439c434,439
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19293.201411 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19293.201411 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency
442c442
< system.cpu.l2cache.tags.tagsinuse 32626.732272 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use
447,449c447,449
< system.cpu.l2cache.tags.occ_blocks::writebacks 2506.606006 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754528 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor
493,494c493,494
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681386500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681386500 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles
496,497c496,497
< system.cpu.l2cache.demand_miss_latency::cpu.data 15151332500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 15244353500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles
499,500c499,500
< system.cpu.l2cache.overall_miss_latency::cpu.data 15151332500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 15244353500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles
531,532c531,532
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.321366 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.321366 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency
534,535c534,535
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52501.742670 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency
537,538c537,538
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52501.742670 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency
567,568c567,568
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456416500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456416500 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles
570,571c570,571
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265432500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 12340763500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles
573,574c573,574
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265432500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 12340763500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles
593,594c593,594
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency
596,597c596,597
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency
599,600c599,600
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency
601a602,607
> system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
617,618c623,624
< system.cpu.toL2Bus.snoop_fanout::mean 1.140237 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.347233 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram
620,622c626,628
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1579165 85.98% 85.98% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 257579 14.02% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram
624c630
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram