Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt

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stats.txt (11687:b3d5f0e9e258)	stats.txt (11955:1170d039b31e)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.046047 # Number of seconds simulated 4sim_ticks 1046047111500 # Number of ticks simulated 5final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1255251 # Simulator instruction rate (inst/s) 8host_op_rate 1542152 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2053674689 # Simulator tick rate (ticks/s) 10host_mem_usage 277480 # Number of bytes of host memory used 11host_seconds 509.35 # Real time elapsed on the host 12sim_insts 639366787 # Number of instructions simulated 13sim_ops 785501035 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory 19system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 51system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 52system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 53system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 54system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 55system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 56system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 73system.cpu.dtb.walker.walks 0 # Table walker walks requested 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 81system.cpu.dtb.inst_hits 0 # ITB inst hits 82system.cpu.dtb.inst_misses 0 # ITB inst misses 83system.cpu.dtb.read_hits 0 # DTB read hits 84system.cpu.dtb.read_misses 0 # DTB read misses 85system.cpu.dtb.write_hits 0 # DTB write hits 86system.cpu.dtb.write_misses 0 # DTB write misses 87system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 88system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 89system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 90system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 91system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 92system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 93system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dtb.read_accesses 0 # DTB read accesses 97system.cpu.dtb.write_accesses 0 # DTB write accesses 98system.cpu.dtb.inst_accesses 0 # ITB inst accesses 99system.cpu.dtb.hits 0 # DTB hits 100system.cpu.dtb.misses 0 # DTB misses 101system.cpu.dtb.accesses 0 # DTB accesses 102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 111system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 112system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 113system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 114system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 115system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 116system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 133system.cpu.itb.walker.walks 0 # Table walker walks requested 134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 141system.cpu.itb.inst_hits 0 # ITB inst hits 142system.cpu.itb.inst_misses 0 # ITB inst misses 143system.cpu.itb.read_hits 0 # DTB read hits 144system.cpu.itb.read_misses 0 # DTB read misses 145system.cpu.itb.write_hits 0 # DTB write hits 146system.cpu.itb.write_misses 0 # DTB write misses 147system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 148system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 149system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 150system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 151system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 152system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 153system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 154system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 0 # ITB inst accesses 159system.cpu.itb.hits 0 # DTB hits 160system.cpu.itb.misses 0 # DTB misses 161system.cpu.itb.accesses 0 # DTB accesses	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.046047 # Number of seconds simulated 4sim_ticks 1046047111500 # Number of ticks simulated 5final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1255251 # Simulator instruction rate (inst/s) 8host_op_rate 1542152 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2053674689 # Simulator tick rate (ticks/s) 10host_mem_usage 277480 # Number of bytes of host memory used 11host_seconds 509.35 # Real time elapsed on the host 12sim_insts 639366787 # Number of instructions simulated 13sim_ops 785501035 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory 19system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 51system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 52system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 53system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 54system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 55system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 56system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 73system.cpu.dtb.walker.walks 0 # Table walker walks requested 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 81system.cpu.dtb.inst_hits 0 # ITB inst hits 82system.cpu.dtb.inst_misses 0 # ITB inst misses 83system.cpu.dtb.read_hits 0 # DTB read hits 84system.cpu.dtb.read_misses 0 # DTB read misses 85system.cpu.dtb.write_hits 0 # DTB write hits 86system.cpu.dtb.write_misses 0 # DTB write misses 87system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 88system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 89system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 90system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 91system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 92system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 93system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dtb.read_accesses 0 # DTB read accesses 97system.cpu.dtb.write_accesses 0 # DTB write accesses 98system.cpu.dtb.inst_accesses 0 # ITB inst accesses 99system.cpu.dtb.hits 0 # DTB hits 100system.cpu.dtb.misses 0 # DTB misses 101system.cpu.dtb.accesses 0 # DTB accesses 102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 111system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 112system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 113system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 114system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 115system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 116system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 133system.cpu.itb.walker.walks 0 # Table walker walks requested 134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 141system.cpu.itb.inst_hits 0 # ITB inst hits 142system.cpu.itb.inst_misses 0 # ITB inst misses 143system.cpu.itb.read_hits 0 # DTB read hits 144system.cpu.itb.read_misses 0 # DTB read misses 145system.cpu.itb.write_hits 0 # DTB write hits 146system.cpu.itb.write_misses 0 # DTB write misses 147system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 148system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 149system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 150system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 151system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 152system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 153system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 154system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 0 # ITB inst accesses 159system.cpu.itb.hits 0 # DTB hits 160system.cpu.itb.misses 0 # DTB misses 161system.cpu.itb.accesses 0 # DTB accesses
162system.cpu.workload.num_syscalls 673 # Number of system calls	162system.cpu.workload.numSyscalls 673 # Number of system calls
163system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states 164system.cpu.numCycles 2092094223 # number of cpu cycles simulated 165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 167system.cpu.committedInsts 639366787 # Number of instructions committed 168system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed 169system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses 170system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses 171system.cpu.num_func_calls 37261296 # number of times a function call or return occured 172system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls 173system.cpu.num_int_insts 682251400 # number of integer instructions 174system.cpu.num_fp_insts 24239771 # number of float instructions 175system.cpu.num_int_register_reads 1272307653 # number of times the integer registers were read 176system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written 177system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read 178system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written 179system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read 180system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written 181system.cpu.num_mem_refs 381221435 # number of memory refs 182system.cpu.num_load_insts 252240938 # Number of load instructions 183system.cpu.num_store_insts 128980497 # Number of store instructions 184system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 185system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles 186system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 187system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 188system.cpu.Branches 137364860 # Number of branches fetched 189system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 190system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction 191system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction 192system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction 193system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction 194system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction 195system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction 196system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction 197system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction 198system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction 199system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction 200system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction 201system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction 202system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction 203system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction 204system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction 205system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction 206system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction 207system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction 208system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction 209system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction 210system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction 211system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction 212system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction 213system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction 214system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction 215system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction 216system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction 217system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction 218system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction 219system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction 220system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction 221system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction 222system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction 223system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction 224system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction 225system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 226system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 227system.cpu.op_class::total 788730744 # Class of executed instruction 228system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 229system.cpu.dcache.tags.replacements 778046 # number of replacements 230system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use 231system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. 232system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. 233system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. 234system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit. 235system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor 236system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy 237system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy 238system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 239system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 240system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id 241system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id 242system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id 243system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id 244system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 245system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses 246system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses 247system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 248system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits 249system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits 250system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits 251system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits 252system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits 253system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits 254system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 255system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 256system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 257system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 258system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits 259system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits 260system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits 261system.cpu.dcache.overall_hits::total 378498833 # number of overall hits 262system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses 263system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses 264system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses 265system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses 266system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses 267system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses 268system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses 269system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses 270system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses 271system.cpu.dcache.overall_misses::total 782143 # number of overall misses 272system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles 273system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles 274system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles 275system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles 276system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles 277system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles 278system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles 279system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles 280system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) 281system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) 282system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 283system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 284system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) 285system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) 286system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 287system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 288system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 289system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 290system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses 291system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses 292system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses 293system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses 294system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses 295system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses 296system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses 297system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses 298system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses 299system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses 300system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses 301system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses 302system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses 303system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses 304system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency 305system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency 306system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency 307system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency 308system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency 309system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency 310system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency 311system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency 312system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 313system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 314system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 315system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 316system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 317system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 318system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks 319system.cpu.dcache.writebacks::total 88967 # number of writebacks 320system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 321system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 322system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 323system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 324system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 325system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 326system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses 327system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses 328system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses 329system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses 330system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 331system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 332system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses 333system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses 334system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses 335system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses 336system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles 337system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles 338system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles 339system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles 340system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles 341system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles 342system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles 343system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles 344system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles 345system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles 346system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 347system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 348system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 349system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 350system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses 351system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses 352system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 353system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 354system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 355system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 356system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency 357system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency 358system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency 359system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency 360system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency 361system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency 362system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency 363system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency 364system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency 365system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency 366system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 367system.cpu.icache.tags.replacements 8769 # number of replacements 368system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use 369system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. 370system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. 371system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. 372system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 373system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor 374system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy 375system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy 376system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id 377system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 378system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 379system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id 380system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id 381system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses 382system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses 383system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 384system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits 385system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits 386system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits 387system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits 388system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits 389system.cpu.icache.overall_hits::total 643367692 # number of overall hits 390system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses 391system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses 392system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses 393system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses 394system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses 395system.cpu.icache.overall_misses::total 10208 # number of overall misses 396system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles 397system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles 398system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles 399system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles 400system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles 401system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles 402system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) 403system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) 404system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses 405system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses 406system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses 407system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses 408system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses 409system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses 410system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses 411system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses 412system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses 413system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses 414system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency 415system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency 416system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency 417system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency 418system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency 419system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency 420system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 421system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 422system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 425system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 426system.cpu.icache.writebacks::writebacks 8769 # number of writebacks 427system.cpu.icache.writebacks::total 8769 # number of writebacks 428system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses 429system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses 430system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses 431system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses 432system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses 433system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses 434system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210621500 # number of ReadReq MSHR miss cycles 435system.cpu.icache.ReadReq_mshr_miss_latency::total 210621500 # number of ReadReq MSHR miss cycles 436system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210621500 # number of demand (read+write) MSHR miss cycles 437system.cpu.icache.demand_mshr_miss_latency::total 210621500 # number of demand (read+write) MSHR miss cycles 438system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210621500 # number of overall MSHR miss cycles 439system.cpu.icache.overall_mshr_miss_latency::total 210621500 # number of overall MSHR miss cycles 440system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses 441system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses 442system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses 443system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses 444system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 445system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 446system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20632.983934 # average ReadReq mshr miss latency 447system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20632.983934 # average ReadReq mshr miss latency 448system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency 449system.cpu.icache.demand_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency 450system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency 451system.cpu.icache.overall_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency 452system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 453system.cpu.l2cache.tags.replacements 257791 # number of replacements 454system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use 455system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks. 456system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks. 457system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks. 458system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit. 459system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor 460system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor 461system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor 462system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy 466system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id 470system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id 471system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id 472system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 473system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses 474system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses 475system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 476system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits 477system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits 478system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits 479system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits 480system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits 481system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits 482system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits 483system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits 484system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490296 # number of ReadSharedReq hits 485system.cpu.l2cache.ReadSharedReq_hits::total 490296 # number of ReadSharedReq hits 486system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits 487system.cpu.l2cache.demand_hits::cpu.data 493526 # number of demand (read+write) hits 488system.cpu.l2cache.demand_hits::total 501975 # number of demand (read+write) hits 489system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits 490system.cpu.l2cache.overall_hits::cpu.data 493526 # number of overall hits 491system.cpu.l2cache.overall_hits::total 501975 # number of overall hits 492system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses 493system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses 494system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses 495system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses 496system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222523 # number of ReadSharedReq misses 497system.cpu.l2cache.ReadSharedReq_misses::total 222523 # number of ReadSharedReq misses 498system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses 499system.cpu.l2cache.demand_misses::cpu.data 288616 # number of demand (read+write) misses 500system.cpu.l2cache.demand_misses::total 290375 # number of demand (read+write) misses 501system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses 502system.cpu.l2cache.overall_misses::cpu.data 288616 # number of overall misses 503system.cpu.l2cache.overall_misses::total 290375 # number of overall misses 504system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500 # number of ReadExReq miss cycles 505system.cpu.l2cache.ReadExReq_miss_latency::total 3998679500 # number of ReadExReq miss cycles 506system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles 507system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles 508system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles 509system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles 510system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles 511system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles 512system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles 513system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles 514system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles 515system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles 516system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses) 517system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses) 518system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) 519system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) 520system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) 521system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) 522system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) 523system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses) 524system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses) 525system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses) 526system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses 527system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses 528system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses 529system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses 530system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses 531system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses 532system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses 533system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses 534system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses 535system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses 536system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses 537system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses 538system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses 539system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses 540system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses 541system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses 542system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses 543system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses 544system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency 545system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency 546system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency 547system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency 548system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency 549system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency 550system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency 551system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency 552system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency 553system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency 554system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency 555system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency 556system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 559system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 561system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 562system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 563system.cpu.l2cache.writebacks::total 66098 # number of writebacks 564system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses 565system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses 566system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses 567system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses 568system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses 569system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses 570system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses 571system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses 572system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses 573system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses 574system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses 575system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses 576system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles 577system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles 578system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles 579system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles 580system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles 581system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles 582system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles 583system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles 584system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles 585system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles 586system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles 587system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles 588system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses 589system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses 590system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses 591system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses 592system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses 593system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses 594system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses 595system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses 596system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses 597system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses 598system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses 599system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses 600system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency 601system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency 602system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency 603system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency 604system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency 605system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency 606system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency 607system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency 608system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency 609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency 610system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency 611system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency 612system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. 613system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. 614system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 615system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter. 616system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 617system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 618system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 619system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution 620system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution 621system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution 622system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution 627system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) 628system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) 629system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) 630system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) 631system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes) 632system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes) 633system.cpu.toL2Bus.snoops 257791 # Total snoops (count) 634system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) 635system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram 636system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram 637system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram 638system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 639system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram 640system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram 641system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram 642system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 643system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 644system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 645system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram 646system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks) 647system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 648system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) 649system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 650system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) 651system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 652system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter. 653system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data. 654system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 655system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 656system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 657system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 658system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 659system.membus.trans_dist::ReadResp 224282 # Transaction distribution 660system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 661system.membus.trans_dist::CleanEvict 190103 # Transaction distribution 662system.membus.trans_dist::ReadExReq 66093 # Transaction distribution 663system.membus.trans_dist::ReadExResp 66093 # Transaction distribution 664system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution 665system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes) 666system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes) 667system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes) 668system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes) 669system.membus.snoops 0 # Total snoops (count) 670system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 671system.membus.snoop_fanout::samples 290376 # Request fanout histogram 672system.membus.snoop_fanout::mean 0 # Request fanout histogram 673system.membus.snoop_fanout::stdev 0 # Request fanout histogram 674system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 675system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram 676system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 677system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 678system.membus.snoop_fanout::min_value 0 # Request fanout histogram 679system.membus.snoop_fanout::max_value 0 # Request fanout histogram 680system.membus.snoop_fanout::total 290376 # Request fanout histogram 681system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks) 682system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 683system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks) 684system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 685 686---------- End Simulation Statistics ----------	163system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states 164system.cpu.numCycles 2092094223 # number of cpu cycles simulated 165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 167system.cpu.committedInsts 639366787 # Number of instructions committed 168system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed 169system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses 170system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses 171system.cpu.num_func_calls 37261296 # number of times a function call or return occured 172system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls 173system.cpu.num_int_insts 682251400 # number of integer instructions 174system.cpu.num_fp_insts 24239771 # number of float instructions 175system.cpu.num_int_register_reads 1272307653 # number of times the integer registers were read 176system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written 177system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read 178system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written 179system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read 180system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written 181system.cpu.num_mem_refs 381221435 # number of memory refs 182system.cpu.num_load_insts 252240938 # Number of load instructions 183system.cpu.num_store_insts 128980497 # Number of store instructions 184system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 185system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles 186system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 187system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 188system.cpu.Branches 137364860 # Number of branches fetched 189system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 190system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction 191system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction 192system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction 193system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction 194system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction 195system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction 196system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction 197system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction 198system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction 199system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction 200system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction 201system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction 202system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction 203system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction 204system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction 205system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction 206system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction 207system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction 208system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction 209system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction 210system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction 211system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction 212system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction 213system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction 214system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction 215system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction 216system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction 217system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction 218system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction 219system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction 220system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction 221system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction 222system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction 223system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction 224system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction 225system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 226system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 227system.cpu.op_class::total 788730744 # Class of executed instruction 228system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 229system.cpu.dcache.tags.replacements 778046 # number of replacements 230system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use 231system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. 232system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. 233system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. 234system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit. 235system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor 236system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy 237system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy 238system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 239system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 240system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id 241system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id 242system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id 243system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id 244system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 245system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses 246system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses 247system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 248system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits 249system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits 250system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits 251system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits 252system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits 253system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits 254system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 255system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 256system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 257system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 258system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits 259system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits 260system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits 261system.cpu.dcache.overall_hits::total 378498833 # number of overall hits 262system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses 263system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses 264system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses 265system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses 266system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses 267system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses 268system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses 269system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses 270system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses 271system.cpu.dcache.overall_misses::total 782143 # number of overall misses 272system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles 273system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles 274system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles 275system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles 276system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles 277system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles 278system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles 279system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles 280system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) 281system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) 282system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 283system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 284system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) 285system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) 286system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 287system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 288system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 289system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 290system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses 291system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses 292system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses 293system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses 294system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses 295system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses 296system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses 297system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses 298system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses 299system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses 300system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses 301system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses 302system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses 303system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses 304system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency 305system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency 306system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency 307system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency 308system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency 309system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency 310system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency 311system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency 312system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 313system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 314system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 315system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 316system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 317system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 318system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks 319system.cpu.dcache.writebacks::total 88967 # number of writebacks 320system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 321system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 322system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 323system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 324system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 325system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 326system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses 327system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses 328system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses 329system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses 330system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 331system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 332system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses 333system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses 334system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses 335system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses 336system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles 337system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles 338system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles 339system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles 340system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles 341system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles 342system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles 343system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles 344system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles 345system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles 346system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 347system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 348system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 349system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 350system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses 351system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses 352system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 353system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 354system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 355system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 356system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency 357system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency 358system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency 359system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency 360system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency 361system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency 362system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency 363system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency 364system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency 365system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency 366system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 367system.cpu.icache.tags.replacements 8769 # number of replacements 368system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use 369system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. 370system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. 371system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. 372system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 373system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor 374system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy 375system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy 376system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id 377system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 378system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 379system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id 380system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id 381system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses 382system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses 383system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 384system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits 385system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits 386system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits 387system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits 388system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits 389system.cpu.icache.overall_hits::total 643367692 # number of overall hits 390system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses 391system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses 392system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses 393system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses 394system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses 395system.cpu.icache.overall_misses::total 10208 # number of overall misses 396system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles 397system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles 398system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles 399system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles 400system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles 401system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles 402system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) 403system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) 404system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses 405system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses 406system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses 407system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses 408system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses 409system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses 410system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses 411system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses 412system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses 413system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses 414system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency 415system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency 416system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency 417system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency 418system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency 419system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency 420system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 421system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 422system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 425system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 426system.cpu.icache.writebacks::writebacks 8769 # number of writebacks 427system.cpu.icache.writebacks::total 8769 # number of writebacks 428system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses 429system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses 430system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses 431system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses 432system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses 433system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses 434system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210621500 # number of ReadReq MSHR miss cycles 435system.cpu.icache.ReadReq_mshr_miss_latency::total 210621500 # number of ReadReq MSHR miss cycles 436system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210621500 # number of demand (read+write) MSHR miss cycles 437system.cpu.icache.demand_mshr_miss_latency::total 210621500 # number of demand (read+write) MSHR miss cycles 438system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210621500 # number of overall MSHR miss cycles 439system.cpu.icache.overall_mshr_miss_latency::total 210621500 # number of overall MSHR miss cycles 440system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses 441system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses 442system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses 443system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses 444system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 445system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 446system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20632.983934 # average ReadReq mshr miss latency 447system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20632.983934 # average ReadReq mshr miss latency 448system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency 449system.cpu.icache.demand_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency 450system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency 451system.cpu.icache.overall_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency 452system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 453system.cpu.l2cache.tags.replacements 257791 # number of replacements 454system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use 455system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks. 456system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks. 457system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks. 458system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit. 459system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor 460system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor 461system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor 462system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy 466system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id 470system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id 471system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id 472system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 473system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses 474system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses 475system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 476system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits 477system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits 478system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits 479system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits 480system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits 481system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits 482system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits 483system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits 484system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490296 # number of ReadSharedReq hits 485system.cpu.l2cache.ReadSharedReq_hits::total 490296 # number of ReadSharedReq hits 486system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits 487system.cpu.l2cache.demand_hits::cpu.data 493526 # number of demand (read+write) hits 488system.cpu.l2cache.demand_hits::total 501975 # number of demand (read+write) hits 489system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits 490system.cpu.l2cache.overall_hits::cpu.data 493526 # number of overall hits 491system.cpu.l2cache.overall_hits::total 501975 # number of overall hits 492system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses 493system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses 494system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses 495system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses 496system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222523 # number of ReadSharedReq misses 497system.cpu.l2cache.ReadSharedReq_misses::total 222523 # number of ReadSharedReq misses 498system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses 499system.cpu.l2cache.demand_misses::cpu.data 288616 # number of demand (read+write) misses 500system.cpu.l2cache.demand_misses::total 290375 # number of demand (read+write) misses 501system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses 502system.cpu.l2cache.overall_misses::cpu.data 288616 # number of overall misses 503system.cpu.l2cache.overall_misses::total 290375 # number of overall misses 504system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500 # number of ReadExReq miss cycles 505system.cpu.l2cache.ReadExReq_miss_latency::total 3998679500 # number of ReadExReq miss cycles 506system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles 507system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles 508system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles 509system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles 510system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles 511system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles 512system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles 513system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles 514system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles 515system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles 516system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses) 517system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses) 518system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) 519system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) 520system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) 521system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) 522system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) 523system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses) 524system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses) 525system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses) 526system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses 527system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses 528system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses 529system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses 530system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses 531system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses 532system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses 533system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses 534system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses 535system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses 536system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses 537system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses 538system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses 539system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses 540system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses 541system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses 542system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses 543system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses 544system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency 545system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency 546system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency 547system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency 548system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency 549system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency 550system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency 551system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency 552system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency 553system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency 554system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency 555system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency 556system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 559system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 561system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 562system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 563system.cpu.l2cache.writebacks::total 66098 # number of writebacks 564system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses 565system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses 566system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses 567system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses 568system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses 569system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses 570system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses 571system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses 572system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses 573system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses 574system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses 575system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses 576system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles 577system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles 578system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles 579system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles 580system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles 581system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles 582system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles 583system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles 584system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles 585system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles 586system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles 587system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles 588system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses 589system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses 590system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses 591system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses 592system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses 593system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses 594system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses 595system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses 596system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses 597system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses 598system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses 599system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses 600system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency 601system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency 602system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency 603system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency 604system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency 605system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency 606system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency 607system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency 608system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency 609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency 610system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency 611system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency 612system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. 613system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. 614system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 615system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter. 616system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 617system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 618system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 619system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution 620system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution 621system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution 622system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution 627system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) 628system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) 629system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) 630system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) 631system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes) 632system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes) 633system.cpu.toL2Bus.snoops 257791 # Total snoops (count) 634system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) 635system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram 636system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram 637system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram 638system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 639system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram 640system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram 641system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram 642system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 643system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 644system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 645system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram 646system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks) 647system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 648system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) 649system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 650system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) 651system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 652system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter. 653system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data. 654system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 655system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 656system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 657system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 658system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states 659system.membus.trans_dist::ReadResp 224282 # Transaction distribution 660system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 661system.membus.trans_dist::CleanEvict 190103 # Transaction distribution 662system.membus.trans_dist::ReadExReq 66093 # Transaction distribution 663system.membus.trans_dist::ReadExResp 66093 # Transaction distribution 664system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution 665system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes) 666system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes) 667system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes) 668system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes) 669system.membus.snoops 0 # Total snoops (count) 670system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 671system.membus.snoop_fanout::samples 290376 # Request fanout histogram 672system.membus.snoop_fanout::mean 0 # Request fanout histogram 673system.membus.snoop_fanout::stdev 0 # Request fanout histogram 674system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 675system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram 676system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 677system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 678system.membus.snoop_fanout::min_value 0 # Request fanout histogram 679system.membus.snoop_fanout::max_value 0 # Request fanout histogram 680system.membus.snoop_fanout::total 290376 # Request fanout histogram 681system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks) 682system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 683system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks) 684system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 685 686---------- End Simulation Statistics ----------