1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.043695 # Number of seconds simulated
4sim_ticks 1043695084000 # Number of ticks simulated
5final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.043695 # Number of seconds simulated
4sim_ticks 1043695084000 # Number of ticks simulated
5final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 520727 # Simulator instruction rate (inst/s)
8host_op_rate 639745 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 850028397 # Simulator tick rate (ticks/s)
10host_mem_usage 259968 # Number of bytes of host memory used
11host_seconds 1227.84 # Real time elapsed on the host
| 7host_inst_rate 974812 # Simulator instruction rate (inst/s)
8host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1591272225 # Simulator tick rate (ticks/s)
10host_mem_usage 314196 # Number of bytes of host memory used
11host_seconds 655.89 # Real time elapsed on the host
|
12sim_insts 639366786 # Number of instructions simulated
13sim_ops 785501034 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory
18system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s)
| 12sim_insts 639366786 # Number of instructions simulated
13sim_ops 785501034 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory
18system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s)
|
39system.membus.throughput 21818480 # Throughput (bytes/s)
| |
40system.membus.trans_dist::ReadReq 223619 # Transaction distribution
41system.membus.trans_dist::ReadResp 223619 # Transaction distribution
42system.membus.trans_dist::Writeback 66098 # Transaction distribution
43system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
44system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes)
46system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes)
| 39system.membus.trans_dist::ReadReq 223619 # Transaction distribution
40system.membus.trans_dist::ReadResp 223619 # Transaction distribution
41system.membus.trans_dist::Writeback 66098 # Transaction distribution
42system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
43system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes)
45system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes)
|
47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes)
48system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes)
49system.membus.data_through_bus 22771840 # Total data (bytes)
50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
| 46system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes)
47system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes)
48system.membus.snoops 0 # Total snoops (count)
49system.membus.snoop_fanout::samples 355811 # Request fanout histogram
50system.membus.snoop_fanout::mean 0 # Request fanout histogram
51system.membus.snoop_fanout::stdev 0 # Request fanout histogram
52system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
53system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram
54system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
55system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
56system.membus.snoop_fanout::min_value 0 # Request fanout histogram
57system.membus.snoop_fanout::max_value 0 # Request fanout histogram
58system.membus.snoop_fanout::total 355811 # Request fanout histogram
|
51system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks)
52system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
53system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks)
54system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
55system.cpu_clk_domain.clock 500 # Clock period in ticks
56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
77system.cpu.dtb.inst_hits 0 # ITB inst hits
78system.cpu.dtb.inst_misses 0 # ITB inst misses
79system.cpu.dtb.read_hits 0 # DTB read hits
80system.cpu.dtb.read_misses 0 # DTB read misses
81system.cpu.dtb.write_hits 0 # DTB write hits
82system.cpu.dtb.write_misses 0 # DTB write misses
83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
92system.cpu.dtb.read_accesses 0 # DTB read accesses
93system.cpu.dtb.write_accesses 0 # DTB write accesses
94system.cpu.dtb.inst_accesses 0 # ITB inst accesses
95system.cpu.dtb.hits 0 # DTB hits
96system.cpu.dtb.misses 0 # DTB misses
97system.cpu.dtb.accesses 0 # DTB accesses
98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
119system.cpu.itb.inst_hits 0 # ITB inst hits
120system.cpu.itb.inst_misses 0 # ITB inst misses
121system.cpu.itb.read_hits 0 # DTB read hits
122system.cpu.itb.read_misses 0 # DTB read misses
123system.cpu.itb.write_hits 0 # DTB write hits
124system.cpu.itb.write_misses 0 # DTB write misses
125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
134system.cpu.itb.read_accesses 0 # DTB read accesses
135system.cpu.itb.write_accesses 0 # DTB write accesses
136system.cpu.itb.inst_accesses 0 # ITB inst accesses
137system.cpu.itb.hits 0 # DTB hits
138system.cpu.itb.misses 0 # DTB misses
139system.cpu.itb.accesses 0 # DTB accesses
140system.cpu.workload.num_syscalls 673 # Number of system calls
141system.cpu.numCycles 2087390168 # number of cpu cycles simulated
142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
144system.cpu.committedInsts 639366786 # Number of instructions committed
145system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed
146system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
147system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
148system.cpu.num_func_calls 37261296 # number of times a function call or return occured
149system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
150system.cpu.num_int_insts 682251400 # number of integer instructions
151system.cpu.num_fp_insts 24239771 # number of float instructions
152system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read
153system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
154system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
155system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
156system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read
157system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
158system.cpu.num_mem_refs 381221435 # number of memory refs
159system.cpu.num_load_insts 252240938 # Number of load instructions
160system.cpu.num_store_insts 128980497 # Number of store instructions
161system.cpu.num_idle_cycles 0 # Number of idle cycles
162system.cpu.num_busy_cycles 2087390168 # Number of busy cycles
163system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
164system.cpu.idle_fraction 0 # Percentage of idle cycles
165system.cpu.Branches 137364859 # Number of branches fetched
166system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
167system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction
168system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
169system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
170system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
171system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
172system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
173system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
174system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
175system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
176system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
177system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
178system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
179system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
180system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
181system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
182system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
183system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
184system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
185system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
186system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
187system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
188system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
189system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
190system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
191system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
192system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
193system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
194system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
195system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
196system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
197system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
198system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
199system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
200system.cpu.op_class::total 788730743 # Class of executed instruction
201system.cpu.icache.tags.replacements 8769 # number of replacements
202system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use
203system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks.
204system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
205system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks.
206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
207system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor
208system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
209system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
210system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
211system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
212system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
213system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
214system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
215system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses
216system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses
217system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits
218system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits
219system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits
220system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits
221system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits
222system.cpu.icache.overall_hits::total 643367691 # number of overall hits
223system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
224system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
225system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
226system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
227system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
228system.cpu.icache.overall_misses::total 10208 # number of overall misses
229system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles
230system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles
231system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles
232system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles
233system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles
234system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles
235system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses)
236system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses)
237system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses
238system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses
239system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses
240system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses
241system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
242system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
243system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
244system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
245system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
246system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
247system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency
248system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency
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251system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency
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258system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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263system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses
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268system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles
269system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles
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271system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles
272system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles
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274system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
275system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
276system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
277system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
278system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
279system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency
280system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency
281system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
282system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
283system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
284system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
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287system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use
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289system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks.
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293system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor
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302system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
303system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id
304system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id
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312system.cpu.l2cache.Writeback_hits::total 91561 # number of Writeback hits
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347system.cpu.l2cache.Writeback_accesses::total 91561 # number of Writeback accesses(hits+misses)
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387system.cpu.l2cache.writebacks::total 66098 # number of writebacks
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499system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses
500system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses
501system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses
502system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses
503system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses
504system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
505system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
506system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
507system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency
508system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency
509system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency
510system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency
511system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency
512system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency
513system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency
514system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency
515system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
516system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
517system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
518system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
519system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
520system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
521system.cpu.dcache.fast_writes 0 # number of fast writes performed
522system.cpu.dcache.cache_copies 0 # number of cache copies performed
523system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks
524system.cpu.dcache.writebacks::total 91561 # number of writebacks
525system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
526system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
527system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
528system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
529system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
530system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
531system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses
532system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses
533system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses
534system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
535system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
536system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
537system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses
538system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
539system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
540system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
541system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles
542system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles
543system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles
544system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles
545system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles
546system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles
547system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles
548system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles
549system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles
550system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles
551system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
552system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
553system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
554system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
555system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses
556system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses
557system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
558system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
559system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
560system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency
562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency
563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency
564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency
565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency
566system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency
567system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency
568system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency
569system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency
570system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency
571system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 59system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks)
60system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
61system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks)
62system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
63system.cpu_clk_domain.clock 500 # Clock period in ticks
64system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
65system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
66system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
67system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
68system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
69system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
70system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
71system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
72system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
73system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
74system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
75system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
76system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
77system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
78system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
79system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
80system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
81system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
82system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
83system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
84system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
85system.cpu.dtb.inst_hits 0 # ITB inst hits
86system.cpu.dtb.inst_misses 0 # ITB inst misses
87system.cpu.dtb.read_hits 0 # DTB read hits
88system.cpu.dtb.read_misses 0 # DTB read misses
89system.cpu.dtb.write_hits 0 # DTB write hits
90system.cpu.dtb.write_misses 0 # DTB write misses
91system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
92system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
93system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
94system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
95system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
96system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
97system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
98system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
99system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
100system.cpu.dtb.read_accesses 0 # DTB read accesses
101system.cpu.dtb.write_accesses 0 # DTB write accesses
102system.cpu.dtb.inst_accesses 0 # ITB inst accesses
103system.cpu.dtb.hits 0 # DTB hits
104system.cpu.dtb.misses 0 # DTB misses
105system.cpu.dtb.accesses 0 # DTB accesses
106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
127system.cpu.itb.inst_hits 0 # ITB inst hits
128system.cpu.itb.inst_misses 0 # ITB inst misses
129system.cpu.itb.read_hits 0 # DTB read hits
130system.cpu.itb.read_misses 0 # DTB read misses
131system.cpu.itb.write_hits 0 # DTB write hits
132system.cpu.itb.write_misses 0 # DTB write misses
133system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
134system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
135system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
136system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
137system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
138system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
139system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
140system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
141system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
142system.cpu.itb.read_accesses 0 # DTB read accesses
143system.cpu.itb.write_accesses 0 # DTB write accesses
144system.cpu.itb.inst_accesses 0 # ITB inst accesses
145system.cpu.itb.hits 0 # DTB hits
146system.cpu.itb.misses 0 # DTB misses
147system.cpu.itb.accesses 0 # DTB accesses
148system.cpu.workload.num_syscalls 673 # Number of system calls
149system.cpu.numCycles 2087390168 # number of cpu cycles simulated
150system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
151system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
152system.cpu.committedInsts 639366786 # Number of instructions committed
153system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed
154system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
155system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
156system.cpu.num_func_calls 37261296 # number of times a function call or return occured
157system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
158system.cpu.num_int_insts 682251400 # number of integer instructions
159system.cpu.num_fp_insts 24239771 # number of float instructions
160system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read
161system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
162system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
163system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
164system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read
165system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
166system.cpu.num_mem_refs 381221435 # number of memory refs
167system.cpu.num_load_insts 252240938 # Number of load instructions
168system.cpu.num_store_insts 128980497 # Number of store instructions
169system.cpu.num_idle_cycles 0 # Number of idle cycles
170system.cpu.num_busy_cycles 2087390168 # Number of busy cycles
171system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
172system.cpu.idle_fraction 0 # Percentage of idle cycles
173system.cpu.Branches 137364859 # Number of branches fetched
174system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
175system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction
176system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
177system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
178system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
179system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
180system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
181system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
182system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
183system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
184system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
185system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
186system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
187system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
188system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
189system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
190system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
191system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
192system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
193system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
194system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
195system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
196system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
197system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
198system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
199system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
200system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
201system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
202system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
203system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
204system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
205system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
206system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
207system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::total 788730743 # Class of executed instruction
209system.cpu.icache.tags.replacements 8769 # number of replacements
210system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use
211system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks.
212system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
213system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks.
214system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
215system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor
216system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
217system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
218system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
219system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
220system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
221system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
222system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
223system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses
224system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses
225system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits
226system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits
227system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits
228system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits
229system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits
230system.cpu.icache.overall_hits::total 643367691 # number of overall hits
231system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
232system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
233system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
234system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
235system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
236system.cpu.icache.overall_misses::total 10208 # number of overall misses
237system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles
238system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles
239system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles
240system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles
241system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles
242system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles
243system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses)
244system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses)
245system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses
246system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses
247system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses
248system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses
249system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
250system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
251system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
252system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
253system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
254system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
255system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency
256system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency
257system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency
258system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency
259system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency
260system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency
261system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
262system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
263system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
264system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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266system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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274system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
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276system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles
277system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles
278system.cpu.icache.demand_mshr_miss_latency::total 186706500 # number of demand (read+write) MSHR miss cycles
279system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles
280system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles
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282system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
283system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
284system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
285system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
286system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
287system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency
288system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency
289system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
290system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
291system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
292system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
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295system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use
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297system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks.
298system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks.
299system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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301system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor
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308system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
309system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
310system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
311system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id
312system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id
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315system.cpu.l2cache.tags.data_accesses 7430286 # Number of data accesses
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318system.cpu.l2cache.ReadReq_hits::total 499408 # number of ReadReq hits
319system.cpu.l2cache.Writeback_hits::writebacks 91561 # number of Writeback hits
320system.cpu.l2cache.Writeback_hits::total 91561 # number of Writeback hits
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322system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits
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355system.cpu.l2cache.Writeback_accesses::total 91561 # number of Writeback accesses(hits+misses)
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514system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
515system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency
516system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency
517system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency
518system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency
519system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency
520system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency
521system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency
522system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency
523system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
524system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
525system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
526system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
527system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
528system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
529system.cpu.dcache.fast_writes 0 # number of fast writes performed
530system.cpu.dcache.cache_copies 0 # number of cache copies performed
531system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks
532system.cpu.dcache.writebacks::total 91561 # number of writebacks
533system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
534system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
535system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
536system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
537system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
538system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
539system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses
540system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses
541system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses
542system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
543system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
544system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
545system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses
546system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
547system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
548system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
549system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles
550system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles
551system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles
552system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles
553system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles
554system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles
555system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles
556system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles
557system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles
558system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles
559system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
560system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
561system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
562system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
563system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses
564system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses
565system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
566system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
567system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
568system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
569system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency
570system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency
571system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency
572system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency
573system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency
574system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency
575system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency
576system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency
577system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency
578system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency
579system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
572system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s)
| |
573system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution
574system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
575system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution
576system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
577system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
578system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes)
579system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes)
580system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes)
| 580system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution
581system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
582system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution
583system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
584system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
585system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes)
586system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes)
587system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes)
|
581system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
582system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes)
583system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
584system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes)
585system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
| 588system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
589system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes)
590system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
591system.cpu.toL2Bus.snoops 0 # Total snoops (count)
592system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram
593system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
594system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
595system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
596system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
597system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
598system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
599system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
600system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
601system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram
602system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
603system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
604system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
605system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
606system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram
|
586system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
587system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
588system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
589system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
590system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
591system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
592
593---------- End Simulation Statistics ----------
| 607system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
608system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
609system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
610system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
611system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
612system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
613
614---------- End Simulation Statistics ----------
|