| config.ini (9885:afd9ea6101d9) | config.ini (10036:80e84beef3bb) |
|---|---|
| 1[root] 2type=Root 3children=system | 1[root] 2type=Root 3children=system |
| 4eventq_index=0 |
|
| 4full_system=false | 5full_system=false |
| 6sim_quantum=0 |
|
| 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain | 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17eventq_index=0 |
|
| 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= --- 5 unchanged lines hidden (view full) --- 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 | 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= --- 5 unchanged lines hidden (view full) --- 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 |
| 39eventq_index=0 |
|
| 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=TimingSimpleCPU 40children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 41checker=Null 42clk_domain=system.cpu_clk_domain 43cpu_id=0 44do_checkpoint_insts=true 45do_quiesce=true 46do_statistics_insts=true 47dtb=system.cpu.dtb | 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=TimingSimpleCPU 44children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 45checker=Null 46clk_domain=system.cpu_clk_domain 47cpu_id=0 48do_checkpoint_insts=true 49do_quiesce=true 50do_statistics_insts=true 51dtb=system.cpu.dtb |
| 52eventq_index=0 |
|
| 48function_trace=false 49function_trace_start=0 50interrupts=system.cpu.interrupts 51isa=system.cpu.isa 52itb=system.cpu.itb 53max_insts_all_threads=0 54max_insts_any_thread=0 55max_loads_all_threads=0 --- 10 unchanged lines hidden (view full) --- 66icache_port=system.cpu.icache.cpu_side 67 68[system.cpu.dcache] 69type=BaseCache 70children=tags 71addr_ranges=0:18446744073709551615 72assoc=2 73clk_domain=system.cpu_clk_domain | 53function_trace=false 54function_trace_start=0 55interrupts=system.cpu.interrupts 56isa=system.cpu.isa 57itb=system.cpu.itb 58max_insts_all_threads=0 59max_insts_any_thread=0 60max_loads_all_threads=0 --- 10 unchanged lines hidden (view full) --- 71icache_port=system.cpu.icache.cpu_side 72 73[system.cpu.dcache] 74type=BaseCache 75children=tags 76addr_ranges=0:18446744073709551615 77assoc=2 78clk_domain=system.cpu_clk_domain |
| 79eventq_index=0 |
|
| 74forward_snoops=true 75hit_latency=2 76is_top_level=true 77max_miss_count=0 78mshrs=4 79prefetch_on_access=false 80prefetcher=Null 81response_latency=2 | 80forward_snoops=true 81hit_latency=2 82is_top_level=true 83max_miss_count=0 84mshrs=4 85prefetch_on_access=false 86prefetcher=Null 87response_latency=2 |
| 88sequential_access=false |
|
| 82size=262144 83system=system 84tags=system.cpu.dcache.tags 85tgts_per_mshr=20 86two_queue=false 87write_buffers=8 88cpu_side=system.cpu.dcache_port 89mem_side=system.cpu.toL2Bus.slave[1] 90 91[system.cpu.dcache.tags] 92type=LRU 93assoc=2 94block_size=64 95clk_domain=system.cpu_clk_domain | 89size=262144 90system=system 91tags=system.cpu.dcache.tags 92tgts_per_mshr=20 93two_queue=false 94write_buffers=8 95cpu_side=system.cpu.dcache_port 96mem_side=system.cpu.toL2Bus.slave[1] 97 98[system.cpu.dcache.tags] 99type=LRU 100assoc=2 101block_size=64 102clk_domain=system.cpu_clk_domain |
| 103eventq_index=0 |
|
| 96hit_latency=2 | 104hit_latency=2 |
| 105sequential_access=false |
|
| 97size=262144 98 99[system.cpu.dtb] 100type=ArmTLB 101children=walker | 106size=262144 107 108[system.cpu.dtb] 109type=ArmTLB 110children=walker |
| 111eventq_index=0 |
|
| 102size=64 103walker=system.cpu.dtb.walker 104 105[system.cpu.dtb.walker] 106type=ArmTableWalker 107clk_domain=system.cpu_clk_domain | 112size=64 113walker=system.cpu.dtb.walker 114 115[system.cpu.dtb.walker] 116type=ArmTableWalker 117clk_domain=system.cpu_clk_domain |
| 118eventq_index=0 |
|
| 108num_squash_per_cycle=2 109sys=system 110port=system.cpu.toL2Bus.slave[3] 111 112[system.cpu.icache] 113type=BaseCache 114children=tags 115addr_ranges=0:18446744073709551615 116assoc=2 117clk_domain=system.cpu_clk_domain | 119num_squash_per_cycle=2 120sys=system 121port=system.cpu.toL2Bus.slave[3] 122 123[system.cpu.icache] 124type=BaseCache 125children=tags 126addr_ranges=0:18446744073709551615 127assoc=2 128clk_domain=system.cpu_clk_domain |
| 129eventq_index=0 |
|
| 118forward_snoops=true 119hit_latency=2 120is_top_level=true 121max_miss_count=0 122mshrs=4 123prefetch_on_access=false 124prefetcher=Null 125response_latency=2 | 130forward_snoops=true 131hit_latency=2 132is_top_level=true 133max_miss_count=0 134mshrs=4 135prefetch_on_access=false 136prefetcher=Null 137response_latency=2 |
| 138sequential_access=false |
|
| 126size=131072 127system=system 128tags=system.cpu.icache.tags 129tgts_per_mshr=20 130two_queue=false 131write_buffers=8 132cpu_side=system.cpu.icache_port 133mem_side=system.cpu.toL2Bus.slave[0] 134 135[system.cpu.icache.tags] 136type=LRU 137assoc=2 138block_size=64 139clk_domain=system.cpu_clk_domain | 139size=131072 140system=system 141tags=system.cpu.icache.tags 142tgts_per_mshr=20 143two_queue=false 144write_buffers=8 145cpu_side=system.cpu.icache_port 146mem_side=system.cpu.toL2Bus.slave[0] 147 148[system.cpu.icache.tags] 149type=LRU 150assoc=2 151block_size=64 152clk_domain=system.cpu_clk_domain |
| 153eventq_index=0 |
|
| 140hit_latency=2 | 154hit_latency=2 |
| 155sequential_access=false |
|
| 141size=131072 142 143[system.cpu.interrupts] 144type=ArmInterrupts | 156size=131072 157 158[system.cpu.interrupts] 159type=ArmInterrupts |
| 160eventq_index=0 |
|
| 145 146[system.cpu.isa] 147type=ArmISA | 161 162[system.cpu.isa] 163type=ArmISA |
| 164eventq_index=0 |
|
| 148fpsid=1090793632 149id_isar0=34607377 150id_isar1=34677009 151id_isar2=555950401 152id_isar3=17899825 153id_isar4=268501314 154id_isar5=0 155id_mmfr0=3 156id_mmfr1=0 157id_mmfr2=19070976 158id_mmfr3=4027589137 159id_pfr0=49 160id_pfr1=1 161midr=890224640 162 163[system.cpu.itb] 164type=ArmTLB 165children=walker | 165fpsid=1090793632 166id_isar0=34607377 167id_isar1=34677009 168id_isar2=555950401 169id_isar3=17899825 170id_isar4=268501314 171id_isar5=0 172id_mmfr0=3 173id_mmfr1=0 174id_mmfr2=19070976 175id_mmfr3=4027589137 176id_pfr0=49 177id_pfr1=1 178midr=890224640 179 180[system.cpu.itb] 181type=ArmTLB 182children=walker |
| 183eventq_index=0 |
|
| 166size=64 167walker=system.cpu.itb.walker 168 169[system.cpu.itb.walker] 170type=ArmTableWalker 171clk_domain=system.cpu_clk_domain | 184size=64 185walker=system.cpu.itb.walker 186 187[system.cpu.itb.walker] 188type=ArmTableWalker 189clk_domain=system.cpu_clk_domain |
| 190eventq_index=0 |
|
| 172num_squash_per_cycle=2 173sys=system 174port=system.cpu.toL2Bus.slave[2] 175 176[system.cpu.l2cache] 177type=BaseCache 178children=tags 179addr_ranges=0:18446744073709551615 180assoc=8 181clk_domain=system.cpu_clk_domain | 191num_squash_per_cycle=2 192sys=system 193port=system.cpu.toL2Bus.slave[2] 194 195[system.cpu.l2cache] 196type=BaseCache 197children=tags 198addr_ranges=0:18446744073709551615 199assoc=8 200clk_domain=system.cpu_clk_domain |
| 201eventq_index=0 |
|
| 182forward_snoops=true 183hit_latency=20 184is_top_level=false 185max_miss_count=0 186mshrs=20 187prefetch_on_access=false 188prefetcher=Null 189response_latency=20 | 202forward_snoops=true 203hit_latency=20 204is_top_level=false 205max_miss_count=0 206mshrs=20 207prefetch_on_access=false 208prefetcher=Null 209response_latency=20 |
| 210sequential_access=false |
|
| 190size=2097152 191system=system 192tags=system.cpu.l2cache.tags 193tgts_per_mshr=12 194two_queue=false 195write_buffers=8 196cpu_side=system.cpu.toL2Bus.master[0] 197mem_side=system.membus.slave[1] 198 199[system.cpu.l2cache.tags] 200type=LRU 201assoc=8 202block_size=64 203clk_domain=system.cpu_clk_domain | 211size=2097152 212system=system 213tags=system.cpu.l2cache.tags 214tgts_per_mshr=12 215two_queue=false 216write_buffers=8 217cpu_side=system.cpu.toL2Bus.master[0] 218mem_side=system.membus.slave[1] 219 220[system.cpu.l2cache.tags] 221type=LRU 222assoc=8 223block_size=64 224clk_domain=system.cpu_clk_domain |
| 225eventq_index=0 |
|
| 204hit_latency=20 | 226hit_latency=20 |
| 227sequential_access=false |
|
| 205size=2097152 206 207[system.cpu.toL2Bus] 208type=CoherentBus 209clk_domain=system.cpu_clk_domain | 228size=2097152 229 230[system.cpu.toL2Bus] 231type=CoherentBus 232clk_domain=system.cpu_clk_domain |
| 233eventq_index=0 |
|
| 210header_cycles=1 211system=system 212use_default_range=false 213width=32 214master=system.cpu.l2cache.cpu_side 215slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 216 217[system.cpu.tracer] 218type=ExeTracer | 234header_cycles=1 235system=system 236use_default_range=false 237width=32 238master=system.cpu.l2cache.cpu_side 239slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 240 241[system.cpu.tracer] 242type=ExeTracer |
| 243eventq_index=0 |
|
| 219 220[system.cpu.workload] 221type=LiveProcess 222cmd=perlbmk -I. -I lib lgred.makerand.pl 223cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing 224egid=100 225env= 226errout=cerr 227euid=100 | 244 245[system.cpu.workload] 246type=LiveProcess 247cmd=perlbmk -I. -I lib lgred.makerand.pl 248cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing 249egid=100 250env= 251errout=cerr 252euid=100 |
| 228executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk | 253eventq_index=0 254executable=/dist/cpu2000/binaries/arm/linux/perlbmk |
| 229gid=100 230input=cin 231max_stack_size=67108864 232output=cout 233pid=100 234ppid=99 235simpoint=0 236system=system 237uid=100 238 239[system.cpu_clk_domain] 240type=SrcClockDomain 241clock=500 | 255gid=100 256input=cin 257max_stack_size=67108864 258output=cout 259pid=100 260ppid=99 261simpoint=0 262system=system 263uid=100 264 265[system.cpu_clk_domain] 266type=SrcClockDomain 267clock=500 |
| 268eventq_index=0 |
|
| 242voltage_domain=system.voltage_domain 243 244[system.membus] 245type=CoherentBus 246clk_domain=system.clk_domain | 269voltage_domain=system.voltage_domain 270 271[system.membus] 272type=CoherentBus 273clk_domain=system.clk_domain |
| 274eventq_index=0 |
|
| 247header_cycles=1 248system=system 249use_default_range=false 250width=8 251master=system.physmem.port 252slave=system.system_port system.cpu.l2cache.mem_side 253 254[system.physmem] 255type=SimpleMemory 256bandwidth=73.000000 257clk_domain=system.clk_domain 258conf_table_reported=true | 275header_cycles=1 276system=system 277use_default_range=false 278width=8 279master=system.physmem.port 280slave=system.system_port system.cpu.l2cache.mem_side 281 282[system.physmem] 283type=SimpleMemory 284bandwidth=73.000000 285clk_domain=system.clk_domain 286conf_table_reported=true |
| 287eventq_index=0 |
|
| 259in_addr_map=true 260latency=30000 261latency_var=0 262null=false 263range=0:134217727 264port=system.membus.master[0] 265 266[system.voltage_domain] 267type=VoltageDomain | 288in_addr_map=true 289latency=30000 290latency_var=0 291null=false 292range=0:134217727 293port=system.membus.master[0] 294 295[system.voltage_domain] 296type=VoltageDomain |
| 297eventq_index=0 |
|
| 268voltage=1.000000 269 | 298voltage=1.000000 299 |