| config.ini (9079:9a244ebdc3c9) | config.ini (9096:8971a998190a) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 152 unchanged lines hidden (view full) --- 161mem_side=system.membus.slave[1] 162 163[system.cpu.toL2Bus] 164type=CoherentBus 165block_size=64 166clock=1000 167header_cycles=1 168use_default_range=false | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 152 unchanged lines hidden (view full) --- 161mem_side=system.membus.slave[1] 162 163[system.cpu.toL2Bus] 164type=CoherentBus 165block_size=64 166clock=1000 167header_cycles=1 168use_default_range=false |
| 169width=64 | 169width=8 |
| 170master=system.cpu.l2cache.cpu_side 171slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 172 173[system.cpu.tracer] 174type=ExeTracer 175 176[system.cpu.workload] 177type=LiveProcess --- 15 unchanged lines hidden (view full) --- 193uid=100 194 195[system.membus] 196type=CoherentBus 197block_size=64 198clock=1000 199header_cycles=1 200use_default_range=false | 170master=system.cpu.l2cache.cpu_side 171slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 172 173[system.cpu.tracer] 174type=ExeTracer 175 176[system.cpu.workload] 177type=LiveProcess --- 15 unchanged lines hidden (view full) --- 193uid=100 194 195[system.membus] 196type=CoherentBus 197block_size=64 198clock=1000 199header_cycles=1 200use_default_range=false |
| 201width=64 | 201width=8 |
| 202master=system.physmem.port[0] 203slave=system.system_port system.cpu.l2cache.mem_side 204 205[system.physmem] 206type=SimpleMemory 207conf_table_reported=false 208file= 209in_addr_map=true 210latency=30000 211latency_var=0 212null=false 213range=0:134217727 214zero=false 215port=system.membus.master[0] 216 | 202master=system.physmem.port[0] 203slave=system.system_port system.cpu.l2cache.mem_side 204 205[system.physmem] 206type=SimpleMemory 207conf_table_reported=false 208file= 209in_addr_map=true 210latency=30000 211latency_var=0 212null=false 213range=0:134217727 214zero=false 215port=system.membus.master[0] 216 |