| config.ini (8835:7c68f84d7c4e) | config.ini (8893:e29c604a2582) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 12 unchanged lines hidden (view full) --- 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 12 unchanged lines hidden (view full) --- 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 |
| 29system_port=system.membus.port[0] | 29system_port=system.membus.slave[0] |
| 30 31[system.cpu] 32type=TimingSimpleCPU 33children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload 34checker=Null 35clock=500 36cpu_id=0 37defer_registration=false --- 16 unchanged lines hidden (view full) --- 54system=system 55tracer=system.cpu.tracer 56workload=system.cpu.workload 57dcache_port=system.cpu.dcache.cpu_side 58icache_port=system.cpu.icache.cpu_side 59 60[system.cpu.dcache] 61type=BaseCache | 30 31[system.cpu] 32type=TimingSimpleCPU 33children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload 34checker=Null 35clock=500 36cpu_id=0 37defer_registration=false --- 16 unchanged lines hidden (view full) --- 54system=system 55tracer=system.cpu.tracer 56workload=system.cpu.workload 57dcache_port=system.cpu.dcache.cpu_side 58icache_port=system.cpu.icache.cpu_side 59 60[system.cpu.dcache] 61type=BaseCache |
| 62addr_range=0:18446744073709551615 | 62addr_ranges=0:18446744073709551615 |
| 63assoc=2 64block_size=64 65forward_snoops=true 66hash_delay=1 67is_top_level=true 68latency=1000 69max_miss_count=0 70mshrs=10 --- 4 unchanged lines hidden (view full) --- 75size=262144 76subblock_size=0 77system=system 78tgts_per_mshr=5 79trace_addr=0 80two_queue=false 81write_buffers=8 82cpu_side=system.cpu.dcache_port | 63assoc=2 64block_size=64 65forward_snoops=true 66hash_delay=1 67is_top_level=true 68latency=1000 69max_miss_count=0 70mshrs=10 --- 4 unchanged lines hidden (view full) --- 75size=262144 76subblock_size=0 77system=system 78tgts_per_mshr=5 79trace_addr=0 80two_queue=false 81write_buffers=8 82cpu_side=system.cpu.dcache_port |
| 83mem_side=system.cpu.toL2Bus.port[1] | 83mem_side=system.cpu.toL2Bus.slave[1] |
| 84 85[system.cpu.dtb] 86type=ArmTLB 87children=walker 88size=64 89walker=system.cpu.dtb.walker 90 91[system.cpu.dtb.walker] 92type=ArmTableWalker 93max_backoff=100000 94min_backoff=0 95sys=system | 84 85[system.cpu.dtb] 86type=ArmTLB 87children=walker 88size=64 89walker=system.cpu.dtb.walker 90 91[system.cpu.dtb.walker] 92type=ArmTableWalker 93max_backoff=100000 94min_backoff=0 95sys=system |
| 96port=system.cpu.toL2Bus.port[3] | 96port=system.cpu.toL2Bus.slave[3] |
| 97 98[system.cpu.icache] 99type=BaseCache | 97 98[system.cpu.icache] 99type=BaseCache |
| 100addr_range=0:18446744073709551615 | 100addr_ranges=0:18446744073709551615 |
| 101assoc=2 102block_size=64 103forward_snoops=true 104hash_delay=1 105is_top_level=true 106latency=1000 107max_miss_count=0 108mshrs=10 --- 4 unchanged lines hidden (view full) --- 113size=131072 114subblock_size=0 115system=system 116tgts_per_mshr=5 117trace_addr=0 118two_queue=false 119write_buffers=8 120cpu_side=system.cpu.icache_port | 101assoc=2 102block_size=64 103forward_snoops=true 104hash_delay=1 105is_top_level=true 106latency=1000 107max_miss_count=0 108mshrs=10 --- 4 unchanged lines hidden (view full) --- 113size=131072 114subblock_size=0 115system=system 116tgts_per_mshr=5 117trace_addr=0 118two_queue=false 119write_buffers=8 120cpu_side=system.cpu.icache_port |
| 121mem_side=system.cpu.toL2Bus.port[0] | 121mem_side=system.cpu.toL2Bus.slave[0] |
| 122 123[system.cpu.interrupts] 124type=ArmInterrupts 125 126[system.cpu.itb] 127type=ArmTLB 128children=walker 129size=64 130walker=system.cpu.itb.walker 131 132[system.cpu.itb.walker] 133type=ArmTableWalker 134max_backoff=100000 135min_backoff=0 136sys=system | 122 123[system.cpu.interrupts] 124type=ArmInterrupts 125 126[system.cpu.itb] 127type=ArmTLB 128children=walker 129size=64 130walker=system.cpu.itb.walker 131 132[system.cpu.itb.walker] 133type=ArmTableWalker 134max_backoff=100000 135min_backoff=0 136sys=system |
| 137port=system.cpu.toL2Bus.port[2] | 137port=system.cpu.toL2Bus.slave[2] |
| 138 139[system.cpu.l2cache] 140type=BaseCache | 138 139[system.cpu.l2cache] 140type=BaseCache |
| 141addr_range=0:18446744073709551615 | 141addr_ranges=0:18446744073709551615 |
| 142assoc=2 143block_size=64 144forward_snoops=true 145hash_delay=1 146is_top_level=false 147latency=10000 148max_miss_count=0 149mshrs=10 150prefetch_on_access=false 151prefetcher=Null 152prioritizeRequests=false 153repl=Null 154size=2097152 155subblock_size=0 156system=system 157tgts_per_mshr=5 158trace_addr=0 159two_queue=false 160write_buffers=8 | 142assoc=2 143block_size=64 144forward_snoops=true 145hash_delay=1 146is_top_level=false 147latency=10000 148max_miss_count=0 149mshrs=10 150prefetch_on_access=false 151prefetcher=Null 152prioritizeRequests=false 153repl=Null 154size=2097152 155subblock_size=0 156system=system 157tgts_per_mshr=5 158trace_addr=0 159two_queue=false 160write_buffers=8 |
| 161cpu_side=system.cpu.toL2Bus.port[4] 162mem_side=system.membus.port[2] | 161cpu_side=system.cpu.toL2Bus.master[0] 162mem_side=system.membus.slave[1] |
| 163 164[system.cpu.toL2Bus] 165type=Bus 166block_size=64 167bus_id=0 168clock=1000 169header_cycles=1 170use_default_range=false 171width=64 | 163 164[system.cpu.toL2Bus] 165type=Bus 166block_size=64 167bus_id=0 168clock=1000 169header_cycles=1 170use_default_range=false 171width=64 |
| 172port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side | 172master=system.cpu.l2cache.cpu_side 173slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| 173 174[system.cpu.tracer] 175type=ExeTracer 176 177[system.cpu.workload] 178type=LiveProcess 179cmd=perlbmk -I. -I lib lgred.makerand.pl 180cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing --- 15 unchanged lines hidden (view full) --- 196[system.membus] 197type=Bus 198block_size=64 199bus_id=0 200clock=1000 201header_cycles=1 202use_default_range=false 203width=64 | 174 175[system.cpu.tracer] 176type=ExeTracer 177 178[system.cpu.workload] 179type=LiveProcess 180cmd=perlbmk -I. -I lib lgred.makerand.pl 181cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing --- 15 unchanged lines hidden (view full) --- 197[system.membus] 198type=Bus 199block_size=64 200bus_id=0 201clock=1000 202header_cycles=1 203use_default_range=false 204width=64 |
| 204port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side | 205master=system.physmem.port[0] 206slave=system.system_port system.cpu.l2cache.mem_side |
| 205 206[system.physmem] 207type=PhysicalMemory 208file= 209latency=30000 210latency_var=0 211null=false 212range=0:134217727 213zero=false | 207 208[system.physmem] 209type=PhysicalMemory 210file= 211latency=30000 212latency_var=0 213null=false 214range=0:134217727 215zero=false |
| 214port=system.membus.port[1] | 216port=system.membus.master[0] |
| 215 | 217 |