20a21
> load_offset=0
44c45
< children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
---
> children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
50a52
> dstage2_mmu=system.cpu.dstage2_mmu
56a59
> istage2_mmu=system.cpu.istage2_mmu
107a111,134
> [system.cpu.dstage2_mmu]
> type=ArmStage2MMU
> children=stage2_tlb
> eventq_index=0
> stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
> tlb=system.cpu.dtb
>
> [system.cpu.dstage2_mmu.stage2_tlb]
> type=ArmTLB
> children=walker
> eventq_index=0
> is_stage2=true
> size=32
> walker=system.cpu.dstage2_mmu.stage2_tlb.walker
>
> [system.cpu.dstage2_mmu.stage2_tlb.walker]
> type=ArmTableWalker
> clk_domain=system.cpu_clk_domain
> eventq_index=0
> is_stage2=true
> num_squash_per_cycle=2
> sys=system
> port=system.cpu.toL2Bus.slave[5]
>
111a139
> is_stage2=false
118a147
> is_stage2=false
165a195,204
> id_aa64afr0_el1=0
> id_aa64afr1_el1=0
> id_aa64dfr0_el1=1052678
> id_aa64dfr1_el1=0
> id_aa64isar0_el1=0
> id_aa64isar1_el1=0
> id_aa64mmfr0_el1=15728642
> id_aa64mmfr1_el1=0
> id_aa64pfr0_el1=17
> id_aa64pfr1_el1=0
172c211
< id_mmfr0=3
---
> id_mmfr0=270536963
175c214
< id_mmfr3=4027589137
---
> id_mmfr3=34611729
177,178c216,218
< id_pfr1=1
< midr=890224640
---
> id_pfr1=4113
> midr=1091551472
> system=system
179a220,243
> [system.cpu.istage2_mmu]
> type=ArmStage2MMU
> children=stage2_tlb
> eventq_index=0
> stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
> tlb=system.cpu.itb
>
> [system.cpu.istage2_mmu.stage2_tlb]
> type=ArmTLB
> children=walker
> eventq_index=0
> is_stage2=true
> size=32
> walker=system.cpu.istage2_mmu.stage2_tlb.walker
>
> [system.cpu.istage2_mmu.stage2_tlb.walker]
> type=ArmTableWalker
> clk_domain=system.cpu_clk_domain
> eventq_index=0
> is_stage2=true
> num_squash_per_cycle=2
> sys=system
> port=system.cpu.toL2Bus.slave[4]
>
183a248
> is_stage2=false
190a256
> is_stage2=false
239c305
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
---
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port