| stats.txt (10036:80e84beef3bb) | stats.txt (10038:7eccd14e2610) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.945613 # Number of seconds simulated 4sim_ticks 945613126000 # Number of ticks simulated 5final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.945613 # Number of seconds simulated 4sim_ticks 945613126000 # Number of ticks simulated 5final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1817390 # Simulator instruction rate (inst/s) 8host_op_rate 2475033 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1241382789 # Simulator tick rate (ticks/s) 10host_mem_usage 247108 # Number of bytes of host memory used 11host_seconds 761.74 # Real time elapsed on the host | 7host_inst_rate 1603190 # Simulator instruction rate (inst/s) 8host_op_rate 2183323 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1095071931 # Simulator tick rate (ticks/s) 10host_mem_usage 266996 # Number of bytes of host memory used 11host_seconds 863.52 # Real time elapsed on the host |
| 12sim_insts 1384381606 # Number of instructions simulated 13sim_ops 1885336358 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory --- 14 unchanged lines hidden (view full) --- 34system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s) 38system.membus.throughput 9675679644 # Throughput (bytes/s) 39system.membus.data_through_bus 9149449674 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.cpu_clk_domain.clock 500 # Clock period in ticks | 12sim_insts 1384381606 # Number of instructions simulated 13sim_ops 1885336358 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory --- 14 unchanged lines hidden (view full) --- 34system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s) 38system.membus.throughput 9675679644 # Throughput (bytes/s) 39system.membus.data_through_bus 9149449674 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 42system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 43system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 44system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 46system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 53system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 54system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 55system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 58system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 59system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 60system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 61system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 62system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
|
| 42system.cpu.dtb.inst_hits 0 # ITB inst hits 43system.cpu.dtb.inst_misses 0 # ITB inst misses 44system.cpu.dtb.read_hits 0 # DTB read hits 45system.cpu.dtb.read_misses 0 # DTB read misses 46system.cpu.dtb.write_hits 0 # DTB write hits 47system.cpu.dtb.write_misses 0 # DTB write misses 48system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 55system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.dtb.read_accesses 0 # DTB read accesses 58system.cpu.dtb.write_accesses 0 # DTB write accesses 59system.cpu.dtb.inst_accesses 0 # ITB inst accesses 60system.cpu.dtb.hits 0 # DTB hits 61system.cpu.dtb.misses 0 # DTB misses 62system.cpu.dtb.accesses 0 # DTB accesses | 63system.cpu.dtb.inst_hits 0 # ITB inst hits 64system.cpu.dtb.inst_misses 0 # ITB inst misses 65system.cpu.dtb.read_hits 0 # DTB read hits 66system.cpu.dtb.read_misses 0 # DTB read misses 67system.cpu.dtb.write_hits 0 # DTB write hits 68system.cpu.dtb.write_misses 0 # DTB write misses 69system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 70system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 76system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 77system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 78system.cpu.dtb.read_accesses 0 # DTB read accesses 79system.cpu.dtb.write_accesses 0 # DTB write accesses 80system.cpu.dtb.inst_accesses 0 # ITB inst accesses 81system.cpu.dtb.hits 0 # DTB hits 82system.cpu.dtb.misses 0 # DTB misses 83system.cpu.dtb.accesses 0 # DTB accesses |
| 84system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 85system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 86system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 87system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 88system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 89system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 90system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 91system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 92system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 93system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 94system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 95system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 96system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 97system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 98system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 99system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 100system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 101system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 102system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 103system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 104system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
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| 63system.cpu.itb.inst_hits 0 # ITB inst hits 64system.cpu.itb.inst_misses 0 # ITB inst misses 65system.cpu.itb.read_hits 0 # DTB read hits 66system.cpu.itb.read_misses 0 # DTB read misses 67system.cpu.itb.write_hits 0 # DTB write hits 68system.cpu.itb.write_misses 0 # DTB write misses 69system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 70system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 17 unchanged lines hidden (view full) --- 88system.cpu.committedInsts 1384381606 # Number of instructions committed 89system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed 90system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses 91system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses 92system.cpu.num_func_calls 80372855 # number of times a function call or return occured 93system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls 94system.cpu.num_int_insts 1653698868 # number of integer instructions 95system.cpu.num_fp_insts 52289415 # number of float instructions | 105system.cpu.itb.inst_hits 0 # ITB inst hits 106system.cpu.itb.inst_misses 0 # ITB inst misses 107system.cpu.itb.read_hits 0 # DTB read hits 108system.cpu.itb.read_misses 0 # DTB read misses 109system.cpu.itb.write_hits 0 # DTB write hits 110system.cpu.itb.write_misses 0 # DTB write misses 111system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 17 unchanged lines hidden (view full) --- 130system.cpu.committedInsts 1384381606 # Number of instructions committed 131system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed 132system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses 133system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses 134system.cpu.num_func_calls 80372855 # number of times a function call or return occured 135system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls 136system.cpu.num_int_insts 1653698868 # number of integer instructions 137system.cpu.num_fp_insts 52289415 # number of float instructions |
| 96system.cpu.num_int_register_reads 8601515912 # number of times the integer registers were read | 138system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read |
| 97system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written 98system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read 99system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written 100system.cpu.num_mem_refs 908382479 # number of memory refs 101system.cpu.num_load_insts 631387181 # Number of load instructions 102system.cpu.num_store_insts 276995298 # Number of store instructions 103system.cpu.num_idle_cycles 0 # Number of idle cycles 104system.cpu.num_busy_cycles 1891226253 # Number of busy cycles 105system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 106system.cpu.idle_fraction 0 # Percentage of idle cycles 107 108---------- End Simulation Statistics ---------- | 139system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written 140system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read 141system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written 142system.cpu.num_mem_refs 908382479 # number of memory refs 143system.cpu.num_load_insts 631387181 # Number of load instructions 144system.cpu.num_store_insts 276995298 # Number of store instructions 145system.cpu.num_idle_cycles 0 # Number of idle cycles 146system.cpu.num_busy_cycles 1891226253 # Number of busy cycles 147system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 148system.cpu.idle_fraction 0 # Percentage of idle cycles 149 150---------- End Simulation Statistics ---------- |