Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt

stats.txt (11570:4aac82f10951)	stats.txt (11606:6b749761c398)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.395727 # Number of seconds simulated 4sim_ticks 395726778500 # Number of ticks simulated 5final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.395727 # Number of seconds simulated 4sim_ticks 395726778500 # Number of ticks simulated 5final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 860032 # Simulator instruction rate (inst/s) 8host_op_rate 1058813 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 531234389 # Simulator tick rate (ticks/s) 10host_mem_usage 264584 # Number of bytes of host memory used 11host_seconds 744.92 # Real time elapsed on the host	7host_inst_rate 969638 # Simulator instruction rate (inst/s) 8host_op_rate 1193752 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 598936996 # Simulator tick rate (ticks/s) 10host_mem_usage 268708 # Number of bytes of host memory used 11host_seconds 660.72 # Real time elapsed on the host
12sim_insts 640654411 # Number of instructions simulated 13sim_ops 788730070 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory 19system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory 23system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory 27system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) 39system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 40system.cpu_clk_domain.clock 500 # Clock period in ticks 41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 42system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 53system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 54system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 63system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 72system.cpu.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.inst_hits 0 # ITB inst hits 81system.cpu.dtb.inst_misses 0 # ITB inst misses 82system.cpu.dtb.read_hits 0 # DTB read hits 83system.cpu.dtb.read_misses 0 # DTB read misses 84system.cpu.dtb.write_hits 0 # DTB write hits 85system.cpu.dtb.write_misses 0 # DTB write misses 86system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 87system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 88system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 89system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 90system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 91system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 92system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 93system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.dtb.read_accesses 0 # DTB read accesses 96system.cpu.dtb.write_accesses 0 # DTB write accesses 97system.cpu.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.dtb.hits 0 # DTB hits 99system.cpu.dtb.misses 0 # DTB misses 100system.cpu.dtb.accesses 0 # DTB accesses 101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 102system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 111system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 112system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 113system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 115system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 116system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 121system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 122system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 123system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 132system.cpu.itb.walker.walks 0 # Table walker walks requested 133system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.inst_hits 0 # ITB inst hits 141system.cpu.itb.inst_misses 0 # ITB inst misses 142system.cpu.itb.read_hits 0 # DTB read hits 143system.cpu.itb.read_misses 0 # DTB read misses 144system.cpu.itb.write_hits 0 # DTB write hits 145system.cpu.itb.write_misses 0 # DTB write misses 146system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 147system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 149system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 150system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 151system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.itb.read_accesses 0 # DTB read accesses 156system.cpu.itb.write_accesses 0 # DTB write accesses 157system.cpu.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.itb.hits 0 # DTB hits 159system.cpu.itb.misses 0 # DTB misses 160system.cpu.itb.accesses 0 # DTB accesses 161system.cpu.workload.num_syscalls 673 # Number of system calls 162system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states 163system.cpu.numCycles 791453558 # number of cpu cycles simulated 164system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 166system.cpu.committedInsts 640654411 # Number of instructions committed 167system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed 168system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses 169system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses 170system.cpu.num_func_calls 37261296 # number of times a function call or return occured 171system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls 172system.cpu.num_int_insts 682251400 # number of integer instructions 173system.cpu.num_fp_insts 24239771 # number of float instructions 174system.cpu.num_int_register_reads 1268495038 # number of times the integer registers were read 175system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written 176system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read 177system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written 178system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read 179system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written 180system.cpu.num_mem_refs 381221435 # number of memory refs 181system.cpu.num_load_insts 252240938 # Number of load instructions 182system.cpu.num_store_insts 128980497 # Number of store instructions 183system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 184system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles 185system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 186system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 187system.cpu.Branches 137364860 # Number of branches fetched 188system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 189system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction 190system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction 191system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction 192system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction 193system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction 194system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction 195system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction 196system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction 197system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction 198system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction 199system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction 200system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction 201system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction 202system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction 203system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction 204system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction 205system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction 206system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction 207system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction 208system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction 209system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction 210system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction 211system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction 212system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction 213system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction 214system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction 215system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction 216system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction 217system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction 218system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction 219system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction 220system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 221system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 222system.cpu.op_class::total 788730744 # Class of executed instruction	12sim_insts 640654411 # Number of instructions simulated 13sim_ops 788730070 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory 19system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory 23system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory 27system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) 39system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 40system.cpu_clk_domain.clock 500 # Clock period in ticks 41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 42system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 53system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 54system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 63system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 72system.cpu.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.inst_hits 0 # ITB inst hits 81system.cpu.dtb.inst_misses 0 # ITB inst misses 82system.cpu.dtb.read_hits 0 # DTB read hits 83system.cpu.dtb.read_misses 0 # DTB read misses 84system.cpu.dtb.write_hits 0 # DTB write hits 85system.cpu.dtb.write_misses 0 # DTB write misses 86system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 87system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 88system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 89system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 90system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 91system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 92system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 93system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.dtb.read_accesses 0 # DTB read accesses 96system.cpu.dtb.write_accesses 0 # DTB write accesses 97system.cpu.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.dtb.hits 0 # DTB hits 99system.cpu.dtb.misses 0 # DTB misses 100system.cpu.dtb.accesses 0 # DTB accesses 101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 102system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 111system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 112system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 113system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 115system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 116system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 121system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 122system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 123system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 132system.cpu.itb.walker.walks 0 # Table walker walks requested 133system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.inst_hits 0 # ITB inst hits 141system.cpu.itb.inst_misses 0 # ITB inst misses 142system.cpu.itb.read_hits 0 # DTB read hits 143system.cpu.itb.read_misses 0 # DTB read misses 144system.cpu.itb.write_hits 0 # DTB write hits 145system.cpu.itb.write_misses 0 # DTB write misses 146system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 147system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 149system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 150system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 151system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.itb.read_accesses 0 # DTB read accesses 156system.cpu.itb.write_accesses 0 # DTB write accesses 157system.cpu.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.itb.hits 0 # DTB hits 159system.cpu.itb.misses 0 # DTB misses 160system.cpu.itb.accesses 0 # DTB accesses 161system.cpu.workload.num_syscalls 673 # Number of system calls 162system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states 163system.cpu.numCycles 791453558 # number of cpu cycles simulated 164system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 166system.cpu.committedInsts 640654411 # Number of instructions committed 167system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed 168system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses 169system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses 170system.cpu.num_func_calls 37261296 # number of times a function call or return occured 171system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls 172system.cpu.num_int_insts 682251400 # number of integer instructions 173system.cpu.num_fp_insts 24239771 # number of float instructions 174system.cpu.num_int_register_reads 1268495038 # number of times the integer registers were read 175system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written 176system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read 177system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written 178system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read 179system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written 180system.cpu.num_mem_refs 381221435 # number of memory refs 181system.cpu.num_load_insts 252240938 # Number of load instructions 182system.cpu.num_store_insts 128980497 # Number of store instructions 183system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 184system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles 185system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 186system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 187system.cpu.Branches 137364860 # Number of branches fetched 188system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 189system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction 190system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction 191system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction 192system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction 193system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction 194system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction 195system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction 196system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction 197system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction 198system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction 199system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction 200system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction 201system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction 202system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction 203system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction 204system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction 205system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction 206system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction 207system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction 208system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction 209system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction 210system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction 211system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction 212system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction 213system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction 214system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction 215system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction 216system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction 217system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction 218system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction 219system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction 220system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 221system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 222system.cpu.op_class::total 788730744 # Class of executed instruction
	223system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 224system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 225system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 226system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 227system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 228system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
223system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 224system.membus.trans_dist::ReadReq 893703778 # Transaction distribution 225system.membus.trans_dist::ReadResp 893709517 # Transaction distribution 226system.membus.trans_dist::WriteReq 128951477 # Transaction distribution 227system.membus.trans_dist::WriteResp 128951477 # Transaction distribution 228system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution 229system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution 230system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution 231system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution 232system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution 233system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes) 236system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes) 237system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) 238system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) 239system.membus.snoops 0 # Total snoops (count) 240system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 241system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram	229system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states 230system.membus.trans_dist::ReadReq 893703778 # Transaction distribution 231system.membus.trans_dist::ReadResp 893709517 # Transaction distribution 232system.membus.trans_dist::WriteReq 128951477 # Transaction distribution 233system.membus.trans_dist::WriteResp 128951477 # Transaction distribution 234system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution 235system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution 236system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution 237system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution 238system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution 239system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes) 240system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) 241system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes) 242system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes) 243system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) 244system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) 245system.membus.snoops 0 # Total snoops (count) 246system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 247system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
242system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram 243system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram	248system.membus.snoop_fanout::mean 0 # Request fanout histogram 249system.membus.snoop_fanout::stdev 0 # Request fanout histogram
244system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram	250system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
245system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram 246system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram	251system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram 252system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
247system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 248system.membus.snoop_fanout::min_value 0 # Request fanout histogram	253system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 254system.membus.snoop_fanout::min_value 0 # Request fanout histogram
249system.membus.snoop_fanout::max_value 1 # Request fanout histogram	255system.membus.snoop_fanout::max_value 0 # Request fanout histogram
250system.membus.snoop_fanout::total 1022670353 # Request fanout histogram 251 252---------- End Simulation Statistics ----------	256system.membus.snoop_fanout::total 1022670353 # Request fanout histogram 257 258---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.395727 # Number of seconds simulated
4sim_ticks 395726778500 # Number of ticks simulated
5final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 860032 # Simulator instruction rate (inst/s)
8host_op_rate 1058813 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 531234389 # Simulator tick rate (ticks/s)
10host_mem_usage 264584 # Number of bytes of host memory used
11host_seconds 744.92 # Real time elapsed on the host

7host_inst_rate 969638 # Simulator instruction rate (inst/s)
8host_op_rate 1193752 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 598936996 # Simulator tick rate (ticks/s)
10host_mem_usage 268708 # Number of bytes of host memory used
11host_seconds 660.72 # Real time elapsed on the host

12sim_insts 640654411 # Number of instructions simulated
13sim_ops 788730070 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
19system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory
23system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory
27system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s)
39system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
40system.cpu_clk_domain.clock 500 # Clock period in ticks
41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
42system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
50system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
51system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
52system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
53system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
54system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
55system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
60system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
61system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
62system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
63system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
64system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
65system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
66system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
68system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
69system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
70system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
72system.cpu.dtb.walker.walks 0 # Table walker walks requested
73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
75system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
78system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
79system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
80system.cpu.dtb.inst_hits 0 # ITB inst hits
81system.cpu.dtb.inst_misses 0 # ITB inst misses
82system.cpu.dtb.read_hits 0 # DTB read hits
83system.cpu.dtb.read_misses 0 # DTB read misses
84system.cpu.dtb.write_hits 0 # DTB write hits
85system.cpu.dtb.write_misses 0 # DTB write misses
86system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
87system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
88system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
89system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
90system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
91system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
92system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
93system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
94system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
95system.cpu.dtb.read_accesses 0 # DTB read accesses
96system.cpu.dtb.write_accesses 0 # DTB write accesses
97system.cpu.dtb.inst_accesses 0 # ITB inst accesses
98system.cpu.dtb.hits 0 # DTB hits
99system.cpu.dtb.misses 0 # DTB misses
100system.cpu.dtb.accesses 0 # DTB accesses
101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
102system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
110system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
111system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
112system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
113system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
114system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
115system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
116system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
120system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
121system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
122system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
123system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
124system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
125system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
126system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
127system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
128system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
129system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
130system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
132system.cpu.itb.walker.walks 0 # Table walker walks requested
133system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
135system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
136system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
138system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
139system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
140system.cpu.itb.inst_hits 0 # ITB inst hits
141system.cpu.itb.inst_misses 0 # ITB inst misses
142system.cpu.itb.read_hits 0 # DTB read hits
143system.cpu.itb.read_misses 0 # DTB read misses
144system.cpu.itb.write_hits 0 # DTB write hits
145system.cpu.itb.write_misses 0 # DTB write misses
146system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
147system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
148system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
149system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
150system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
151system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
152system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
153system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
154system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
155system.cpu.itb.read_accesses 0 # DTB read accesses
156system.cpu.itb.write_accesses 0 # DTB write accesses
157system.cpu.itb.inst_accesses 0 # ITB inst accesses
158system.cpu.itb.hits 0 # DTB hits
159system.cpu.itb.misses 0 # DTB misses
160system.cpu.itb.accesses 0 # DTB accesses
161system.cpu.workload.num_syscalls 673 # Number of system calls
162system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states
163system.cpu.numCycles 791453558 # number of cpu cycles simulated
164system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
165system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
166system.cpu.committedInsts 640654411 # Number of instructions committed
167system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed
168system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
169system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
170system.cpu.num_func_calls 37261296 # number of times a function call or return occured
171system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
172system.cpu.num_int_insts 682251400 # number of integer instructions
173system.cpu.num_fp_insts 24239771 # number of float instructions
174system.cpu.num_int_register_reads 1268495038 # number of times the integer registers were read
175system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
176system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
177system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
178system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read
179system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
180system.cpu.num_mem_refs 381221435 # number of memory refs
181system.cpu.num_load_insts 252240938 # Number of load instructions
182system.cpu.num_store_insts 128980497 # Number of store instructions
183system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
184system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles
185system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
186system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
187system.cpu.Branches 137364860 # Number of branches fetched
188system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
189system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
190system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
191system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
192system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
193system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
194system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
195system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
196system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
197system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
198system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
199system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
200system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
201system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
202system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
203system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
204system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
205system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
206system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
207system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
208system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
209system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
210system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
211system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
212system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
213system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
214system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
215system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
216system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
217system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
218system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
219system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
220system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
221system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
222system.cpu.op_class::total 788730744 # Class of executed instruction

223system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
224system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
225system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
226system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
227system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
228system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

223system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
224system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
225system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
226system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
227system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
228system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
229system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution
230system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
231system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
232system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
233system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes)
234system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
235system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes)
236system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes)
237system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
238system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
239system.membus.snoops 0 # Total snoops (count)
240system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
241system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram

229system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
230system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
231system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
232system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
233system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
234system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
235system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution
236system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
237system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
238system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
239system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes)
240system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
241system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes)
242system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes)
243system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
244system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
245system.membus.snoops 0 # Total snoops (count)
246system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
247system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram

242system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram
243system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram

248system.membus.snoop_fanout::mean 0 # Request fanout histogram
249system.membus.snoop_fanout::stdev 0 # Request fanout histogram

244system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

250system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

245system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram
246system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram

251system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram
252system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram

247system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
248system.membus.snoop_fanout::min_value 0 # Request fanout histogram

253system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
254system.membus.snoop_fanout::min_value 0 # Request fanout histogram

249system.membus.snoop_fanout::max_value 1 # Request fanout histogram

255system.membus.snoop_fanout::max_value 0 # Request fanout histogram