1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.945613 # Number of seconds simulated
4sim_ticks 945613126000 # Number of ticks simulated
5final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.945613 # Number of seconds simulated
4sim_ticks 945613126000 # Number of ticks simulated
5final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1077492 # Simulator instruction rate (inst/s)
8host_op_rate 1467395 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 735989505 # Simulator tick rate (ticks/s)
10host_mem_usage 323780 # Number of bytes of host memory used
11host_seconds 1284.82 # Real time elapsed on the host
| 7host_inst_rate 1407956 # Simulator instruction rate (inst/s)
8host_op_rate 1917442 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 961716087 # Simulator tick rate (ticks/s)
10host_mem_usage 309672 # Number of bytes of host memory used
11host_seconds 983.26 # Real time elapsed on the host
|
12sim_insts 1384381606 # Number of instructions simulated
13sim_ops 1885336358 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory
18system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 5561086004 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory
22system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 1390271501 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 620345398 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 2010616899 # Number of read requests responded to by this memory
26system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 5880931484 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 2606145374 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 8487076858 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 5880931484 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 5880931484 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::cpu.data 1188602786 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s)
38system.membus.throughput 9675679644 # Throughput (bytes/s)
39system.membus.data_through_bus 9149449674 # Total data (bytes)
40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
41system.cpu_clk_domain.clock 500 # Clock period in ticks
42system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
43system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
44system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
45system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
46system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
47system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
52system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
53system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
54system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
55system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
56system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
57system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
58system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
59system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
60system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
61system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
62system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
63system.cpu.dtb.inst_hits 0 # ITB inst hits
64system.cpu.dtb.inst_misses 0 # ITB inst misses
65system.cpu.dtb.read_hits 0 # DTB read hits
66system.cpu.dtb.read_misses 0 # DTB read misses
67system.cpu.dtb.write_hits 0 # DTB write hits
68system.cpu.dtb.write_misses 0 # DTB write misses
69system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
70system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
71system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
72system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
73system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
74system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
75system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
76system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
77system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
78system.cpu.dtb.read_accesses 0 # DTB read accesses
79system.cpu.dtb.write_accesses 0 # DTB write accesses
80system.cpu.dtb.inst_accesses 0 # ITB inst accesses
81system.cpu.dtb.hits 0 # DTB hits
82system.cpu.dtb.misses 0 # DTB misses
83system.cpu.dtb.accesses 0 # DTB accesses
84system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
85system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
86system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
87system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
88system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
89system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
90system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
91system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
92system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
93system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
94system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
95system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
96system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
97system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
98system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
99system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
100system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
101system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
102system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
103system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
104system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
105system.cpu.itb.inst_hits 0 # ITB inst hits
106system.cpu.itb.inst_misses 0 # ITB inst misses
107system.cpu.itb.read_hits 0 # DTB read hits
108system.cpu.itb.read_misses 0 # DTB read misses
109system.cpu.itb.write_hits 0 # DTB write hits
110system.cpu.itb.write_misses 0 # DTB write misses
111system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
112system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
113system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
114system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
115system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
116system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
117system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
118system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
119system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
120system.cpu.itb.read_accesses 0 # DTB read accesses
121system.cpu.itb.write_accesses 0 # DTB write accesses
122system.cpu.itb.inst_accesses 0 # ITB inst accesses
123system.cpu.itb.hits 0 # DTB hits
124system.cpu.itb.misses 0 # DTB misses
125system.cpu.itb.accesses 0 # DTB accesses
126system.cpu.workload.num_syscalls 1411 # Number of system calls
127system.cpu.numCycles 1891226253 # number of cpu cycles simulated
128system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
129system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
130system.cpu.committedInsts 1384381606 # Number of instructions committed
131system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed
132system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses
133system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
134system.cpu.num_func_calls 80372855 # number of times a function call or return occured
135system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls
136system.cpu.num_int_insts 1653698868 # number of integer instructions
137system.cpu.num_fp_insts 52289415 # number of float instructions
138system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read
139system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written
140system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
141system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
142system.cpu.num_mem_refs 908382479 # number of memory refs
143system.cpu.num_load_insts 631387181 # Number of load instructions
144system.cpu.num_store_insts 276995298 # Number of store instructions
145system.cpu.num_idle_cycles 0 # Number of idle cycles
146system.cpu.num_busy_cycles 1891226253 # Number of busy cycles
147system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
148system.cpu.idle_fraction 0 # Percentage of idle cycles
149system.cpu.Branches 298259106 # Number of branches fetched
| 12sim_insts 1384381606 # Number of instructions simulated
13sim_ops 1885336358 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory
18system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 5561086004 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory
22system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 1390271501 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 620345398 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 2010616899 # Number of read requests responded to by this memory
26system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 5880931484 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 2606145374 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 8487076858 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 5880931484 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 5880931484 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::cpu.data 1188602786 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s)
38system.membus.throughput 9675679644 # Throughput (bytes/s)
39system.membus.data_through_bus 9149449674 # Total data (bytes)
40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
41system.cpu_clk_domain.clock 500 # Clock period in ticks
42system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
43system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
44system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
45system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
46system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
47system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
52system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
53system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
54system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
55system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
56system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
57system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
58system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
59system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
60system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
61system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
62system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
63system.cpu.dtb.inst_hits 0 # ITB inst hits
64system.cpu.dtb.inst_misses 0 # ITB inst misses
65system.cpu.dtb.read_hits 0 # DTB read hits
66system.cpu.dtb.read_misses 0 # DTB read misses
67system.cpu.dtb.write_hits 0 # DTB write hits
68system.cpu.dtb.write_misses 0 # DTB write misses
69system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
70system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
71system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
72system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
73system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
74system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
75system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
76system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
77system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
78system.cpu.dtb.read_accesses 0 # DTB read accesses
79system.cpu.dtb.write_accesses 0 # DTB write accesses
80system.cpu.dtb.inst_accesses 0 # ITB inst accesses
81system.cpu.dtb.hits 0 # DTB hits
82system.cpu.dtb.misses 0 # DTB misses
83system.cpu.dtb.accesses 0 # DTB accesses
84system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
85system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
86system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
87system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
88system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
89system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
90system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
91system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
92system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
93system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
94system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
95system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
96system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
97system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
98system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
99system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
100system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
101system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
102system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
103system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
104system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
105system.cpu.itb.inst_hits 0 # ITB inst hits
106system.cpu.itb.inst_misses 0 # ITB inst misses
107system.cpu.itb.read_hits 0 # DTB read hits
108system.cpu.itb.read_misses 0 # DTB read misses
109system.cpu.itb.write_hits 0 # DTB write hits
110system.cpu.itb.write_misses 0 # DTB write misses
111system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
112system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
113system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
114system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
115system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
116system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
117system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
118system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
119system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
120system.cpu.itb.read_accesses 0 # DTB read accesses
121system.cpu.itb.write_accesses 0 # DTB write accesses
122system.cpu.itb.inst_accesses 0 # ITB inst accesses
123system.cpu.itb.hits 0 # DTB hits
124system.cpu.itb.misses 0 # DTB misses
125system.cpu.itb.accesses 0 # DTB accesses
126system.cpu.workload.num_syscalls 1411 # Number of system calls
127system.cpu.numCycles 1891226253 # number of cpu cycles simulated
128system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
129system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
130system.cpu.committedInsts 1384381606 # Number of instructions committed
131system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed
132system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses
133system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
134system.cpu.num_func_calls 80372855 # number of times a function call or return occured
135system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls
136system.cpu.num_int_insts 1653698868 # number of integer instructions
137system.cpu.num_fp_insts 52289415 # number of float instructions
138system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read
139system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written
140system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
141system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
142system.cpu.num_mem_refs 908382479 # number of memory refs
143system.cpu.num_load_insts 631387181 # Number of load instructions
144system.cpu.num_store_insts 276995298 # Number of store instructions
145system.cpu.num_idle_cycles 0 # Number of idle cycles
146system.cpu.num_busy_cycles 1891226253 # Number of busy cycles
147system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
148system.cpu.idle_fraction 0 # Percentage of idle cycles
149system.cpu.Branches 298259106 # Number of branches fetched
|
| 150system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
151system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction
152system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction
153system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction
154system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction
155system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction
156system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction
157system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction
158system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction
159system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction
160system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction
161system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction
162system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction
163system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction
164system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction
165system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction
166system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction
167system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction
168system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction
169system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction
170system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction
171system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction
172system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction
173system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction
174system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction
175system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction
176system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction
177system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction
178system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction
179system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction
180system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction
181system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction
182system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
183system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
184system.cpu.op_class::total 1885337770 # Class of executed instruction
|
150
151---------- End Simulation Statistics ----------
| 185
186---------- End Simulation Statistics ----------
|