20a21
> load_offset=0
44c45
< children=dtb interrupts isa itb tracer workload
---
> children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
50a52
> dstage2_mmu=system.cpu.dstage2_mmu
57a60
> istage2_mmu=system.cpu.istage2_mmu
79a83,106
> [system.cpu.dstage2_mmu]
> type=ArmStage2MMU
> children=stage2_tlb
> eventq_index=0
> stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
> tlb=system.cpu.dtb
>
> [system.cpu.dstage2_mmu.stage2_tlb]
> type=ArmTLB
> children=walker
> eventq_index=0
> is_stage2=true
> size=32
> walker=system.cpu.dstage2_mmu.stage2_tlb.walker
>
> [system.cpu.dstage2_mmu.stage2_tlb.walker]
> type=ArmTableWalker
> clk_domain=system.cpu_clk_domain
> eventq_index=0
> is_stage2=true
> num_squash_per_cycle=2
> sys=system
> port=system.membus.slave[6]
>
83a111
> is_stage2=false
90a119
> is_stage2=false
102a132,141
> id_aa64afr0_el1=0
> id_aa64afr1_el1=0
> id_aa64dfr0_el1=1052678
> id_aa64dfr1_el1=0
> id_aa64isar0_el1=0
> id_aa64isar1_el1=0
> id_aa64mmfr0_el1=15728642
> id_aa64mmfr1_el1=0
> id_aa64pfr0_el1=17
> id_aa64pfr1_el1=0
109c148
< id_mmfr0=3
---
> id_mmfr0=270536963
112c151
< id_mmfr3=4027589137
---
> id_mmfr3=34611729
114,115c153,155
< id_pfr1=1
< midr=890224640
---
> id_pfr1=4113
> midr=1091551472
> system=system
116a157,180
> [system.cpu.istage2_mmu]
> type=ArmStage2MMU
> children=stage2_tlb
> eventq_index=0
> stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
> tlb=system.cpu.itb
>
> [system.cpu.istage2_mmu.stage2_tlb]
> type=ArmTLB
> children=walker
> eventq_index=0
> is_stage2=true
> size=32
> walker=system.cpu.istage2_mmu.stage2_tlb.walker
>
> [system.cpu.istage2_mmu.stage2_tlb.walker]
> type=ArmTableWalker
> clk_domain=system.cpu_clk_domain
> eventq_index=0
> is_stage2=true
> num_squash_per_cycle=2
> sys=system
> port=system.membus.slave[5]
>
120a185
> is_stage2=false
127a193
> is_stage2=false
171c237
< slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
---
> slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port