Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.633885 # Number of seconds simulated
4sim_ticks 633884897500 # Number of ticks simulated
5final_tick 633884897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.629535 # Number of seconds simulated
4sim_ticks 629535413500 # Number of ticks simulated
5final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 87779 # Simulator instruction rate (inst/s)
8host_op_rate 119542 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 40192628 # Simulator tick rate (ticks/s)
10host_mem_usage 283676 # Number of bytes of host memory used
11host_seconds 15771.17 # Real time elapsed on the host

7host_inst_rate 71307 # Simulator instruction rate (inst/s)
8host_op_rate 97111 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 32426577 # Simulator tick rate (ticks/s)
10host_mem_usage 303200 # Number of bytes of host memory used
11host_seconds 19414.18 # Real time elapsed on the host

12sim_insts 1384370590 # Number of instructions simulated
13sim_ops 1885325342 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory

15system.physmem.bytes_read::cpu.data 30242944 # Number of bytes read from this memory
16system.physmem.bytes_read::total 30398080 # Number of bytes read from this memory

15system.physmem.bytes_read::cpu.data 30242496 # Number of bytes read from this memory
16system.physmem.bytes_read::total 30397632 # Number of bytes read from this memory

17system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
20system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory

22system.physmem.num_reads::cpu.data 472546 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 474970 # Number of read requests responded to by this memory

22system.physmem.num_reads::cpu.data 472539 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 474963 # Number of read requests responded to by this memory

24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory

26system.physmem.bw_read::cpu.inst 244738 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 47710466 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 47955205 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 244738 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 244738 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 6673565 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 6673565 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 6673565 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 244738 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 47710466 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 54628770 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 474970 # Number of read requests accepted

26system.physmem.bw_read::cpu.inst 246429 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 48039388 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 48285817 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 246429 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 246429 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 6719673 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 6719673 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 6719673 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 246429 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 48039388 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 55005490 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 474963 # Number of read requests accepted

38system.physmem.writeReqs 66098 # Number of write requests accepted

39system.physmem.readBursts 474970 # Number of DRAM read bursts, including those serviced by the write queue

39system.physmem.readBursts 474963 # Number of DRAM read bursts, including those serviced by the write queue

40system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue

41system.physmem.bytesReadDRAM 30392000 # Total number of bytes read from DRAM
42system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue
43system.physmem.bytesWritten 4230080 # Total number of bytes written to DRAM
44system.physmem.bytesReadSys 30398080 # Total read bytes from the system interface side

41system.physmem.bytesReadDRAM 30390400 # Total number of bytes read from DRAM
42system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue
43system.physmem.bytesWritten 4229888 # Total number of bytes written to DRAM
44system.physmem.bytesReadSys 30397632 # Total read bytes from the system interface side

45system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side

46system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue

46system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue

47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one

48system.physmem.neitherReadNorWriteReqs 4324 # Number of requests that are neither read nor write
49system.physmem.perBankRdBursts::0 29875 # Per bank write bursts
50system.physmem.perBankRdBursts::1 29673 # Per bank write bursts
51system.physmem.perBankRdBursts::2 29745 # Per bank write bursts
52system.physmem.perBankRdBursts::3 29707 # Per bank write bursts
53system.physmem.perBankRdBursts::4 29817 # Per bank write bursts
54system.physmem.perBankRdBursts::5 29835 # Per bank write bursts
55system.physmem.perBankRdBursts::6 29655 # Per bank write bursts
56system.physmem.perBankRdBursts::7 29450 # Per bank write bursts
57system.physmem.perBankRdBursts::8 29485 # Per bank write bursts
58system.physmem.perBankRdBursts::9 29492 # Per bank write bursts

48system.physmem.neitherReadNorWriteReqs 4262 # Number of requests that are neither read nor write
49system.physmem.perBankRdBursts::0 29871 # Per bank write bursts
50system.physmem.perBankRdBursts::1 29675 # Per bank write bursts
51system.physmem.perBankRdBursts::2 29749 # Per bank write bursts
52system.physmem.perBankRdBursts::3 29712 # Per bank write bursts
53system.physmem.perBankRdBursts::4 29816 # Per bank write bursts
54system.physmem.perBankRdBursts::5 29834 # Per bank write bursts
55system.physmem.perBankRdBursts::6 29642 # Per bank write bursts
56system.physmem.perBankRdBursts::7 29444 # Per bank write bursts
57system.physmem.perBankRdBursts::8 29480 # Per bank write bursts
58system.physmem.perBankRdBursts::9 29489 # Per bank write bursts

59system.physmem.perBankRdBursts::10 29547 # Per bank write bursts

60system.physmem.perBankRdBursts::11 29655 # Per bank write bursts
61system.physmem.perBankRdBursts::12 29700 # Per bank write bursts
62system.physmem.perBankRdBursts::13 29805 # Per bank write bursts

60system.physmem.perBankRdBursts::11 29649 # Per bank write bursts
61system.physmem.perBankRdBursts::12 29701 # Per bank write bursts
62system.physmem.perBankRdBursts::13 29813 # Per bank write bursts

63system.physmem.perBankRdBursts::14 29629 # Per bank write bursts

64system.physmem.perBankRdBursts::15 29805 # Per bank write bursts

64system.physmem.perBankRdBursts::15 29799 # Per bank write bursts

65system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
66system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
67system.physmem.perBankWrBursts::2 4138 # Per bank write bursts
68system.physmem.perBankWrBursts::3 4148 # Per bank write bursts
69system.physmem.perBankWrBursts::4 4226 # Per bank write bursts
70system.physmem.perBankWrBursts::5 4224 # Per bank write bursts

71system.physmem.perBankWrBursts::6 4174 # Per bank write bursts

71system.physmem.perBankWrBursts::6 4173 # Per bank write bursts

72system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
73system.physmem.perBankWrBursts::8 4096 # Per bank write bursts

74system.physmem.perBankWrBursts::9 4094 # Per bank write bursts
75system.physmem.perBankWrBursts::10 4096 # Per bank write bursts

74system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
75system.physmem.perBankWrBursts::10 4095 # Per bank write bursts

76system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
77system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
78system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
79system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
80system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

83system.physmem.totGap 633884833500 # Total gap between requests

83system.physmem.totGap 629535350500 # Total gap between requests

84system.physmem.readPktSize::0 0 # Read request sizes (log2)
85system.physmem.readPktSize::1 0 # Read request sizes (log2)
86system.physmem.readPktSize::2 0 # Read request sizes (log2)
87system.physmem.readPktSize::3 0 # Read request sizes (log2)
88system.physmem.readPktSize::4 0 # Read request sizes (log2)
89system.physmem.readPktSize::5 0 # Read request sizes (log2)

90system.physmem.readPktSize::6 474970 # Read request sizes (log2)

90system.physmem.readPktSize::6 474963 # Read request sizes (log2)

91system.physmem.writePktSize::0 0 # Write request sizes (log2)
92system.physmem.writePktSize::1 0 # Write request sizes (log2)
93system.physmem.writePktSize::2 0 # Write request sizes (log2)
94system.physmem.writePktSize::3 0 # Write request sizes (log2)
95system.physmem.writePktSize::4 0 # Write request sizes (log2)
96system.physmem.writePktSize::5 0 # Write request sizes (log2)
97system.physmem.writePktSize::6 66098 # Write request sizes (log2)

98system.physmem.rdQLenPdf::0 407902 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::1 66613 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see

98system.physmem.rdQLenPdf::0 407876 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::1 66617 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::2 275 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see

105system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see

--- 12 unchanged lines hidden (view full) ---

125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
130system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see

133system.physmem.wrQLenPdf::3 3004 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::4 3004 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::5 3004 # What write queue length does an incoming req see

133system.physmem.wrQLenPdf::3 3005 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::4 3005 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::5 3005 # What write queue length does an incoming req see

136system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::9 3004 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::10 3004 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::11 3004 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::12 3004 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::13 3004 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see

147system.physmem.wrQLenPdf::17 3005 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::18 3005 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::19 3004 # What write queue length does an incoming req see

147system.physmem.wrQLenPdf::17 3004 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::18 3004 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::19 3005 # What write queue length does an incoming req see

150system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see

151system.physmem.wrQLenPdf::21 3008 # What write queue length does an incoming req see

151system.physmem.wrQLenPdf::21 3006 # What write queue length does an incoming req see

152system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see

162system.physmem.bytesPerActivate::samples 190556 # Bytes accessed per row activation
163system.physmem.bytesPerActivate::mean 181.682403 # Bytes accessed per row activation
164system.physmem.bytesPerActivate::gmean 122.345891 # Bytes accessed per row activation
165system.physmem.bytesPerActivate::stdev 377.529861 # Bytes accessed per row activation
166system.physmem.bytesPerActivate::64 76623 40.21% 40.21% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::128 50018 26.25% 66.46% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::192 37571 19.72% 86.18% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::256 19599 10.29% 96.46% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::320 202 0.11% 96.57% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::384 233 0.12% 96.69% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::448 93 0.05% 96.74% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::512 219 0.11% 96.85% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::576 79 0.04% 96.89% # Bytes accessed per row activation

162system.physmem.bytesPerActivate::samples 190822 # Bytes accessed per row activation
163system.physmem.bytesPerActivate::mean 181.419082 # Bytes accessed per row activation
164system.physmem.bytesPerActivate::gmean 122.160667 # Bytes accessed per row activation
165system.physmem.bytesPerActivate::stdev 377.205430 # Bytes accessed per row activation
166system.physmem.bytesPerActivate::64 76972 40.34% 40.34% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::128 49989 26.20% 66.53% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::192 37639 19.72% 86.26% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::256 19482 10.21% 96.47% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::320 187 0.10% 96.57% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::384 252 0.13% 96.70% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::448 85 0.04% 96.74% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::512 218 0.11% 96.86% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::576 85 0.04% 96.90% # Bytes accessed per row activation

175system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation

176system.physmem.bytesPerActivate::704 59 0.03% 97.05% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::768 225 0.12% 97.16% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::832 74 0.04% 97.20% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::896 178 0.09% 97.30% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::960 61 0.03% 97.33% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1024 176 0.09% 97.42% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1088 47 0.02% 97.45% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1152 188 0.10% 97.54% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1216 71 0.04% 97.58% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1280 186 0.10% 97.68% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1344 71 0.04% 97.72% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1408 3176 1.67% 99.38% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1472 17 0.01% 99.39% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1536 14 0.01% 99.40% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1600 12 0.01% 99.41% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::1664 11 0.01% 99.41% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::1728 7 0.00% 99.41% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1792 10 0.01% 99.42% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1856 16 0.01% 99.43% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1920 14 0.01% 99.44% # Bytes accessed per row activation

176system.physmem.bytesPerActivate::704 52 0.03% 97.05% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::768 225 0.12% 97.17% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::832 65 0.03% 97.20% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::896 188 0.10% 97.30% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::960 60 0.03% 97.33% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::1024 181 0.09% 97.43% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::1088 44 0.02% 97.45% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1152 201 0.11% 97.55% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1216 67 0.04% 97.59% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1280 181 0.09% 97.68% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1344 66 0.03% 97.72% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1408 3167 1.66% 99.38% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1472 20 0.01% 99.39% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1536 13 0.01% 99.40% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1600 12 0.01% 99.40% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::1664 12 0.01% 99.41% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::1728 13 0.01% 99.42% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1792 17 0.01% 99.42% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1856 15 0.01% 99.43% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1920 15 0.01% 99.44% # Bytes accessed per row activation

196system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation

197system.physmem.bytesPerActivate::2048 23 0.01% 99.46% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::2112 18 0.01% 99.47% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::2176 9 0.00% 99.47% # Bytes accessed per row activation

197system.physmem.bytesPerActivate::2048 10 0.01% 99.46% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::2112 18 0.01% 99.46% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::2176 13 0.01% 99.47% # Bytes accessed per row activation

200system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation

201system.physmem.bytesPerActivate::2304 13 0.01% 99.48% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::2368 10 0.01% 99.49% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::2432 12 0.01% 99.50% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::2496 24 0.01% 99.51% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::2560 8 0.00% 99.51% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::2624 18 0.01% 99.52% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::2688 22 0.01% 99.53% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::2752 22 0.01% 99.55% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2816 14 0.01% 99.55% # Bytes accessed per row activation

201system.physmem.bytesPerActivate::2304 14 0.01% 99.48% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::2368 14 0.01% 99.49% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::2432 15 0.01% 99.50% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::2496 21 0.01% 99.51% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::2560 12 0.01% 99.52% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::2624 17 0.01% 99.53% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::2688 16 0.01% 99.53% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::2752 16 0.01% 99.54% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2816 13 0.01% 99.55% # Bytes accessed per row activation

210system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation

211system.physmem.bytesPerActivate::2944 11 0.01% 99.56% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::3008 10 0.01% 99.57% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::3072 8 0.00% 99.57% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::3136 14 0.01% 99.58% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::3200 4 0.00% 99.58% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::3264 19 0.01% 99.59% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::3328 19 0.01% 99.60% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::3392 21 0.01% 99.61% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::3456 17 0.01% 99.62% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::3520 18 0.01% 99.63% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::3584 12 0.01% 99.64% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::3648 19 0.01% 99.65% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::3712 10 0.01% 99.65% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3776 12 0.01% 99.66% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3840 10 0.01% 99.67% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3904 12 0.01% 99.67% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3968 16 0.01% 99.68% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::4032 16 0.01% 99.69% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::4096 16 0.01% 99.70% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::4160 31 0.02% 99.71% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::4224 17 0.01% 99.72% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::4288 10 0.01% 99.73% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::4352 9 0.00% 99.73% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::4416 11 0.01% 99.74% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::4480 6 0.00% 99.74% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::4544 17 0.01% 99.75% # Bytes accessed per row activation

211system.physmem.bytesPerActivate::2944 12 0.01% 99.56% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::3008 14 0.01% 99.57% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::3072 9 0.00% 99.57% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::3136 19 0.01% 99.58% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::3200 10 0.01% 99.59% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::3264 20 0.01% 99.60% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::3328 10 0.01% 99.61% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::3392 16 0.01% 99.61% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::3456 12 0.01% 99.62% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::3520 21 0.01% 99.63% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::3584 13 0.01% 99.64% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::3648 16 0.01% 99.65% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::3712 15 0.01% 99.65% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3776 18 0.01% 99.66% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3840 7 0.00% 99.67% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3904 15 0.01% 99.68% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3968 17 0.01% 99.68% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::4032 14 0.01% 99.69% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::4096 12 0.01% 99.70% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::4160 28 0.01% 99.71% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::4224 16 0.01% 99.72% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::4288 14 0.01% 99.73% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::4352 7 0.00% 99.73% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::4416 17 0.01% 99.74% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::4480 11 0.01% 99.75% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::4544 14 0.01% 99.75% # Bytes accessed per row activation

237system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation

238system.physmem.bytesPerActivate::4672 16 0.01% 99.77% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4736 14 0.01% 99.77% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4800 19 0.01% 99.78% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4864 17 0.01% 99.79% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4928 16 0.01% 99.80% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4992 3 0.00% 99.80% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::5056 13 0.01% 99.81% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::5120 6 0.00% 99.81% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::5184 7 0.00% 99.82% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::5248 7 0.00% 99.82% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::5312 10 0.01% 99.82% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::5376 14 0.01% 99.83% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::5440 20 0.01% 99.84% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::5504 16 0.01% 99.85% # Bytes accessed per row activation

238system.physmem.bytesPerActivate::4672 19 0.01% 99.77% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4736 10 0.01% 99.78% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4800 13 0.01% 99.78% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4864 9 0.00% 99.79% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4928 17 0.01% 99.80% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4992 8 0.00% 99.80% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::5056 17 0.01% 99.81% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::5120 7 0.00% 99.81% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::5184 9 0.00% 99.82% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::5248 9 0.00% 99.82% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::5312 13 0.01% 99.83% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::5376 11 0.01% 99.83% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::5440 14 0.01% 99.84% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::5504 12 0.01% 99.85% # Bytes accessed per row activation

252system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation

253system.physmem.bytesPerActivate::5632 12 0.01% 99.86% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::5696 34 0.02% 99.88% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::5760 69 0.04% 99.92% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::5824 58 0.03% 99.95% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::5888 3 0.00% 99.95% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5952 1 0.00% 99.95% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::6016 3 0.00% 99.95% # Bytes accessed per row activation

253system.physmem.bytesPerActivate::5632 15 0.01% 99.86% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::5696 31 0.02% 99.88% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::5760 73 0.04% 99.92% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::5824 59 0.03% 99.95% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::5888 4 0.00% 99.95% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5952 3 0.00% 99.95% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::6016 6 0.00% 99.96% # Bytes accessed per row activation

260system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation

261system.physmem.bytesPerActivate::6144 59 0.03% 99.99% # Bytes accessed per row activation

261system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # Bytes accessed per row activation

262system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation

264system.physmem.bytesPerActivate::total 190556 # Bytes accessed per row activation
265system.physmem.totQLat 3723849000 # Total ticks spent queuing
266system.physmem.totMemAccLat 15162897750 # Total ticks spent from burst creation until serviced by the DRAM
267system.physmem.totBusLat 2374375000 # Total ticks spent in databus transfers
268system.physmem.totBankLat 9064673750 # Total ticks spent accessing banks
269system.physmem.avgQLat 7841.75 # Average queueing delay per DRAM burst
270system.physmem.avgBankLat 19088.55 # Average bank access latency per DRAM burst

264system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation
265system.physmem.totQLat 3804882250 # Total ticks spent queuing
266system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM
267system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers
268system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks
269system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst
270system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst

271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

272system.physmem.avgMemAccLat 31930.29 # Average memory access latency per DRAM burst
273system.physmem.avgRdBW 47.95 # Average DRAM read bandwidth in MiByte/s
274system.physmem.avgWrBW 6.67 # Average achieved write bandwidth in MiByte/s
275system.physmem.avgRdBWSys 47.96 # Average system read bandwidth in MiByte/s
276system.physmem.avgWrBWSys 6.67 # Average system write bandwidth in MiByte/s

272system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst
273system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s
274system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s
275system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s
276system.physmem.avgWrBWSys 6.72 # Average system write bandwidth in MiByte/s

277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
278system.physmem.busUtil 0.43 # Data bus utilization in percentage

279system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads

279system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads

280system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
281system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing

282system.physmem.avgWrQLen 4.41 # Average write queue length when enqueuing
283system.physmem.readRowHits 301072 # Number of row buffer hits during reads
284system.physmem.writeRowHits 49342 # Number of row buffer hits during writes
285system.physmem.readRowHitRate 63.40 # Row buffer hit rate for reads
286system.physmem.writeRowHitRate 74.65 # Row buffer hit rate for writes
287system.physmem.avgGap 1171543.75 # Average gap between requests
288system.physmem.pageHitRate 64.77 # Row buffer hit rate, read and write combined
289system.physmem.prechargeAllPercent 24.91 # Percentage of time for which DRAM has all the banks in precharge state
290system.membus.throughput 54628770 # Throughput (bytes/s)
291system.membus.trans_dist::ReadReq 408895 # Transaction distribution
292system.membus.trans_dist::ReadResp 408895 # Transaction distribution

282system.physmem.avgWrQLen 6.84 # Average write queue length when enqueuing
283system.physmem.readRowHits 300749 # Number of row buffer hits during reads
284system.physmem.writeRowHits 49371 # Number of row buffer hits during writes
285system.physmem.readRowHitRate 63.34 # Row buffer hit rate for reads
286system.physmem.writeRowHitRate 74.69 # Row buffer hit rate for writes
287system.physmem.avgGap 1163520.10 # Average gap between requests
288system.physmem.pageHitRate 64.72 # Row buffer hit rate, read and write combined
289system.physmem.prechargeAllPercent 24.30 # Percentage of time for which DRAM has all the banks in precharge state
290system.membus.throughput 55005389 # Throughput (bytes/s)
291system.membus.trans_dist::ReadReq 408886 # Transaction distribution
292system.membus.trans_dist::ReadResp 408885 # Transaction distribution

293system.membus.trans_dist::Writeback 66098 # Transaction distribution

294system.membus.trans_dist::UpgradeReq 4324 # Transaction distribution
295system.membus.trans_dist::UpgradeResp 4324 # Transaction distribution
296system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
297system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
298system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024686 # Packet count per connected master and slave (bytes)
299system.membus.pkt_count::total 1024686 # Packet count per connected master and slave (bytes)
300system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34628352 # Cumulative packet size per connected master and slave (bytes)
301system.membus.tot_pkt_size::total 34628352 # Cumulative packet size per connected master and slave (bytes)
302system.membus.data_through_bus 34628352 # Total data (bytes)

294system.membus.trans_dist::UpgradeReq 4262 # Transaction distribution
295system.membus.trans_dist::UpgradeResp 4262 # Transaction distribution
296system.membus.trans_dist::ReadExReq 66077 # Transaction distribution
297system.membus.trans_dist::ReadExResp 66077 # Transaction distribution
298system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024547 # Packet count per connected master and slave (bytes)
299system.membus.pkt_count::total 1024547 # Packet count per connected master and slave (bytes)
300system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627840 # Cumulative packet size per connected master and slave (bytes)
301system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes)
302system.membus.data_through_bus 34627840 # Total data (bytes)

303system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)

304system.membus.reqLayer0.occupancy 1216897000 # Layer occupancy (ticks)

304system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks)

305system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)

306system.membus.respLayer1.occupancy 4442648676 # Layer occupancy (ticks)

306system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks)

307system.membus.respLayer1.utilization 0.7 # Layer utilization (%)

308system.cpu.branchPred.lookups 445875274 # Number of BP lookups
309system.cpu.branchPred.condPredicted 355714891 # Number of conditional branches predicted
310system.cpu.branchPred.condIncorrect 31013117 # Number of conditional branches incorrect
311system.cpu.branchPred.BTBLookups 262160312 # Number of BTB lookups
312system.cpu.branchPred.BTBHits 234316871 # Number of BTB hits

308system.cpu.branchPred.lookups 438247561 # Number of BP lookups
309system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted
310system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect
311system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups
312system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits

313system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

314system.cpu.branchPred.BTBHitPct 89.379231 # BTB Hit Percentage
315system.cpu.branchPred.usedRAS 52540791 # Number of times the RAS was used to get a target.
316system.cpu.branchPred.RASInCorrect 2805997 # Number of incorrect RAS predictions.

314system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage
315system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target.
316system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions.

317system.cpu.dtb.inst_hits 0 # ITB inst hits
318system.cpu.dtb.inst_misses 0 # ITB inst misses
319system.cpu.dtb.read_hits 0 # DTB read hits
320system.cpu.dtb.read_misses 0 # DTB read misses
321system.cpu.dtb.write_hits 0 # DTB write hits
322system.cpu.dtb.write_misses 0 # DTB write misses
323system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
324system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 27 unchanged lines hidden (view full) ---

352system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
353system.cpu.itb.read_accesses 0 # DTB read accesses
354system.cpu.itb.write_accesses 0 # DTB write accesses
355system.cpu.itb.inst_accesses 0 # ITB inst accesses
356system.cpu.itb.hits 0 # DTB hits
357system.cpu.itb.misses 0 # DTB misses
358system.cpu.itb.accesses 0 # DTB accesses
359system.cpu.workload.num_syscalls 1411 # Number of system calls

360system.cpu.numCycles 1267769796 # number of cpu cycles simulated

360system.cpu.numCycles 1259070828 # number of cpu cycles simulated

361system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
362system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

363system.cpu.fetch.icacheStallCycles 359604051 # Number of cycles fetch is stalled on an Icache miss
364system.cpu.fetch.Insts 2297734506 # Number of instructions fetch has processed
365system.cpu.fetch.Branches 445875274 # Number of branches that fetch encountered
366system.cpu.fetch.predictedBranches 286857662 # Number of branches that fetch has predicted taken
367system.cpu.fetch.Cycles 606667357 # Number of cycles fetch has run and was not squashing or blocked
368system.cpu.fetch.SquashCycles 159378109 # Number of cycles fetch has spent squashing
369system.cpu.fetch.BlockedCycles 130943287 # Number of cycles fetch has spent blocked
370system.cpu.fetch.MiscStallCycles 611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
371system.cpu.fetch.PendingTrapStallCycles 11360 # Number of stall cycles due to pending traps
372system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR
373system.cpu.fetch.CacheLines 340050056 # Number of cache lines fetched
374system.cpu.fetch.IcacheSquashes 11891209 # Number of outstanding Icache misses that were squashed
375system.cpu.fetch.rateDist::samples 1225539818 # Number of instructions fetched each cycle (Total)
376system.cpu.fetch.rateDist::mean 2.573745 # Number of instructions fetched each cycle (Total)
377system.cpu.fetch.rateDist::stdev 3.170795 # Number of instructions fetched each cycle (Total)

363system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss
364system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed
365system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered
366system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken
367system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked
368system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing
369system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked
370system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
371system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps
372system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR
373system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched
374system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed
375system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total)
376system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total)
377system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total)

378system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

379system.cpu.fetch.rateDist::0 618917347 50.50% 50.50% # Number of instructions fetched each cycle (Total)
380system.cpu.fetch.rateDist::1 42971146 3.51% 54.01% # Number of instructions fetched each cycle (Total)
381system.cpu.fetch.rateDist::2 97897325 7.99% 62.00% # Number of instructions fetched each cycle (Total)
382system.cpu.fetch.rateDist::3 56071890 4.58% 66.57% # Number of instructions fetched each cycle (Total)
383system.cpu.fetch.rateDist::4 75061628 6.12% 72.70% # Number of instructions fetched each cycle (Total)
384system.cpu.fetch.rateDist::5 45063261 3.68% 76.37% # Number of instructions fetched each cycle (Total)
385system.cpu.fetch.rateDist::6 31435951 2.57% 78.94% # Number of instructions fetched each cycle (Total)
386system.cpu.fetch.rateDist::7 31903606 2.60% 81.54% # Number of instructions fetched each cycle (Total)
387system.cpu.fetch.rateDist::8 226217664 18.46% 100.00% # Number of instructions fetched each cycle (Total)

379system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total)
380system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total)
381system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total)
382system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total)
383system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total)
384system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total)
385system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total)
386system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total)
387system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total)

388system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
389system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
390system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

391system.cpu.fetch.rateDist::total 1225539818 # Number of instructions fetched each cycle (Total)
392system.cpu.fetch.branchRate 0.351701 # Number of branch fetches per cycle
393system.cpu.fetch.rate 1.812423 # Number of inst fetches per cycle
394system.cpu.decode.IdleCycles 410024939 # Number of cycles decode is idle
395system.cpu.decode.BlockedCycles 104223819 # Number of cycles decode is blocked
396system.cpu.decode.RunCycles 567090713 # Number of cycles decode is running
397system.cpu.decode.UnblockCycles 15899066 # Number of cycles decode is unblocking
398system.cpu.decode.SquashCycles 128301281 # Number of cycles decode is squashing
399system.cpu.decode.BranchResolved 47087821 # Number of times decode resolved a branch
400system.cpu.decode.BranchMispred 11947 # Number of times decode detected a branch misprediction
401system.cpu.decode.DecodedInsts 3044373258 # Number of instructions handled by decode
402system.cpu.decode.SquashedInsts 26488 # Number of squashed instructions handled by decode
403system.cpu.rename.SquashCycles 128301281 # Number of cycles rename is squashing
404system.cpu.rename.IdleCycles 445072814 # Number of cycles rename is idle
405system.cpu.rename.BlockCycles 37752394 # Number of cycles rename is blocking
406system.cpu.rename.serializeStallCycles 469546 # count of cycles rename stalled for serializing inst
407system.cpu.rename.RunCycles 545867989 # Number of cycles rename is running
408system.cpu.rename.UnblockCycles 68075794 # Number of cycles rename is unblocking
409system.cpu.rename.RenamedInsts 2962731385 # Number of instructions processed by rename
410system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full
411system.cpu.rename.IQFullEvents 4402501 # Number of times rename has blocked due to IQ full
412system.cpu.rename.LSQFullEvents 53439360 # Number of times rename has blocked due to LSQ full
413system.cpu.rename.FullRegisterEvents 9 # Number of times there has been no free registers
414system.cpu.rename.RenamedOperands 2946792223 # Number of destination operands rename has renamed
415system.cpu.rename.RenameLookups 14100168268 # Number of register rename lookups that rename has made
416system.cpu.rename.int_rename_lookups 12232464769 # Number of integer rename lookups
417system.cpu.rename.fp_rename_lookups 87261724 # Number of floating rename lookups

391system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total)
392system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle
393system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle
394system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle
395system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked
396system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running
397system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking
398system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing
399system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch
400system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction
401system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode
402system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode
403system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing
404system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle
405system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking
406system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst
407system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running
408system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking
409system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename
410system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full
411system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full
412system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full
413system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
414system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed
415system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made
416system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups
417system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups

418system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed

419system.cpu.rename.UndoneMaps 953652133 # Number of HB maps that are undone due to squashing
420system.cpu.rename.serializingInsts 20387 # count of serializing insts renamed
421system.cpu.rename.tempSerializingInsts 17854 # count of temporary serializing insts renamed
422system.cpu.rename.skidInsts 175792199 # count of insts added to the skid buffer
423system.cpu.memDep0.insertedLoads 972804227 # Number of loads inserted to the mem dependence unit.
424system.cpu.memDep0.insertedStores 491413736 # Number of stores inserted to the mem dependence unit.
425system.cpu.memDep0.conflictingLoads 36509550 # Number of conflicting loads.
426system.cpu.memDep0.conflictingStores 42116928 # Number of conflicting stores.
427system.cpu.iq.iqInstsAdded 2808310459 # Number of instructions added to the IQ (excludes non-spec)
428system.cpu.iq.iqNonSpecInstsAdded 27673 # Number of non-speculative instructions added to the IQ
429system.cpu.iq.iqInstsIssued 2443543142 # Number of instructions issued
430system.cpu.iq.iqSquashedInstsIssued 13552705 # Number of squashed instructions issued
431system.cpu.iq.iqSquashedInstsExamined 910455744 # Number of squashed instructions iterated over during squash; mainly for profiling
432system.cpu.iq.iqSquashedOperandsExamined 2345608138 # Number of squashed operands that are examined and possibly removed from graph
433system.cpu.iq.iqSquashedNonSpecRemoved 6289 # Number of squashed non-spec instructions that were removed
434system.cpu.iq.issued_per_cycle::samples 1225539818 # Number of insts issued each cycle
435system.cpu.iq.issued_per_cycle::mean 1.993850 # Number of insts issued each cycle
436system.cpu.iq.issued_per_cycle::stdev 1.871016 # Number of insts issued each cycle

419system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing
420system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed
421system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed
422system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer
423system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit.
424system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit.
425system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads.
426system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores.
427system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec)
428system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ
429system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued
430system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued
431system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling
432system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph
433system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed
434system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle
435system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle
436system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle

437system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

438system.cpu.iq.issued_per_cycle::0 386142313 31.51% 31.51% # Number of insts issued each cycle
439system.cpu.iq.issued_per_cycle::1 183212489 14.95% 46.46% # Number of insts issued each cycle
440system.cpu.iq.issued_per_cycle::2 204921233 16.72% 63.18% # Number of insts issued each cycle
441system.cpu.iq.issued_per_cycle::3 171581285 14.00% 77.18% # Number of insts issued each cycle
442system.cpu.iq.issued_per_cycle::4 134431508 10.97% 88.15% # Number of insts issued each cycle
443system.cpu.iq.issued_per_cycle::5 92278264 7.53% 95.68% # Number of insts issued each cycle
444system.cpu.iq.issued_per_cycle::6 37194117 3.03% 98.71% # Number of insts issued each cycle
445system.cpu.iq.issued_per_cycle::7 12766594 1.04% 99.75% # Number of insts issued each cycle
446system.cpu.iq.issued_per_cycle::8 3012015 0.25% 100.00% # Number of insts issued each cycle

438system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle
439system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle
440system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle
441system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle
442system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle
443system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle
444system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle
445system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle
446system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle

447system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
448system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
449system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

450system.cpu.iq.issued_per_cycle::total 1225539818 # Number of insts issued each cycle

450system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle

451system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

452system.cpu.iq.fu_full::IntAlu 692354 0.79% 0.79% # attempts to use FU when none available
453system.cpu.iq.fu_full::IntMult 24381 0.03% 0.81% # attempts to use FU when none available
454system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available
455system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available
456system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available
457system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available
458system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available
459system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available
460system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
461system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available
462system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available
463system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available
464system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available
465system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available
466system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available
467system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available
468system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available
469system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available
470system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available
471system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available
472system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available
473system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available
474system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available
475system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available
476system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available
477system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available
478system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available
479system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available
480system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
481system.cpu.iq.fu_full::MemRead 55108221 62.64% 63.46% # attempts to use FU when none available
482system.cpu.iq.fu_full::MemWrite 32145057 36.54% 100.00% # attempts to use FU when none available

452system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available
453system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available
454system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
455system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
456system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
457system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
458system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
459system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
460system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
461system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available
462system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available
463system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available
464system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available
465system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available
466system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available
467system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available
468system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available
469system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available
470system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available
471system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available
472system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available
473system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
474system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
475system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
476system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
477system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
478system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
479system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
480system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
481system.cpu.iq.fu_full::MemRead 55158409 62.92% 63.76% # attempts to use FU when none available
482system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # attempts to use FU when none available

483system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
484system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
485system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

486system.cpu.iq.FU_type_0::IntAlu 1110380096 45.44% 45.44% # Type of FU issued
487system.cpu.iq.FU_type_0::IntMult 11223911 0.46% 45.90% # Type of FU issued
488system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.90% # Type of FU issued
489system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.90% # Type of FU issued
490system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.90% # Type of FU issued
491system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.90% # Type of FU issued
492system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.90% # Type of FU issued
493system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.90% # Type of FU issued
494system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.90% # Type of FU issued
495system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.90% # Type of FU issued
496system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.90% # Type of FU issued
497system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.90% # Type of FU issued
498system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.90% # Type of FU issued
499system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.90% # Type of FU issued
500system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.90% # Type of FU issued
501system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.90% # Type of FU issued
502system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.90% # Type of FU issued
503system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.90% # Type of FU issued
504system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.90% # Type of FU issued
505system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.90% # Type of FU issued
506system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.96% # Type of FU issued
507system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.96% # Type of FU issued
508system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.24% # Type of FU issued
509system.cpu.iq.FU_type_0::SimdFloatCvt 5502670 0.23% 46.46% # Type of FU issued
510system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.46% # Type of FU issued
511system.cpu.iq.FU_type_0::SimdFloatMisc 23408416 0.96% 47.42% # Type of FU issued
512system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.42% # Type of FU issued
513system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.42% # Type of FU issued
514system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.42% # Type of FU issued
515system.cpu.iq.FU_type_0::MemRead 840781219 34.41% 81.83% # Type of FU issued
516system.cpu.iq.FU_type_0::MemWrite 443995061 18.17% 100.00% # Type of FU issued

486system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued
487system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued
488system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued
489system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued
490system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.81% # Type of FU issued
491system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.81% # Type of FU issued
492system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.81% # Type of FU issued
493system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.81% # Type of FU issued
494system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.81% # Type of FU issued
495system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.81% # Type of FU issued
496system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.81% # Type of FU issued
497system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.81% # Type of FU issued
498system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.81% # Type of FU issued
499system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.81% # Type of FU issued
500system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.81% # Type of FU issued
501system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.81% # Type of FU issued
502system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.81% # Type of FU issued
503system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.81% # Type of FU issued
504system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.81% # Type of FU issued
505system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.81% # Type of FU issued
506system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.86% # Type of FU issued
507system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.86% # Type of FU issued
508system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.15% # Type of FU issued
509system.cpu.iq.FU_type_0::SimdFloatCvt 5502438 0.23% 46.37% # Type of FU issued
510system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.37% # Type of FU issued
511system.cpu.iq.FU_type_0::SimdFloatMisc 23399832 0.96% 47.33% # Type of FU issued
512system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
513system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued
514system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
515system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Type of FU issued
516system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued

517system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
518system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

519system.cpu.iq.FU_type_0::total 2443543142 # Type of FU issued
520system.cpu.iq.rate 1.927434 # Inst issue rate
521system.cpu.iq.fu_busy_cnt 87970013 # FU busy when requested
522system.cpu.iq.fu_busy_rate 0.036001 # FU busy rate (busy events/executed inst)
523system.cpu.iq.int_inst_queue_reads 6090822143 # Number of integer instruction queue reads
524system.cpu.iq.int_inst_queue_writes 3633185531 # Number of integer instruction queue writes
525system.cpu.iq.int_inst_queue_wakeup_accesses 2257760958 # Number of integer instruction queue wakeup accesses
526system.cpu.iq.fp_inst_queue_reads 123326677 # Number of floating instruction queue reads
527system.cpu.iq.fp_inst_queue_writes 85675338 # Number of floating instruction queue writes
528system.cpu.iq.fp_inst_queue_wakeup_accesses 56498576 # Number of floating instruction queue wakeup accesses
529system.cpu.iq.int_alu_accesses 2467787139 # Number of integer alu accesses
530system.cpu.iq.fp_alu_accesses 63726016 # Number of floating point alu accesses
531system.cpu.iew.lsq.thread0.forwLoads 85165626 # Number of loads that had data forwarded from stores

519system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued
520system.cpu.iq.rate 1.934087 # Inst issue rate
521system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested
522system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst)
523system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads
524system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes
525system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses
526system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads
527system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes
528system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses
529system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses
530system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses
531system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores

532system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

533system.cpu.iew.lsq.thread0.squashedLoads 341417046 # Number of loads squashed
534system.cpu.iew.lsq.thread0.ignoredResponses 38150 # Number of memory responses ignored because the instruction is squashed
535system.cpu.iew.lsq.thread0.memOrderViolation 1428012 # Number of memory ordering violations
536system.cpu.iew.lsq.thread0.squashedStores 214418439 # Number of stores squashed

533system.cpu.iew.lsq.thread0.squashedLoads 340360670 # Number of loads squashed
534system.cpu.iew.lsq.thread0.ignoredResponses 9529 # Number of memory responses ignored because the instruction is squashed
535system.cpu.iew.lsq.thread0.memOrderViolation 1430281 # Number of memory ordering violations
536system.cpu.iew.lsq.thread0.squashedStores 208692629 # Number of stores squashed

537system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
538system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

539system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
540system.cpu.iew.lsq.thread0.cacheBlocked 322 # Number of times an access to memory failed due to the cache being blocked

539system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
540system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked

541system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

542system.cpu.iew.iewSquashCycles 128301281 # Number of cycles IEW is squashing
543system.cpu.iew.iewBlockCycles 16032166 # Number of cycles IEW is blocking
544system.cpu.iew.iewUnblockCycles 1560767 # Number of cycles IEW is unblocking
545system.cpu.iew.iewDispatchedInsts 2808350603 # Number of instructions dispatched to IQ
546system.cpu.iew.iewDispSquashedInsts 961806 # Number of squashed instructions skipped by dispatch
547system.cpu.iew.iewDispLoadInsts 972804227 # Number of dispatched load instructions
548system.cpu.iew.iewDispStoreInsts 491413736 # Number of dispatched store instructions
549system.cpu.iew.iewDispNonSpecInsts 17687 # Number of dispatched non-speculative instructions
550system.cpu.iew.iewIQFullEvents 1557116 # Number of times the IQ has become full, causing a stall
551system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall
552system.cpu.iew.memOrderViolationEvents 1428012 # Number of memory order violations
553system.cpu.iew.predictedTakenIncorrect 32911757 # Number of branches that were predicted taken incorrectly
554system.cpu.iew.predictedNotTakenIncorrect 1861954 # Number of branches that were predicted not taken incorrectly
555system.cpu.iew.branchMispredicts 34773711 # Number of branch mispredicts detected at execute
556system.cpu.iew.iewExecutedInsts 2367002070 # Number of executed instructions
557system.cpu.iew.iewExecLoadInsts 794874980 # Number of load instructions executed
558system.cpu.iew.iewExecSquashedInsts 76541072 # Number of squashed instructions skipped in execute

542system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing
543system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking
544system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking
545system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ
546system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch
547system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions
548system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions
549system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions
550system.cpu.iew.iewIQFullEvents 1559989 # Number of times the IQ has become full, causing a stall
551system.cpu.iew.iewLSQFullEvents 2525 # Number of times the LSQ has become full, causing a stall
552system.cpu.iew.memOrderViolationEvents 1430281 # Number of memory order violations
553system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly
554system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly
555system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute
556system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions
557system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed
558system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute

559system.cpu.iew.exec_swp 0 # number of swp insts executed

560system.cpu.iew.exec_nop 12471 # number of nop insts executed
561system.cpu.iew.exec_refs 1219940656 # number of memory reference insts executed
562system.cpu.iew.exec_branches 321608336 # Number of branches executed
563system.cpu.iew.exec_stores 425065676 # Number of stores executed
564system.cpu.iew.exec_rate 1.867060 # Inst execution rate
565system.cpu.iew.wb_sent 2340031230 # cumulative count of insts sent to commit
566system.cpu.iew.wb_count 2314259534 # cumulative count of insts written-back
567system.cpu.iew.wb_producers 1351078205 # num instructions producing a value
568system.cpu.iew.wb_consumers 2527156960 # num instructions consuming a value

560system.cpu.iew.exec_nop 12446 # number of nop insts executed
561system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed
562system.cpu.iew.exec_branches 319532182 # Number of branches executed
563system.cpu.iew.exec_stores 423276586 # Number of stores executed
564system.cpu.iew.exec_rate 1.874346 # Inst execution rate
565system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit
566system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back
567system.cpu.iew.wb_producers 1349155886 # num instructions producing a value
568system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value

569system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

570system.cpu.iew.wb_rate 1.825457 # insts written-back per cycle
571system.cpu.iew.wb_fanout 0.534624 # average fanout of values written-back

570system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle
571system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back

572system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

573system.cpu.commit.commitSquashedInsts 923014366 # The number of squashed insts skipped by commit

573system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit

574system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards

575system.cpu.commit.branchMispredicts 31001379 # The number of times a branch was mispredicted
576system.cpu.commit.committed_per_cycle::samples 1097238537 # Number of insts commited each cycle
577system.cpu.commit.committed_per_cycle::mean 1.718256 # Number of insts commited each cycle
578system.cpu.commit.committed_per_cycle::stdev 2.389874 # Number of insts commited each cycle

575system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted
576system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle
577system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle
578system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle

579system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

580system.cpu.commit.committed_per_cycle::0 455331878 41.50% 41.50% # Number of insts commited each cycle
581system.cpu.commit.committed_per_cycle::1 289999556 26.43% 67.93% # Number of insts commited each cycle
582system.cpu.commit.committed_per_cycle::2 95581485 8.71% 76.64% # Number of insts commited each cycle
583system.cpu.commit.committed_per_cycle::3 70096070 6.39% 83.03% # Number of insts commited each cycle
584system.cpu.commit.committed_per_cycle::4 46571745 4.24% 87.27% # Number of insts commited each cycle
585system.cpu.commit.committed_per_cycle::5 22195585 2.02% 89.29% # Number of insts commited each cycle
586system.cpu.commit.committed_per_cycle::6 15856765 1.45% 90.74% # Number of insts commited each cycle
587system.cpu.commit.committed_per_cycle::7 11363497 1.04% 91.78% # Number of insts commited each cycle
588system.cpu.commit.committed_per_cycle::8 90241956 8.22% 100.00% # Number of insts commited each cycle

580system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle
581system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle
582system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle
583system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle
584system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle
585system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle
586system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle
587system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle
588system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle

589system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
590system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
591system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

592system.cpu.commit.committed_per_cycle::total 1097238537 # Number of insts commited each cycle

592system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle

593system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
594system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
595system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
596system.cpu.commit.refs 908382478 # Number of memory references committed
597system.cpu.commit.loads 631387181 # Number of loads committed
598system.cpu.commit.membars 9986 # Number of memory barriers committed
599system.cpu.commit.branches 298259106 # Number of branches committed
600system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
601system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
602system.cpu.commit.function_calls 41577833 # Number of function calls committed.

603system.cpu.commit.bw_lim_events 90241956 # number cycles where commit BW limit reached

603system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached

604system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

605system.cpu.rob.rob_reads 3815328960 # The number of ROB reads
606system.cpu.rob.rob_writes 5745013824 # The number of ROB writes
607system.cpu.timesIdled 352945 # Number of times that the entire CPU went into an idle state and unscheduled itself
608system.cpu.idleCycles 42229978 # Total number of cycles that the CPU has spent unscheduled due to idling

605system.cpu.rob.rob_reads 3791959297 # The number of ROB reads
606system.cpu.rob.rob_writes 5711929091 # The number of ROB writes
607system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself
608system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling

609system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
610system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
611system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated

612system.cpu.cpi 0.915773 # CPI: Cycles Per Instruction
613system.cpu.cpi_total 0.915773 # CPI: Total CPI of All Threads
614system.cpu.ipc 1.091973 # IPC: Instructions Per Cycle
615system.cpu.ipc_total 1.091973 # IPC: Total IPC of All Threads
616system.cpu.int_regfile_reads 11799440532 # number of integer regfile reads
617system.cpu.int_regfile_writes 2227507770 # number of integer regfile writes
618system.cpu.fp_regfile_reads 68853045 # number of floating regfile reads
619system.cpu.fp_regfile_writes 49554235 # number of floating regfile writes
620system.cpu.misc_regfile_reads 1367872939 # number of misc regfile reads

612system.cpu.cpi 0.909490 # CPI: Cycles Per Instruction
613system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads
614system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle
615system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads
616system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads
617system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes
618system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads
619system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes
620system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads

621system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes

622system.cpu.toL2Bus.throughput 167773046 # Throughput (bytes/s)
623system.cpu.toL2Bus.trans_dist::ReadReq 1492868 # Transaction distribution
624system.cpu.toL2Bus.trans_dist::ReadResp 1492867 # Transaction distribution
625system.cpu.toL2Bus.trans_dist::Writeback 96315 # Transaction distribution
626system.cpu.toL2Bus.trans_dist::UpgradeReq 4328 # Transaction distribution
627system.cpu.toL2Bus.trans_dist::UpgradeResp 4328 # Transaction distribution

622system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s)
623system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution
624system.cpu.toL2Bus.trans_dist::ReadResp 1493830 # Transaction distribution
625system.cpu.toL2Bus.trans_dist::Writeback 96313 # Transaction distribution
626system.cpu.toL2Bus.trans_dist::UpgradeReq 4265 # Transaction distribution
627system.cpu.toL2Bus.trans_dist::UpgradeResp 4265 # Transaction distribution

628system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution
629system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution

630system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52441 # Packet count per connected master and slave (bytes)
631system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178974 # Packet count per connected master and slave (bytes)
632system.cpu.toL2Bus.pkt_count::total 3231415 # Packet count per connected master and slave (bytes)
633system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1539648 # Cumulative packet size per connected master and slave (bytes)
634system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104532224 # Cumulative packet size per connected master and slave (bytes)
635system.cpu.toL2Bus.tot_pkt_size::total 106071872 # Cumulative packet size per connected master and slave (bytes)
636system.cpu.toL2Bus.data_through_bus 106071872 # Total data (bytes)
637system.cpu.toL2Bus.snoop_data_through_bus 276928 # Total snoop data (bytes)
638system.cpu.toL2Bus.reqLayer0.occupancy 929329999 # Layer occupancy (ticks)

630system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54300 # Packet count per connected master and slave (bytes)
631system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178976 # Packet count per connected master and slave (bytes)
632system.cpu.toL2Bus.pkt_count::total 3233276 # Packet count per connected master and slave (bytes)
633system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1601152 # Cumulative packet size per connected master and slave (bytes)
634system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536256 # Cumulative packet size per connected master and slave (bytes)
635system.cpu.toL2Bus.tot_pkt_size::total 106137408 # Cumulative packet size per connected master and slave (bytes)
636system.cpu.toL2Bus.data_through_bus 106137408 # Total data (bytes)
637system.cpu.toL2Bus.snoop_data_through_bus 272896 # Total snoop data (bytes)
638system.cpu.toL2Bus.reqLayer0.occupancy 929776999 # Layer occupancy (ticks)

639system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)

640system.cpu.toL2Bus.respLayer0.occupancy 42995247 # Layer occupancy (ticks)

640system.cpu.toL2Bus.respLayer0.occupancy 44342246 # Layer occupancy (ticks)

641system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

642system.cpu.toL2Bus.respLayer1.occupancy 2368559798 # Layer occupancy (ticks)

642system.cpu.toL2Bus.respLayer1.occupancy 2368551488 # Layer occupancy (ticks)

643system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)

644system.cpu.icache.tags.replacements 22373 # number of replacements
645system.cpu.icache.tags.tagsinuse 1644.727747 # Cycle average of tags in use
646system.cpu.icache.tags.total_refs 340012575 # Total number of references to valid blocks.
647system.cpu.icache.tags.sampled_refs 24056 # Sample count of references to valid blocks.
648system.cpu.icache.tags.avg_refs 14134.210800 # Average number of references to valid blocks.

644system.cpu.icache.tags.replacements 23332 # number of replacements
645system.cpu.icache.tags.tagsinuse 1641.273486 # Cycle average of tags in use
646system.cpu.icache.tags.total_refs 334698554 # Total number of references to valid blocks.
647system.cpu.icache.tags.sampled_refs 25017 # Sample count of references to valid blocks.
648system.cpu.icache.tags.avg_refs 13378.844546 # Average number of references to valid blocks.

649system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

650system.cpu.icache.tags.occ_blocks::cpu.inst 1644.727747 # Average occupied blocks per requestor
651system.cpu.icache.tags.occ_percent::cpu.inst 0.803090 # Average percentage of cache occupancy
652system.cpu.icache.tags.occ_percent::total 0.803090 # Average percentage of cache occupancy
653system.cpu.icache.ReadReq_hits::cpu.inst 340019150 # number of ReadReq hits
654system.cpu.icache.ReadReq_hits::total 340019150 # number of ReadReq hits
655system.cpu.icache.demand_hits::cpu.inst 340019150 # number of demand (read+write) hits
656system.cpu.icache.demand_hits::total 340019150 # number of demand (read+write) hits
657system.cpu.icache.overall_hits::cpu.inst 340019150 # number of overall hits
658system.cpu.icache.overall_hits::total 340019150 # number of overall hits
659system.cpu.icache.ReadReq_misses::cpu.inst 30904 # number of ReadReq misses
660system.cpu.icache.ReadReq_misses::total 30904 # number of ReadReq misses
661system.cpu.icache.demand_misses::cpu.inst 30904 # number of demand (read+write) misses
662system.cpu.icache.demand_misses::total 30904 # number of demand (read+write) misses
663system.cpu.icache.overall_misses::cpu.inst 30904 # number of overall misses
664system.cpu.icache.overall_misses::total 30904 # number of overall misses
665system.cpu.icache.ReadReq_miss_latency::cpu.inst 530577244 # number of ReadReq miss cycles
666system.cpu.icache.ReadReq_miss_latency::total 530577244 # number of ReadReq miss cycles
667system.cpu.icache.demand_miss_latency::cpu.inst 530577244 # number of demand (read+write) miss cycles
668system.cpu.icache.demand_miss_latency::total 530577244 # number of demand (read+write) miss cycles
669system.cpu.icache.overall_miss_latency::cpu.inst 530577244 # number of overall miss cycles
670system.cpu.icache.overall_miss_latency::total 530577244 # number of overall miss cycles
671system.cpu.icache.ReadReq_accesses::cpu.inst 340050054 # number of ReadReq accesses(hits+misses)
672system.cpu.icache.ReadReq_accesses::total 340050054 # number of ReadReq accesses(hits+misses)
673system.cpu.icache.demand_accesses::cpu.inst 340050054 # number of demand (read+write) accesses
674system.cpu.icache.demand_accesses::total 340050054 # number of demand (read+write) accesses
675system.cpu.icache.overall_accesses::cpu.inst 340050054 # number of overall (read+write) accesses
676system.cpu.icache.overall_accesses::total 340050054 # number of overall (read+write) accesses
677system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses
678system.cpu.icache.ReadReq_miss_rate::total 0.000091 # miss rate for ReadReq accesses
679system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses
680system.cpu.icache.demand_miss_rate::total 0.000091 # miss rate for demand accesses
681system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses
682system.cpu.icache.overall_miss_rate::total 0.000091 # miss rate for overall accesses
683system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17168.562128 # average ReadReq miss latency
684system.cpu.icache.ReadReq_avg_miss_latency::total 17168.562128 # average ReadReq miss latency
685system.cpu.icache.demand_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency
686system.cpu.icache.demand_avg_miss_latency::total 17168.562128 # average overall miss latency
687system.cpu.icache.overall_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency
688system.cpu.icache.overall_avg_miss_latency::total 17168.562128 # average overall miss latency
689system.cpu.icache.blocked_cycles::no_mshrs 1738 # number of cycles access was blocked

650system.cpu.icache.tags.occ_blocks::cpu.inst 1641.273486 # Average occupied blocks per requestor
651system.cpu.icache.tags.occ_percent::cpu.inst 0.801403 # Average percentage of cache occupancy
652system.cpu.icache.tags.occ_percent::total 0.801403 # Average percentage of cache occupancy
653system.cpu.icache.ReadReq_hits::cpu.inst 334702534 # number of ReadReq hits
654system.cpu.icache.ReadReq_hits::total 334702534 # number of ReadReq hits
655system.cpu.icache.demand_hits::cpu.inst 334702534 # number of demand (read+write) hits
656system.cpu.icache.demand_hits::total 334702534 # number of demand (read+write) hits
657system.cpu.icache.overall_hits::cpu.inst 334702534 # number of overall hits
658system.cpu.icache.overall_hits::total 334702534 # number of overall hits
659system.cpu.icache.ReadReq_misses::cpu.inst 32107 # number of ReadReq misses
660system.cpu.icache.ReadReq_misses::total 32107 # number of ReadReq misses
661system.cpu.icache.demand_misses::cpu.inst 32107 # number of demand (read+write) misses
662system.cpu.icache.demand_misses::total 32107 # number of demand (read+write) misses
663system.cpu.icache.overall_misses::cpu.inst 32107 # number of overall misses
664system.cpu.icache.overall_misses::total 32107 # number of overall misses
665system.cpu.icache.ReadReq_miss_latency::cpu.inst 545585992 # number of ReadReq miss cycles
666system.cpu.icache.ReadReq_miss_latency::total 545585992 # number of ReadReq miss cycles
667system.cpu.icache.demand_miss_latency::cpu.inst 545585992 # number of demand (read+write) miss cycles
668system.cpu.icache.demand_miss_latency::total 545585992 # number of demand (read+write) miss cycles
669system.cpu.icache.overall_miss_latency::cpu.inst 545585992 # number of overall miss cycles
670system.cpu.icache.overall_miss_latency::total 545585992 # number of overall miss cycles
671system.cpu.icache.ReadReq_accesses::cpu.inst 334734641 # number of ReadReq accesses(hits+misses)
672system.cpu.icache.ReadReq_accesses::total 334734641 # number of ReadReq accesses(hits+misses)
673system.cpu.icache.demand_accesses::cpu.inst 334734641 # number of demand (read+write) accesses
674system.cpu.icache.demand_accesses::total 334734641 # number of demand (read+write) accesses
675system.cpu.icache.overall_accesses::cpu.inst 334734641 # number of overall (read+write) accesses
676system.cpu.icache.overall_accesses::total 334734641 # number of overall (read+write) accesses
677system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses
678system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses
679system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses
680system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses
681system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses
682system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses
683system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766 # average ReadReq miss latency
684system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766 # average ReadReq miss latency
685system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency
686system.cpu.icache.demand_avg_miss_latency::total 16992.742766 # average overall miss latency
687system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency
688system.cpu.icache.overall_avg_miss_latency::total 16992.742766 # average overall miss latency
689system.cpu.icache.blocked_cycles::no_mshrs 2092 # number of cycles access was blocked

690system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

691system.cpu.icache.blocked::no_mshrs 31 # number of cycles access was blocked

691system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked

692system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

693system.cpu.icache.avg_blocked_cycles::no_mshrs 56.064516 # average number of cycles each access was blocked

693system.cpu.icache.avg_blocked_cycles::no_mshrs 55.052632 # average number of cycles each access was blocked

694system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
695system.cpu.icache.fast_writes 0 # number of fast writes performed
696system.cpu.icache.cache_copies 0 # number of cache copies performed

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698system.cpu.icache.ReadReq_mshr_hits::total 2520 # number of ReadReq MSHR hits
699system.cpu.icache.demand_mshr_hits::cpu.inst 2520 # number of demand (read+write) MSHR hits
700system.cpu.icache.demand_mshr_hits::total 2520 # number of demand (read+write) MSHR hits
701system.cpu.icache.overall_mshr_hits::cpu.inst 2520 # number of overall MSHR hits
702system.cpu.icache.overall_mshr_hits::total 2520 # number of overall MSHR hits
703system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28384 # number of ReadReq MSHR misses
704system.cpu.icache.ReadReq_mshr_misses::total 28384 # number of ReadReq MSHR misses
705system.cpu.icache.demand_mshr_misses::cpu.inst 28384 # number of demand (read+write) MSHR misses
706system.cpu.icache.demand_mshr_misses::total 28384 # number of demand (read+write) MSHR misses
707system.cpu.icache.overall_mshr_misses::cpu.inst 28384 # number of overall MSHR misses
708system.cpu.icache.overall_mshr_misses::total 28384 # number of overall MSHR misses
709system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 424232750 # number of ReadReq MSHR miss cycles
710system.cpu.icache.ReadReq_mshr_miss_latency::total 424232750 # number of ReadReq MSHR miss cycles
711system.cpu.icache.demand_mshr_miss_latency::cpu.inst 424232750 # number of demand (read+write) MSHR miss cycles
712system.cpu.icache.demand_mshr_miss_latency::total 424232750 # number of demand (read+write) MSHR miss cycles
713system.cpu.icache.overall_mshr_miss_latency::cpu.inst 424232750 # number of overall MSHR miss cycles
714system.cpu.icache.overall_mshr_miss_latency::total 424232750 # number of overall MSHR miss cycles
715system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for ReadReq accesses
716system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000083 # mshr miss rate for ReadReq accesses
717system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for demand accesses
718system.cpu.icache.demand_mshr_miss_rate::total 0.000083 # mshr miss rate for demand accesses
719system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for overall accesses
720system.cpu.icache.overall_mshr_miss_rate::total 0.000083 # mshr miss rate for overall accesses
721system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14946.193278 # average ReadReq mshr miss latency
722system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14946.193278 # average ReadReq mshr miss latency
723system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency
724system.cpu.icache.demand_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency
725system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency
726system.cpu.icache.overall_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency

697system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2825 # number of ReadReq MSHR hits
698system.cpu.icache.ReadReq_mshr_hits::total 2825 # number of ReadReq MSHR hits
699system.cpu.icache.demand_mshr_hits::cpu.inst 2825 # number of demand (read+write) MSHR hits
700system.cpu.icache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits
701system.cpu.icache.overall_mshr_hits::cpu.inst 2825 # number of overall MSHR hits
702system.cpu.icache.overall_mshr_hits::total 2825 # number of overall MSHR hits
703system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29282 # number of ReadReq MSHR misses
704system.cpu.icache.ReadReq_mshr_misses::total 29282 # number of ReadReq MSHR misses
705system.cpu.icache.demand_mshr_misses::cpu.inst 29282 # number of demand (read+write) MSHR misses
706system.cpu.icache.demand_mshr_misses::total 29282 # number of demand (read+write) MSHR misses
707system.cpu.icache.overall_mshr_misses::cpu.inst 29282 # number of overall MSHR misses
708system.cpu.icache.overall_mshr_misses::total 29282 # number of overall MSHR misses
709system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435718750 # number of ReadReq MSHR miss cycles
710system.cpu.icache.ReadReq_mshr_miss_latency::total 435718750 # number of ReadReq MSHR miss cycles
711system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435718750 # number of demand (read+write) MSHR miss cycles
712system.cpu.icache.demand_mshr_miss_latency::total 435718750 # number of demand (read+write) MSHR miss cycles
713system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435718750 # number of overall MSHR miss cycles
714system.cpu.icache.overall_mshr_miss_latency::total 435718750 # number of overall MSHR miss cycles
715system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
716system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
717system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
718system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
719system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
720system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
721system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14880.088450 # average ReadReq mshr miss latency
722system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14880.088450 # average ReadReq mshr miss latency
723system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency
724system.cpu.icache.demand_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency
725system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency
726system.cpu.icache.overall_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency

727system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

728system.cpu.l2cache.tags.replacements 442189 # number of replacements
729system.cpu.l2cache.tags.tagsinuse 32678.484609 # Cycle average of tags in use
730system.cpu.l2cache.tags.total_refs 1109448 # Total number of references to valid blocks.
731system.cpu.l2cache.tags.sampled_refs 474936 # Sample count of references to valid blocks.
732system.cpu.l2cache.tags.avg_refs 2.335995 # Average number of references to valid blocks.

728system.cpu.l2cache.tags.replacements 442179 # number of replacements
729system.cpu.l2cache.tags.tagsinuse 32678.084712 # Cycle average of tags in use
730system.cpu.l2cache.tags.total_refs 1110777 # Total number of references to valid blocks.
731system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks.
732system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks.

733system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

734system.cpu.l2cache.tags.occ_blocks::writebacks 1308.214481 # Average occupied blocks per requestor
735system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.900676 # Average occupied blocks per requestor
736system.cpu.l2cache.tags.occ_blocks::cpu.data 31321.369452 # Average occupied blocks per requestor
737system.cpu.l2cache.tags.occ_percent::writebacks 0.039924 # Average percentage of cache occupancy
738system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001492 # Average percentage of cache occupancy
739system.cpu.l2cache.tags.occ_percent::cpu.data 0.955852 # Average percentage of cache occupancy
740system.cpu.l2cache.tags.occ_percent::total 0.997268 # Average percentage of cache occupancy
741system.cpu.l2cache.ReadReq_hits::cpu.inst 21631 # number of ReadReq hits
742system.cpu.l2cache.ReadReq_hits::cpu.data 1057987 # number of ReadReq hits
743system.cpu.l2cache.ReadReq_hits::total 1079618 # number of ReadReq hits
744system.cpu.l2cache.Writeback_hits::writebacks 96315 # number of Writeback hits
745system.cpu.l2cache.Writeback_hits::total 96315 # number of Writeback hits
746system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
747system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
748system.cpu.l2cache.ReadExReq_hits::cpu.data 6443 # number of ReadExReq hits
749system.cpu.l2cache.ReadExReq_hits::total 6443 # number of ReadExReq hits
750system.cpu.l2cache.demand_hits::cpu.inst 21631 # number of demand (read+write) hits
751system.cpu.l2cache.demand_hits::cpu.data 1064430 # number of demand (read+write) hits
752system.cpu.l2cache.demand_hits::total 1086061 # number of demand (read+write) hits
753system.cpu.l2cache.overall_hits::cpu.inst 21631 # number of overall hits
754system.cpu.l2cache.overall_hits::cpu.data 1064430 # number of overall hits
755system.cpu.l2cache.overall_hits::total 1086061 # number of overall hits

734system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor
735system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor
736system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor
737system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy
738system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001578 # Average percentage of cache occupancy
739system.cpu.l2cache.tags.occ_percent::cpu.data 0.955470 # Average percentage of cache occupancy
740system.cpu.l2cache.tags.occ_percent::total 0.997256 # Average percentage of cache occupancy
741system.cpu.l2cache.ReadReq_hits::cpu.inst 22592 # number of ReadReq hits
742system.cpu.l2cache.ReadReq_hits::cpu.data 1058063 # number of ReadReq hits
743system.cpu.l2cache.ReadReq_hits::total 1080655 # number of ReadReq hits
744system.cpu.l2cache.Writeback_hits::writebacks 96313 # number of Writeback hits
745system.cpu.l2cache.Writeback_hits::total 96313 # number of Writeback hits
746system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
747system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
748system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits
749system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits
750system.cpu.l2cache.demand_hits::cpu.inst 22592 # number of demand (read+write) hits
751system.cpu.l2cache.demand_hits::cpu.data 1064504 # number of demand (read+write) hits
752system.cpu.l2cache.demand_hits::total 1087096 # number of demand (read+write) hits
753system.cpu.l2cache.overall_hits::cpu.inst 22592 # number of overall hits
754system.cpu.l2cache.overall_hits::cpu.data 1064504 # number of overall hits
755system.cpu.l2cache.overall_hits::total 1087096 # number of overall hits

756system.cpu.l2cache.ReadReq_misses::cpu.inst 2426 # number of ReadReq misses

757system.cpu.l2cache.ReadReq_misses::cpu.data 406497 # number of ReadReq misses
758system.cpu.l2cache.ReadReq_misses::total 408923 # number of ReadReq misses
759system.cpu.l2cache.UpgradeReq_misses::cpu.data 4324 # number of UpgradeReq misses
760system.cpu.l2cache.UpgradeReq_misses::total 4324 # number of UpgradeReq misses
761system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
762system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses

757system.cpu.l2cache.ReadReq_misses::cpu.data 406486 # number of ReadReq misses
758system.cpu.l2cache.ReadReq_misses::total 408912 # number of ReadReq misses
759system.cpu.l2cache.UpgradeReq_misses::cpu.data 4262 # number of UpgradeReq misses
760system.cpu.l2cache.UpgradeReq_misses::total 4262 # number of UpgradeReq misses
761system.cpu.l2cache.ReadExReq_misses::cpu.data 66077 # number of ReadExReq misses
762system.cpu.l2cache.ReadExReq_misses::total 66077 # number of ReadExReq misses

763system.cpu.l2cache.demand_misses::cpu.inst 2426 # number of demand (read+write) misses

764system.cpu.l2cache.demand_misses::cpu.data 472572 # number of demand (read+write) misses
765system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses

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765system.cpu.l2cache.demand_misses::total 474989 # number of demand (read+write) misses

766system.cpu.l2cache.overall_misses::cpu.inst 2426 # number of overall misses

767system.cpu.l2cache.overall_misses::cpu.data 472572 # number of overall misses
768system.cpu.l2cache.overall_misses::total 474998 # number of overall misses
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770system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30663807500 # number of ReadReq miss cycles
771system.cpu.l2cache.ReadReq_miss_latency::total 30838984250 # number of ReadReq miss cycles
772system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756616500 # number of ReadExReq miss cycles
773system.cpu.l2cache.ReadExReq_miss_latency::total 4756616500 # number of ReadExReq miss cycles
774system.cpu.l2cache.demand_miss_latency::cpu.inst 175176750 # number of demand (read+write) miss cycles
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777system.cpu.l2cache.overall_miss_latency::cpu.inst 175176750 # number of overall miss cycles
778system.cpu.l2cache.overall_miss_latency::cpu.data 35420424000 # number of overall miss cycles
779system.cpu.l2cache.overall_miss_latency::total 35595600750 # number of overall miss cycles
780system.cpu.l2cache.ReadReq_accesses::cpu.inst 24057 # number of ReadReq accesses(hits+misses)
781system.cpu.l2cache.ReadReq_accesses::cpu.data 1464484 # number of ReadReq accesses(hits+misses)
782system.cpu.l2cache.ReadReq_accesses::total 1488541 # number of ReadReq accesses(hits+misses)
783system.cpu.l2cache.Writeback_accesses::writebacks 96315 # number of Writeback accesses(hits+misses)
784system.cpu.l2cache.Writeback_accesses::total 96315 # number of Writeback accesses(hits+misses)
785system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4328 # number of UpgradeReq accesses(hits+misses)
786system.cpu.l2cache.UpgradeReq_accesses::total 4328 # number of UpgradeReq accesses(hits+misses)

767system.cpu.l2cache.overall_misses::cpu.data 472563 # number of overall misses
768system.cpu.l2cache.overall_misses::total 474989 # number of overall misses
769system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176218750 # number of ReadReq miss cycles
770system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746587000 # number of ReadReq miss cycles
771system.cpu.l2cache.ReadReq_miss_latency::total 30922805750 # number of ReadReq miss cycles
772system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4757394750 # number of ReadExReq miss cycles
773system.cpu.l2cache.ReadExReq_miss_latency::total 4757394750 # number of ReadExReq miss cycles
774system.cpu.l2cache.demand_miss_latency::cpu.inst 176218750 # number of demand (read+write) miss cycles
775system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles
776system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles
777system.cpu.l2cache.overall_miss_latency::cpu.inst 176218750 # number of overall miss cycles
778system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles
779system.cpu.l2cache.overall_miss_latency::total 35680200500 # number of overall miss cycles
780system.cpu.l2cache.ReadReq_accesses::cpu.inst 25018 # number of ReadReq accesses(hits+misses)
781system.cpu.l2cache.ReadReq_accesses::cpu.data 1464549 # number of ReadReq accesses(hits+misses)
782system.cpu.l2cache.ReadReq_accesses::total 1489567 # number of ReadReq accesses(hits+misses)
783system.cpu.l2cache.Writeback_accesses::writebacks 96313 # number of Writeback accesses(hits+misses)
784system.cpu.l2cache.Writeback_accesses::total 96313 # number of Writeback accesses(hits+misses)
785system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4265 # number of UpgradeReq accesses(hits+misses)
786system.cpu.l2cache.UpgradeReq_accesses::total 4265 # number of UpgradeReq accesses(hits+misses)

787system.cpu.l2cache.ReadExReq_accesses::cpu.data 72518 # number of ReadExReq accesses(hits+misses)
788system.cpu.l2cache.ReadExReq_accesses::total 72518 # number of ReadExReq accesses(hits+misses)

789system.cpu.l2cache.demand_accesses::cpu.inst 24057 # number of demand (read+write) accesses
790system.cpu.l2cache.demand_accesses::cpu.data 1537002 # number of demand (read+write) accesses
791system.cpu.l2cache.demand_accesses::total 1561059 # number of demand (read+write) accesses
792system.cpu.l2cache.overall_accesses::cpu.inst 24057 # number of overall (read+write) accesses
793system.cpu.l2cache.overall_accesses::cpu.data 1537002 # number of overall (read+write) accesses
794system.cpu.l2cache.overall_accesses::total 1561059 # number of overall (read+write) accesses
795system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100844 # miss rate for ReadReq accesses
796system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277570 # miss rate for ReadReq accesses
797system.cpu.l2cache.ReadReq_miss_rate::total 0.274714 # miss rate for ReadReq accesses
798system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999076 # miss rate for UpgradeReq accesses
799system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999076 # miss rate for UpgradeReq accesses
800system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911153 # miss rate for ReadExReq accesses
801system.cpu.l2cache.ReadExReq_miss_rate::total 0.911153 # miss rate for ReadExReq accesses
802system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100844 # miss rate for demand accesses
803system.cpu.l2cache.demand_miss_rate::cpu.data 0.307463 # miss rate for demand accesses
804system.cpu.l2cache.demand_miss_rate::total 0.304279 # miss rate for demand accesses
805system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100844 # miss rate for overall accesses
806system.cpu.l2cache.overall_miss_rate::cpu.data 0.307463 # miss rate for overall accesses
807system.cpu.l2cache.overall_miss_rate::total 0.304279 # miss rate for overall accesses
808system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72208.058533 # average ReadReq miss latency
809system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75434.277498 # average ReadReq miss latency
810system.cpu.l2cache.ReadReq_avg_miss_latency::total 75415.137446 # average ReadReq miss latency
811system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71988.142263 # average ReadExReq miss latency
812system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71988.142263 # average ReadExReq miss latency
813system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency
814system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency
815system.cpu.l2cache.demand_avg_miss_latency::total 74938.422372 # average overall miss latency
816system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency
817system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency
818system.cpu.l2cache.overall_avg_miss_latency::total 74938.422372 # average overall miss latency

789system.cpu.l2cache.demand_accesses::cpu.inst 25018 # number of demand (read+write) accesses
790system.cpu.l2cache.demand_accesses::cpu.data 1537067 # number of demand (read+write) accesses
791system.cpu.l2cache.demand_accesses::total 1562085 # number of demand (read+write) accesses
792system.cpu.l2cache.overall_accesses::cpu.inst 25018 # number of overall (read+write) accesses
793system.cpu.l2cache.overall_accesses::cpu.data 1537067 # number of overall (read+write) accesses
794system.cpu.l2cache.overall_accesses::total 1562085 # number of overall (read+write) accesses
795system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.096970 # miss rate for ReadReq accesses
796system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277550 # miss rate for ReadReq accesses
797system.cpu.l2cache.ReadReq_miss_rate::total 0.274517 # miss rate for ReadReq accesses
798system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999297 # miss rate for UpgradeReq accesses
799system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999297 # miss rate for UpgradeReq accesses
800system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911181 # miss rate for ReadExReq accesses
801system.cpu.l2cache.ReadExReq_miss_rate::total 0.911181 # miss rate for ReadExReq accesses
802system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096970 # miss rate for demand accesses
803system.cpu.l2cache.demand_miss_rate::cpu.data 0.307445 # miss rate for demand accesses
804system.cpu.l2cache.demand_miss_rate::total 0.304074 # miss rate for demand accesses
805system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096970 # miss rate for overall accesses
806system.cpu.l2cache.overall_miss_rate::cpu.data 0.307445 # miss rate for overall accesses
807system.cpu.l2cache.overall_miss_rate::total 0.304074 # miss rate for overall accesses
808system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135 # average ReadReq miss latency
809system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency
810system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency
811system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272 # average ReadExReq miss latency
812system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272 # average ReadExReq miss latency
813system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency
814system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
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816system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency
817system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
818system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency

819system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
820system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
821system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
822system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
823system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
824system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
825system.cpu.l2cache.fast_writes 0 # number of fast writes performed
826system.cpu.l2cache.cache_copies 0 # number of cache copies performed
827system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
828system.cpu.l2cache.writebacks::total 66098 # number of writebacks
829system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits

830system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits
831system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits

830system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
831system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits

832system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits

833system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits
834system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits

833system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
834system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits

835system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits

836system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits
837system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits

836system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
837system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits

838system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2424 # number of ReadReq MSHR misses

839system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406471 # number of ReadReq MSHR misses
840system.cpu.l2cache.ReadReq_mshr_misses::total 408895 # number of ReadReq MSHR misses
841system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4324 # number of UpgradeReq MSHR misses
842system.cpu.l2cache.UpgradeReq_mshr_misses::total 4324 # number of UpgradeReq MSHR misses
843system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
844system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses

839system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406462 # number of ReadReq MSHR misses
840system.cpu.l2cache.ReadReq_mshr_misses::total 408886 # number of ReadReq MSHR misses
841system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4262 # number of UpgradeReq MSHR misses
842system.cpu.l2cache.UpgradeReq_mshr_misses::total 4262 # number of UpgradeReq MSHR misses
843system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66077 # number of ReadExReq MSHR misses
844system.cpu.l2cache.ReadExReq_mshr_misses::total 66077 # number of ReadExReq MSHR misses

845system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses

846system.cpu.l2cache.demand_mshr_misses::cpu.data 472546 # number of demand (read+write) MSHR misses
847system.cpu.l2cache.demand_mshr_misses::total 474970 # number of demand (read+write) MSHR misses

846system.cpu.l2cache.demand_mshr_misses::cpu.data 472539 # number of demand (read+write) MSHR misses
847system.cpu.l2cache.demand_mshr_misses::total 474963 # number of demand (read+write) MSHR misses

848system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses

849system.cpu.l2cache.overall_mshr_misses::cpu.data 472546 # number of overall MSHR misses
850system.cpu.l2cache.overall_mshr_misses::total 474970 # number of overall MSHR misses
851system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 144597750 # number of ReadReq MSHR miss cycles
852system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25603608250 # number of ReadReq MSHR miss cycles
853system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25748206000 # number of ReadReq MSHR miss cycles
854system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43244324 # number of UpgradeReq MSHR miss cycles
855system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43244324 # number of UpgradeReq MSHR miss cycles
856system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924227000 # number of ReadExReq MSHR miss cycles
857system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924227000 # number of ReadExReq MSHR miss cycles
858system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 144597750 # number of demand (read+write) MSHR miss cycles
859system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29527835250 # number of demand (read+write) MSHR miss cycles
860system.cpu.l2cache.demand_mshr_miss_latency::total 29672433000 # number of demand (read+write) MSHR miss cycles
861system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 144597750 # number of overall MSHR miss cycles
862system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29527835250 # number of overall MSHR miss cycles
863system.cpu.l2cache.overall_mshr_miss_latency::total 29672433000 # number of overall MSHR miss cycles
864system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for ReadReq accesses
865system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277552 # mshr miss rate for ReadReq accesses
866system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274695 # mshr miss rate for ReadReq accesses
867system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999076 # mshr miss rate for UpgradeReq accesses
868system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999076 # mshr miss rate for UpgradeReq accesses
869system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911153 # mshr miss rate for ReadExReq accesses
870system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911153 # mshr miss rate for ReadExReq accesses
871system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for demand accesses
872system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for demand accesses
873system.cpu.l2cache.demand_mshr_miss_rate::total 0.304261 # mshr miss rate for demand accesses
874system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for overall accesses
875system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for overall accesses
876system.cpu.l2cache.overall_mshr_miss_rate::total 0.304261 # mshr miss rate for overall accesses
877system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59652.537129 # average ReadReq mshr miss latency
878system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62989.999902 # average ReadReq mshr miss latency
879system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62970.214847 # average ReadReq mshr miss latency

849system.cpu.l2cache.overall_mshr_misses::cpu.data 472539 # number of overall MSHR misses
850system.cpu.l2cache.overall_mshr_misses::total 474963 # number of overall MSHR misses
851system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles
852system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles
853system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles
854system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles
855system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles
856system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles
857system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles
858system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles
859system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles
860system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles
861system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles
862system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles
863system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles
864system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses
865system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses
866system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses
867system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999297 # mshr miss rate for UpgradeReq accesses
868system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999297 # mshr miss rate for UpgradeReq accesses
869system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911181 # mshr miss rate for ReadExReq accesses
870system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911181 # mshr miss rate for ReadExReq accesses
871system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for demand accesses
872system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for demand accesses
873system.cpu.l2cache.demand_mshr_miss_rate::total 0.304057 # mshr miss rate for demand accesses
874system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for overall accesses
875system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for overall accesses
876system.cpu.l2cache.overall_mshr_miss_rate::total 0.304057 # mshr miss rate for overall accesses
877system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033 # average ReadReq mshr miss latency
878system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency
879system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency

880system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
881system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency

882system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.495649 # average ReadExReq mshr miss latency
883system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.495649 # average ReadExReq mshr miss latency
884system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency
885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency
886system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency
887system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency
888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency
889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency

882system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency
883system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency
884system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency
885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
886system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency
887system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency
888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency

890system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

891system.cpu.dcache.tags.replacements 1532905 # number of replacements
892system.cpu.dcache.tags.tagsinuse 4094.387385 # Cycle average of tags in use
893system.cpu.dcache.tags.total_refs 971436889 # Total number of references to valid blocks.
894system.cpu.dcache.tags.sampled_refs 1537001 # Sample count of references to valid blocks.
895system.cpu.dcache.tags.avg_refs 632.033999 # Average number of references to valid blocks.
896system.cpu.dcache.tags.warmup_cycle 400661250 # Cycle when the warmup percentage was hit.
897system.cpu.dcache.tags.occ_blocks::cpu.data 4094.387385 # Average occupied blocks per requestor
898system.cpu.dcache.tags.occ_percent::cpu.data 0.999606 # Average percentage of cache occupancy
899system.cpu.dcache.tags.occ_percent::total 0.999606 # Average percentage of cache occupancy
900system.cpu.dcache.ReadReq_hits::cpu.data 695310256 # number of ReadReq hits
901system.cpu.dcache.ReadReq_hits::total 695310256 # number of ReadReq hits
902system.cpu.dcache.WriteReq_hits::cpu.data 276092959 # number of WriteReq hits
903system.cpu.dcache.WriteReq_hits::total 276092959 # number of WriteReq hits
904system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits
905system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits

891system.cpu.dcache.tags.replacements 1532970 # number of replacements
892system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use
893system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks.
894system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks.
895system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks.
896system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit.
897system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor
898system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy
899system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy
900system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits
901system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits
902system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits
903system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits
904system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits
905system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits

906system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
907system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits

908system.cpu.dcache.demand_hits::cpu.data 971403215 # number of demand (read+write) hits
909system.cpu.dcache.demand_hits::total 971403215 # number of demand (read+write) hits
910system.cpu.dcache.overall_hits::cpu.data 971403215 # number of overall hits
911system.cpu.dcache.overall_hits::total 971403215 # number of overall hits
912system.cpu.dcache.ReadReq_misses::cpu.data 1954136 # number of ReadReq misses
913system.cpu.dcache.ReadReq_misses::total 1954136 # number of ReadReq misses
914system.cpu.dcache.WriteReq_misses::cpu.data 842719 # number of WriteReq misses
915system.cpu.dcache.WriteReq_misses::total 842719 # number of WriteReq misses

908system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits
909system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits
910system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits
911system.cpu.dcache.overall_hits::total 971375738 # number of overall hits
912system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses
913system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses
914system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses
915system.cpu.dcache.WriteReq_misses::total 842629 # number of WriteReq misses

916system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
917system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses

918system.cpu.dcache.demand_misses::cpu.data 2796855 # number of demand (read+write) misses
919system.cpu.dcache.demand_misses::total 2796855 # number of demand (read+write) misses
920system.cpu.dcache.overall_misses::cpu.data 2796855 # number of overall misses
921system.cpu.dcache.overall_misses::total 2796855 # number of overall misses
922system.cpu.dcache.ReadReq_miss_latency::cpu.data 80332980069 # number of ReadReq miss cycles
923system.cpu.dcache.ReadReq_miss_latency::total 80332980069 # number of ReadReq miss cycles
924system.cpu.dcache.WriteReq_miss_latency::cpu.data 58617620770 # number of WriteReq miss cycles
925system.cpu.dcache.WriteReq_miss_latency::total 58617620770 # number of WriteReq miss cycles
926system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225000 # number of LoadLockedReq miss cycles
927system.cpu.dcache.LoadLockedReq_miss_latency::total 225000 # number of LoadLockedReq miss cycles
928system.cpu.dcache.demand_miss_latency::cpu.data 138950600839 # number of demand (read+write) miss cycles
929system.cpu.dcache.demand_miss_latency::total 138950600839 # number of demand (read+write) miss cycles
930system.cpu.dcache.overall_miss_latency::cpu.data 138950600839 # number of overall miss cycles
931system.cpu.dcache.overall_miss_latency::total 138950600839 # number of overall miss cycles
932system.cpu.dcache.ReadReq_accesses::cpu.data 697264392 # number of ReadReq accesses(hits+misses)
933system.cpu.dcache.ReadReq_accesses::total 697264392 # number of ReadReq accesses(hits+misses)

918system.cpu.dcache.demand_misses::cpu.data 2796744 # number of demand (read+write) misses
919system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses
920system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses
921system.cpu.dcache.overall_misses::total 2796744 # number of overall misses
922system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles
923system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles
924system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles
925system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles
926system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles
927system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles
928system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles
929system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles
930system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles
931system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles
932system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses)
933system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses)

934system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
935system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)

936system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses)
937system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses)

936system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses)
937system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses)

938system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
939system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)

940system.cpu.dcache.demand_accesses::cpu.data 974200070 # number of demand (read+write) accesses
941system.cpu.dcache.demand_accesses::total 974200070 # number of demand (read+write) accesses
942system.cpu.dcache.overall_accesses::cpu.data 974200070 # number of overall (read+write) accesses
943system.cpu.dcache.overall_accesses::total 974200070 # number of overall (read+write) accesses

940system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses
941system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses
942system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses
943system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses

944system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses
945system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses
946system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses
947system.cpu.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses
948system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
949system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
950system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 # miss rate for demand accesses
951system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses
952system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses
953system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses

954system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41109.206355 # average ReadReq miss latency
955system.cpu.dcache.ReadReq_avg_miss_latency::total 41109.206355 # average ReadReq miss latency
956system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69557.730121 # average WriteReq miss latency
957system.cpu.dcache.WriteReq_avg_miss_latency::total 69557.730121 # average WriteReq miss latency
958system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75000 # average LoadLockedReq miss latency
959system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75000 # average LoadLockedReq miss latency
960system.cpu.dcache.demand_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency
961system.cpu.dcache.demand_avg_miss_latency::total 49681.017013 # average overall miss latency
962system.cpu.dcache.overall_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency
963system.cpu.dcache.overall_avg_miss_latency::total 49681.017013 # average overall miss latency
964system.cpu.dcache.blocked_cycles::no_mshrs 2430 # number of cycles access was blocked
965system.cpu.dcache.blocked_cycles::no_targets 892 # number of cycles access was blocked
966system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked
967system.cpu.dcache.blocked::no_targets 86 # number of cycles access was blocked
968system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.392857 # average number of cycles each access was blocked
969system.cpu.dcache.avg_blocked_cycles::no_targets 10.372093 # average number of cycles each access was blocked

954system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency
955system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency
956system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency
957system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency
958system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency
959system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency
960system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
961system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency
962system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
963system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency
964system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked
965system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked
966system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked
967system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
968system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.557692 # average number of cycles each access was blocked
969system.cpu.dcache.avg_blocked_cycles::no_targets 10.550562 # average number of cycles each access was blocked

970system.cpu.dcache.fast_writes 0 # number of fast writes performed
971system.cpu.dcache.cache_copies 0 # number of cache copies performed

972system.cpu.dcache.writebacks::writebacks 96315 # number of writebacks
973system.cpu.dcache.writebacks::total 96315 # number of writebacks
974system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489650 # number of ReadReq MSHR hits
975system.cpu.dcache.ReadReq_mshr_hits::total 489650 # number of ReadReq MSHR hits
976system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765875 # number of WriteReq MSHR hits
977system.cpu.dcache.WriteReq_mshr_hits::total 765875 # number of WriteReq MSHR hits

972system.cpu.dcache.writebacks::writebacks 96313 # number of writebacks
973system.cpu.dcache.writebacks::total 96313 # number of writebacks
974system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489564 # number of ReadReq MSHR hits
975system.cpu.dcache.ReadReq_mshr_hits::total 489564 # number of ReadReq MSHR hits
976system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765848 # number of WriteReq MSHR hits
977system.cpu.dcache.WriteReq_mshr_hits::total 765848 # number of WriteReq MSHR hits

978system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
979system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits

980system.cpu.dcache.demand_mshr_hits::cpu.data 1255525 # number of demand (read+write) MSHR hits
981system.cpu.dcache.demand_mshr_hits::total 1255525 # number of demand (read+write) MSHR hits
982system.cpu.dcache.overall_mshr_hits::cpu.data 1255525 # number of overall MSHR hits
983system.cpu.dcache.overall_mshr_hits::total 1255525 # number of overall MSHR hits
984system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464486 # number of ReadReq MSHR misses
985system.cpu.dcache.ReadReq_mshr_misses::total 1464486 # number of ReadReq MSHR misses
986system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76844 # number of WriteReq MSHR misses
987system.cpu.dcache.WriteReq_mshr_misses::total 76844 # number of WriteReq MSHR misses
988system.cpu.dcache.demand_mshr_misses::cpu.data 1541330 # number of demand (read+write) MSHR misses
989system.cpu.dcache.demand_mshr_misses::total 1541330 # number of demand (read+write) MSHR misses
990system.cpu.dcache.overall_mshr_misses::cpu.data 1541330 # number of overall MSHR misses
991system.cpu.dcache.overall_mshr_misses::total 1541330 # number of overall MSHR misses
992system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42708562776 # number of ReadReq MSHR miss cycles
993system.cpu.dcache.ReadReq_mshr_miss_latency::total 42708562776 # number of ReadReq MSHR miss cycles
994system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4994223926 # number of WriteReq MSHR miss cycles
995system.cpu.dcache.WriteReq_mshr_miss_latency::total 4994223926 # number of WriteReq MSHR miss cycles
996system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47702786702 # number of demand (read+write) MSHR miss cycles
997system.cpu.dcache.demand_mshr_miss_latency::total 47702786702 # number of demand (read+write) MSHR miss cycles
998system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47702786702 # number of overall MSHR miss cycles
999system.cpu.dcache.overall_mshr_miss_latency::total 47702786702 # number of overall MSHR miss cycles
1000system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002100 # mshr miss rate for ReadReq accesses
1001system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002100 # mshr miss rate for ReadReq accesses

980system.cpu.dcache.demand_mshr_hits::cpu.data 1255412 # number of demand (read+write) MSHR hits
981system.cpu.dcache.demand_mshr_hits::total 1255412 # number of demand (read+write) MSHR hits
982system.cpu.dcache.overall_mshr_hits::cpu.data 1255412 # number of overall MSHR hits
983system.cpu.dcache.overall_mshr_hits::total 1255412 # number of overall MSHR hits
984system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464551 # number of ReadReq MSHR misses
985system.cpu.dcache.ReadReq_mshr_misses::total 1464551 # number of ReadReq MSHR misses
986system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76781 # number of WriteReq MSHR misses
987system.cpu.dcache.WriteReq_mshr_misses::total 76781 # number of WriteReq MSHR misses
988system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 # number of demand (read+write) MSHR misses
989system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses
990system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses
991system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses
992system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles
993system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles
994system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles
995system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles
996system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles
997system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles
998system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles
999system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles
1000system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses
1001system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses

1002system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
1003system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
1004system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses
1005system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses
1006system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses
1007system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses

1008system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29162.834452 # average ReadReq mshr miss latency
1009system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29162.834452 # average ReadReq mshr miss latency
1010system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64991.722529 # average WriteReq mshr miss latency
1011system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64991.722529 # average WriteReq mshr miss latency
1012system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency
1013system.cpu.dcache.demand_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency
1014system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency
1015system.cpu.dcache.overall_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency

1008system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency
1009system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency
1010system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency
1011system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency
1012system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
1013system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
1014system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
1015system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency