stats.txt (9797:9cd5f91e7a79) | stats.txt (9838:43d22d746e7a) |
---|---|
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.640648 # Number of seconds simulated 4sim_ticks 640648369500 # Number of ticks simulated 5final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.640648 # Number of seconds simulated 4sim_ticks 640648369500 # Number of ticks simulated 5final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 99606 # Simulator instruction rate (inst/s) 8host_op_rate 135651 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46095119 # Simulator tick rate (ticks/s) 10host_mem_usage 254320 # Number of bytes of host memory used 11host_seconds 13898.40 # Real time elapsed on the host | 7host_inst_rate 107808 # Simulator instruction rate (inst/s) 8host_op_rate 146820 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49890421 # Simulator tick rate (ticks/s) 10host_mem_usage 251704 # Number of bytes of host memory used 11host_seconds 12841.11 # Real time elapsed on the host |
12sim_insts 1384370590 # Number of instructions simulated 13sim_ops 1885325342 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory --- 9 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 1384370590 # Number of instructions simulated 13sim_ops 1885325342 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory --- 9 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s) |
37system.physmem.readReqs 474992 # Total number of read requests seen 38system.physmem.writeReqs 66098 # Total number of write requests seen 39system.physmem.cpureqs 545451 # Reqs generatd by CPU via cache - shady | 37system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller 38system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller 39system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 40system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts |
40system.physmem.bytesRead 30399488 # Total number of bytes read from memory 41system.physmem.bytesWritten 4230272 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() | 41system.physmem.bytesRead 30399488 # Total number of bytes read from memory 42system.physmem.bytesWritten 4230272 # Total number of bytes written to memory 43system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize() 44system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() |
44system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q | 45system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q |
45system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis --- 186 unchanged lines hidden (view full) --- 239system.membus.throughput 54054139 # Throughput (bytes/s) 240system.membus.trans_dist::ReadReq 408917 # Transaction distribution 241system.membus.trans_dist::ReadResp 408916 # Transaction distribution 242system.membus.trans_dist::Writeback 66098 # Transaction distribution 243system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution 244system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution 245system.membus.trans_dist::ReadExReq 66075 # Transaction distribution 246system.membus.trans_dist::ReadExResp 66075 # Transaction distribution | 46system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed 47system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis --- 186 unchanged lines hidden (view full) --- 240system.membus.throughput 54054139 # Throughput (bytes/s) 241system.membus.trans_dist::ReadReq 408917 # Transaction distribution 242system.membus.trans_dist::ReadResp 408916 # Transaction distribution 243system.membus.trans_dist::Writeback 66098 # Transaction distribution 244system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution 245system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution 246system.membus.trans_dist::ReadExReq 66075 # Transaction distribution 247system.membus.trans_dist::ReadExResp 66075 # Transaction distribution |
247system.membus.pkt_count_system.cpu.l2cache.mem_side 1024803 # Packet count per connected master and slave (bytes) 248system.membus.pkt_count 1024803 # Packet count per connected master and slave (bytes) 249system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34629696 # Cumulative packet size per connected master and slave (bytes) 250system.membus.tot_pkt_size 34629696 # Cumulative packet size per connected master and slave (bytes) | 248system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes) 249system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes) 250system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes) 251system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes) |
251system.membus.data_through_bus 34629696 # Total data (bytes) 252system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 253system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks) 254system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 255system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks) 256system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 257system.cpu.branchPred.lookups 451070712 # Number of BP lookups 258system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted --- 312 unchanged lines hidden (view full) --- 571system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s) 572system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution 573system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution | 252system.membus.data_through_bus 34629696 # Total data (bytes) 253system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 254system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks) 255system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 256system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks) 257system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 258system.cpu.branchPred.lookups 451070712 # Number of BP lookups 259system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted --- 312 unchanged lines hidden (view full) --- 572system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s) 573system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution |
579system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52387 # Packet count per connected master and slave (bytes) 580system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178835 # Packet count per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_count 3231222 # Packet count per connected master and slave (bytes) 582system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1536768 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104525120 # Cumulative packet size per connected master and slave (bytes) 584system.cpu.toL2Bus.tot_pkt_size 106061888 # Cumulative packet size per connected master and slave (bytes) | 580system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes) 582system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes) 583system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes) 584system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes) 585system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes) |
585system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes) 586system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes) 587system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks) 588system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 589system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks) 590system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 591system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks) 592system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) | 586system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes) 587system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes) 588system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks) 589system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 590system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks) 591system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 592system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks) 593system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) |
593system.cpu.icache.tags.replacements 22329 # number of replacements 594system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use 595system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks. 596system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks. 597system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks. 598system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 599system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor 600system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy 601system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy | 594system.cpu.icache.tags.replacements 22329 # number of replacements 595system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use 596system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks. 597system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks. 598system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks. 599system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 600system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor 601system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy 602system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy |
602system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits 603system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits 604system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits 605system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits 606system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits 607system.cpu.icache.overall_hits::total 345973619 # number of overall hits 608system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses 609system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 669system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031 # average ReadReq mshr miss latency 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031 # average ReadReq mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency 673system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency 675system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency 676system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 603system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits 604system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits 605system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits 606system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits 607system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits 608system.cpu.icache.overall_hits::total 345973619 # number of overall hits 609system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses 610system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 670system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031 # average ReadReq mshr miss latency 672system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031 # average ReadReq mshr miss latency 673system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency 674system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency 675system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency 676system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency 677system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
677system.cpu.l2cache.tags.replacements 442208 # number of replacements 678system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use 679system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks. 680system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks. 681system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks. 682system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 678system.cpu.l2cache.tags.replacements 442208 # number of replacements 679system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use 680system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks. 681system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks. 682system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks. 683system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
683system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor | 684system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor |
684system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor 685system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor | 685system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor 686system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor |
686system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy 687system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy 688system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # Average percentage of cache occupancy | 687system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy 688system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy 689system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # Average percentage of cache occupancy |
689system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy | 690system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy |
690system.cpu.l2cache.ReadReq_hits::cpu.inst 21578 # number of ReadReq hits 691system.cpu.l2cache.ReadReq_hits::cpu.data 1057872 # number of ReadReq hits 692system.cpu.l2cache.ReadReq_hits::total 1079450 # number of ReadReq hits 693system.cpu.l2cache.Writeback_hits::writebacks 96304 # number of Writeback hits 694system.cpu.l2cache.Writeback_hits::total 96304 # number of Writeback hits 695system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 696system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 697system.cpu.l2cache.ReadExReq_hits::cpu.data 6444 # number of ReadExReq hits --- 134 unchanged lines hidden (view full) --- 832system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56913.178207 # average ReadExReq mshr miss latency 833system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency 834system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency 835system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency 836system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency 837system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency 838system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency 839system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 691system.cpu.l2cache.ReadReq_hits::cpu.inst 21578 # number of ReadReq hits 692system.cpu.l2cache.ReadReq_hits::cpu.data 1057872 # number of ReadReq hits 693system.cpu.l2cache.ReadReq_hits::total 1079450 # number of ReadReq hits 694system.cpu.l2cache.Writeback_hits::writebacks 96304 # number of Writeback hits 695system.cpu.l2cache.Writeback_hits::total 96304 # number of Writeback hits 696system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 697system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 698system.cpu.l2cache.ReadExReq_hits::cpu.data 6444 # number of ReadExReq hits --- 134 unchanged lines hidden (view full) --- 833system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56913.178207 # average ReadExReq mshr miss latency 834system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency 835system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency 836system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency 837system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency 838system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency 839system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency 840system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
840system.cpu.dcache.tags.replacements 1532805 # number of replacements 841system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use 842system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks. 843system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks. 844system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks. 845system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit. 846system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor 847system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy 848system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy | 841system.cpu.dcache.tags.replacements 1532805 # number of replacements 842system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use 843system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks. 844system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks. 845system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks. 846system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit. 847system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor 848system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy 849system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy |
849system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits 850system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits 851system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits 852system.cpu.dcache.WriteReq_hits::total 276093216 # number of WriteReq hits 853system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits 854system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits 855system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits 856system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits --- 111 unchanged lines hidden --- | 850system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits 851system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits 852system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits 853system.cpu.dcache.WriteReq_hits::total 276093216 # number of WriteReq hits 854system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits 855system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits 856system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits 857system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits --- 111 unchanged lines hidden --- |