| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.627426 # Number of seconds simulated 4sim_ticks 627426486000 # Number of ticks simulated 5final_tick 627426486000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.629145 # Number of seconds simulated 4sim_ticks 629144850500 # Number of ticks simulated 5final_tick 629144850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 65805 # Simulator instruction rate (inst/s) 8host_op_rate 89618 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29824381 # Simulator tick rate (ticks/s) 10host_mem_usage 297136 # Number of bytes of host memory used 11host_seconds 21037.37 # Real time elapsed on the host | 7host_inst_rate 104232 # Simulator instruction rate (inst/s) 8host_op_rate 141949 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47369420 # Simulator tick rate (ticks/s) 10host_mem_usage 254336 # Number of bytes of host memory used 11host_seconds 13281.67 # Real time elapsed on the host |
| 12sim_insts 1384370590 # Number of instructions simulated 13sim_ops 1885325342 # Number of ops (including micro ops) simulated | 12sim_insts 1384370590 # Number of instructions simulated 13sim_ops 1885325342 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 154240 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 30242112 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30396352 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 154240 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 154240 # Number of instructions bytes read from this memory | 14system.physmem.bytes_read::cpu.inst 155072 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 30241984 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30397056 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 155072 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 155072 # Number of instructions bytes read from this memory |
| 19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 20system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory | 19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 20system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory |
| 21system.physmem.num_reads::cpu.inst 2410 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 472533 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 474943 # Number of read requests responded to by this memory | 21system.physmem.num_reads::cpu.inst 2423 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 472531 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 474954 # Number of read requests responded to by this memory |
| 24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory | 24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory |
| 26system.physmem.bw_read::cpu.inst 245830 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 48200248 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 48446077 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 245830 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 245830 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 6742259 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 6742259 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 6742259 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 245830 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 48200248 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 55188336 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 474944 # Total number of read requests seen | 26system.physmem.bw_read::cpu.inst 246481 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 48068396 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 48314877 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 246481 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 246481 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 6723844 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 6723844 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 6723844 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 246481 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 48068396 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 55038721 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 474954 # Total number of read requests seen |
| 38system.physmem.writeReqs 66098 # Total number of write requests seen | 38system.physmem.writeReqs 66098 # Total number of write requests seen |
| 39system.physmem.cpureqs 545373 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 30396352 # Total number of bytes read from memory | 39system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 30397056 # Total number of bytes read from memory |
| 41system.physmem.bytesWritten 4230272 # Total number of bytes written to memory | 41system.physmem.bytesWritten 4230272 # Total number of bytes written to memory |
| 42system.physmem.bytesConsumedRd 30396352 # bytesRead derated as per pkt->getSize() | 42system.physmem.bytesConsumedRd 30397056 # bytesRead derated as per pkt->getSize() |
| 43system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() | 43system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() |
| 44system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 4331 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 29709 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 29700 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 29689 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 29719 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 29749 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 29652 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 29638 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 29679 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 29629 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 29599 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 29613 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 29623 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 29684 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 29651 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 4159 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 4130 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 4128 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 4130 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 4131 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 4119 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 4145 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 4136 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 4104 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 4108 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 4104 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 4133 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis | 44system.physmem.servicedByWrQ 163 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 4296 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 29676 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 29740 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 29705 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 29805 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 29834 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 29631 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 29439 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 29482 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 29490 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 29536 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 29644 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 29703 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 29807 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 29631 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 29795 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis |
| 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 80system.physmem.totGap 627426443000 # Total gap between requests | 80system.physmem.totGap 629144781500 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 87system.physmem.readPktSize::6 474944 # Categorize read packet sizes | 87system.physmem.readPktSize::6 474954 # Categorize read packet sizes |
| 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes 94system.physmem.writePktSize::6 66098 # Categorize write packet sizes | 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes 94system.physmem.writePktSize::6 66098 # Categorize write packet sizes |
| 95system.physmem.rdQLenPdf::0 405886 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 66680 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see | 95system.physmem.rdQLenPdf::0 407688 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 66635 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 380 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 100system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 159system.physmem.totQLat 3439648250 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 21418222000 # Sum of mem lat for all requests 161system.physmem.totBusLat 2373960000 # Total cycles spent in databus access 162system.physmem.totBankLat 15604613750 # Total cycles spent in bank access 163system.physmem.avgQLat 7244.54 # Average queueing delay per request 164system.physmem.avgBankLat 32866.21 # Average bank access latency per request | 159system.physmem.bytesPerActivate::samples 173211 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::mean 199.837655 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::gmean 132.549683 # Bytes accessed per row activation 162system.physmem.bytesPerActivate::stdev 508.405937 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::64-65 59600 34.41% 34.41% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::128-129 42691 24.65% 59.06% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::192-193 39909 23.04% 82.10% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::256-257 25367 14.65% 96.74% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::320-321 276 0.16% 96.90% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::384-385 104 0.06% 96.96% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::448-449 98 0.06% 97.02% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::512-513 91 0.05% 97.07% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::576-577 88 0.05% 97.12% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::640-641 83 0.05% 97.17% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::704-705 78 0.05% 97.21% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::768-769 81 0.05% 97.26% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::832-833 73 0.04% 97.30% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::896-897 74 0.04% 97.35% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::960-961 79 0.05% 97.39% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1024-1025 80 0.05% 97.44% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1216-1217 80 0.05% 97.57% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1280-1281 73 0.04% 97.61% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.65% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1408-1409 73 0.04% 97.70% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1472-1473 3309 1.91% 99.61% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1536-1537 4 0.00% 99.61% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1600-1601 2 0.00% 99.61% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.62% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2240-2241 2 0.00% 99.62% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2432-2433 3 0.00% 99.62% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2624-2625 1 0.00% 99.62% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2688-2689 2 0.00% 99.62% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2752-2753 1 0.00% 99.62% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.67% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::total 173211 # Bytes accessed per row activation 220system.physmem.totQLat 2060605250 # Total cycles spent in queuing delays 221system.physmem.totMemAccLat 15116660250 # Sum of mem lat for all requests 222system.physmem.totBusLat 2373955000 # Total cycles spent in databus access 223system.physmem.totBankLat 10682100000 # Total cycles spent in bank access 224system.physmem.avgQLat 4340.03 # Average queueing delay per request 225system.physmem.avgBankLat 22498.53 # Average bank access latency per request |
| 165system.physmem.avgBusLat 5000.00 # Average bus latency per request | 226system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 166system.physmem.avgMemAccLat 45110.75 # Average memory access latency 167system.physmem.avgRdBW 48.45 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 48.45 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s | 227system.physmem.avgMemAccLat 31838.56 # Average memory access latency 228system.physmem.avgRdBW 48.31 # Average achieved read bandwidth in MB/s 229system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MB/s 230system.physmem.avgConsumedRdBW 48.31 # Average consumed read bandwidth in MB/s 231system.physmem.avgConsumedWrBW 6.72 # Average consumed write bandwidth in MB/s |
| 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 172system.physmem.busUtil 0.43 # Data bus utilization in percentage | 232system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 233system.physmem.busUtil 0.43 # Data bus utilization in percentage |
| 173system.physmem.avgRdQLen 0.03 # Average read queue length over time 174system.physmem.avgWrQLen 17.42 # Average write queue length over time 175system.physmem.readRowHits 143318 # Number of row buffer hits during reads 176system.physmem.writeRowHits 45505 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes 179system.physmem.avgGap 1159663.10 # Average gap between requests 180system.cpu.branchPred.lookups 441070019 # Number of BP lookups 181system.cpu.branchPred.condPredicted 353935839 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 30635394 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 253577570 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 230740155 # Number of BTB hits | 234system.physmem.avgRdQLen 0.02 # Average read queue length over time 235system.physmem.avgWrQLen 17.41 # Average write queue length over time 236system.physmem.readRowHits 318020 # Number of row buffer hits during reads 237system.physmem.writeRowHits 49639 # Number of row buffer hits during writes 238system.physmem.readRowHitRate 66.98 # Row buffer hit rate for reads 239system.physmem.writeRowHitRate 75.10 # Row buffer hit rate for writes 240system.physmem.avgGap 1162817.59 # Average gap between requests 241system.membus.throughput 55038619 # Throughput (bytes/s) 242system.membus.trans_dist::ReadReq 408879 # Transaction distribution 243system.membus.trans_dist::ReadResp 408878 # Transaction distribution 244system.membus.trans_dist::Writeback 66098 # Transaction distribution 245system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution 246system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution 247system.membus.trans_dist::ReadExReq 66075 # Transaction distribution 248system.membus.trans_dist::ReadExResp 66075 # Transaction distribution 249system.membus.pkt_count_system.cpu.l2cache.mem_side 1024597 # Packet count per connected master and slave (bytes) 250system.membus.pkt_count 1024597 # Packet count per connected master and slave (bytes) 251system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34627264 # Cumulative packet size per connected master and slave (bytes) 252system.membus.tot_pkt_size 34627264 # Cumulative packet size per connected master and slave (bytes) 253system.membus.data_through_bus 34627264 # Total data (bytes) 254system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 255system.membus.reqLayer0.occupancy 1206768500 # Layer occupancy (ticks) 256system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 257system.membus.respLayer1.occupancy 4481136954 # Layer occupancy (ticks) 258system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 259system.cpu.branchPred.lookups 441633744 # Number of BP lookups 260system.cpu.branchPred.condPredicted 353245820 # Number of conditional branches predicted 261system.cpu.branchPred.condIncorrect 30626910 # Number of conditional branches incorrect 262system.cpu.branchPred.BTBLookups 253291175 # Number of BTB lookups 263system.cpu.branchPred.BTBHits 229518524 # Number of BTB hits |
| 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 264system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 186system.cpu.branchPred.BTBHitPct 90.993914 # BTB Hit Percentage 187system.cpu.branchPred.usedRAS 51827244 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 2806499 # Number of incorrect RAS predictions. | 265system.cpu.branchPred.BTBHitPct 90.614497 # BTB Hit Percentage 266system.cpu.branchPred.usedRAS 52707299 # Number of times the RAS was used to get a target. 267system.cpu.branchPred.RASInCorrect 2806413 # Number of incorrect RAS predictions. |
| 189system.cpu.dtb.inst_hits 0 # ITB inst hits 190system.cpu.dtb.inst_misses 0 # ITB inst misses 191system.cpu.dtb.read_hits 0 # DTB read hits 192system.cpu.dtb.read_misses 0 # DTB read misses 193system.cpu.dtb.write_hits 0 # DTB write hits 194system.cpu.dtb.write_misses 0 # DTB write misses 195system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 196system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 224system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 225system.cpu.itb.read_accesses 0 # DTB read accesses 226system.cpu.itb.write_accesses 0 # DTB write accesses 227system.cpu.itb.inst_accesses 0 # ITB inst accesses 228system.cpu.itb.hits 0 # DTB hits 229system.cpu.itb.misses 0 # DTB misses 230system.cpu.itb.accesses 0 # DTB accesses 231system.cpu.workload.num_syscalls 1411 # Number of system calls | 268system.cpu.dtb.inst_hits 0 # ITB inst hits 269system.cpu.dtb.inst_misses 0 # ITB inst misses 270system.cpu.dtb.read_hits 0 # DTB read hits 271system.cpu.dtb.read_misses 0 # DTB read misses 272system.cpu.dtb.write_hits 0 # DTB write hits 273system.cpu.dtb.write_misses 0 # DTB write misses 274system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 275system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 303system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 304system.cpu.itb.read_accesses 0 # DTB read accesses 305system.cpu.itb.write_accesses 0 # DTB write accesses 306system.cpu.itb.inst_accesses 0 # ITB inst accesses 307system.cpu.itb.hits 0 # DTB hits 308system.cpu.itb.misses 0 # DTB misses 309system.cpu.itb.accesses 0 # DTB accesses 310system.cpu.workload.num_syscalls 1411 # Number of system calls |
| 232system.cpu.numCycles 1254852973 # number of cpu cycles simulated | 311system.cpu.numCycles 1258289702 # number of cpu cycles simulated |
| 233system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 234system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 312system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 313system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 235system.cpu.fetch.icacheStallCycles 354891147 # Number of cycles fetch is stalled on an Icache miss 236system.cpu.fetch.Insts 2286425176 # Number of instructions fetch has processed 237system.cpu.fetch.Branches 441070019 # Number of branches that fetch encountered 238system.cpu.fetch.predictedBranches 282567399 # Number of branches that fetch has predicted taken 239system.cpu.fetch.Cycles 601918215 # Number of cycles fetch has run and was not squashing or blocked 240system.cpu.fetch.SquashCycles 156601137 # Number of cycles fetch has spent squashing 241system.cpu.fetch.BlockedCycles 130017521 # Number of cycles fetch has spent blocked 242system.cpu.fetch.MiscStallCycles 563 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 243system.cpu.fetch.PendingTrapStallCycles 11246 # Number of stall cycles due to pending traps 244system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR 245system.cpu.fetch.CacheLines 335797832 # Number of cache lines fetched 246system.cpu.fetch.IcacheSquashes 11972922 # Number of outstanding Icache misses that were squashed 247system.cpu.fetch.rateDist::samples 1212752602 # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::mean 2.588148 # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::stdev 3.180737 # Number of instructions fetched each cycle (Total) | 314system.cpu.fetch.icacheStallCycles 355059035 # Number of cycles fetch is stalled on an Icache miss 315system.cpu.fetch.Insts 2281679265 # Number of instructions fetch has processed 316system.cpu.fetch.Branches 441633744 # Number of branches that fetch encountered 317system.cpu.fetch.predictedBranches 282225823 # Number of branches that fetch has predicted taken 318system.cpu.fetch.Cycles 601500993 # Number of cycles fetch has run and was not squashing or blocked 319system.cpu.fetch.SquashCycles 156584245 # Number of cycles fetch has spent squashing 320system.cpu.fetch.BlockedCycles 133257591 # Number of cycles fetch has spent blocked 321system.cpu.fetch.MiscStallCycles 713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 322system.cpu.fetch.PendingTrapStallCycles 11034 # Number of stall cycles due to pending traps 323system.cpu.fetch.IcacheWaitRetryStallCycles 167 # Number of stall cycles due to full MSHR 324system.cpu.fetch.CacheLines 335655020 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 11657170 # Number of outstanding Icache misses that were squashed 326system.cpu.fetch.rateDist::samples 1215734936 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 2.578441 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 3.176596 # Number of instructions fetched each cycle (Total) |
| 250system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 251system.cpu.fetch.rateDist::0 610879185 50.37% 50.37% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::1 42915841 3.54% 53.91% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::2 96172627 7.93% 61.84% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::3 57091199 4.71% 66.55% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::4 71993232 5.94% 72.48% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::5 43518781 3.59% 76.07% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::6 30912276 2.55% 78.62% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::7 32947513 2.72% 81.34% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::8 226321948 18.66% 100.00% # Number of instructions fetched each cycle (Total) | 330system.cpu.fetch.rateDist::0 614278728 50.53% 50.53% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::1 43031217 3.54% 54.07% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 96058050 7.90% 61.97% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 55653458 4.58% 66.55% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 73683625 6.06% 72.61% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 43835223 3.61% 76.21% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 31015132 2.55% 78.76% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 32844314 2.70% 81.47% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 225335189 18.53% 100.00% # Number of instructions fetched each cycle (Total) |
| 260system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 263system.cpu.fetch.rateDist::total 1212752602 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.branchRate 0.351491 # Number of branch fetches per cycle 265system.cpu.fetch.rate 1.822066 # Number of inst fetches per cycle 266system.cpu.decode.IdleCycles 405845320 # Number of cycles decode is idle 267system.cpu.decode.BlockedCycles 102427093 # Number of cycles decode is blocked 268system.cpu.decode.RunCycles 561818768 # Number of cycles decode is running 269system.cpu.decode.UnblockCycles 16761536 # Number of cycles decode is unblocking 270system.cpu.decode.SquashCycles 125899885 # Number of cycles decode is squashing 271system.cpu.decode.BranchResolved 44789430 # Number of times decode resolved a branch 272system.cpu.decode.BranchMispred 14217 # Number of times decode detected a branch misprediction 273system.cpu.decode.DecodedInsts 3028082478 # Number of instructions handled by decode 274system.cpu.decode.SquashedInsts 30107 # Number of squashed instructions handled by decode 275system.cpu.rename.SquashCycles 125899885 # Number of cycles rename is squashing 276system.cpu.rename.IdleCycles 441818256 # Number of cycles rename is idle 277system.cpu.rename.BlockCycles 34409054 # Number of cycles rename is blocking 278system.cpu.rename.serializeStallCycles 439229 # count of cycles rename stalled for serializing inst 279system.cpu.rename.RunCycles 540562916 # Number of cycles rename is running 280system.cpu.rename.UnblockCycles 69623262 # Number of cycles rename is unblocking 281system.cpu.rename.RenamedInsts 2944183318 # Number of instructions processed by rename 282system.cpu.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full 283system.cpu.rename.IQFullEvents 4821524 # Number of times rename has blocked due to IQ full 284system.cpu.rename.LSQFullEvents 54501316 # Number of times rename has blocked due to LSQ full 285system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers 286system.cpu.rename.RenamedOperands 2929324563 # Number of destination operands rename has renamed 287system.cpu.rename.RenameLookups 14012451828 # Number of register rename lookups that rename has made 288system.cpu.rename.int_rename_lookups 13441344414 # Number of integer rename lookups 289system.cpu.rename.fp_rename_lookups 571107414 # Number of floating rename lookups | 342system.cpu.fetch.rateDist::total 1215734936 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.branchRate 0.350979 # Number of branch fetches per cycle 344system.cpu.fetch.rate 1.813318 # Number of inst fetches per cycle 345system.cpu.decode.IdleCycles 405408112 # Number of cycles decode is idle 346system.cpu.decode.BlockedCycles 105525155 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 562197495 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 16710779 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 125893395 # Number of cycles decode is squashing 350system.cpu.decode.BranchResolved 45735070 # Number of times decode resolved a branch 351system.cpu.decode.BranchMispred 12243 # Number of times decode detected a branch misprediction 352system.cpu.decode.DecodedInsts 3027450313 # Number of instructions handled by decode 353system.cpu.decode.SquashedInsts 24999 # Number of squashed instructions handled by decode 354system.cpu.rename.SquashCycles 125893395 # Number of cycles rename is squashing 355system.cpu.rename.IdleCycles 441381944 # Number of cycles rename is idle 356system.cpu.rename.BlockCycles 37599884 # Number of cycles rename is blocking 357system.cpu.rename.serializeStallCycles 466637 # count of cycles rename stalled for serializing inst 358system.cpu.rename.RunCycles 540742593 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 69650483 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 2947282074 # Number of instructions processed by rename 361system.cpu.rename.ROBFullEvents 91 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 4813438 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LSQFullEvents 54199144 # Number of times rename has blocked due to LSQ full 364system.cpu.rename.RenamedOperands 2931640163 # Number of destination operands rename has renamed 365system.cpu.rename.RenameLookups 14025190740 # Number of register rename lookups that rename has made 366system.cpu.rename.int_rename_lookups 13455020985 # Number of integer rename lookups 367system.cpu.rename.fp_rename_lookups 570169755 # Number of floating rename lookups |
| 290system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed | 368system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed |
| 291system.cpu.rename.UndoneMaps 936184473 # Number of HB maps that are undone due to squashing 292system.cpu.rename.serializingInsts 21713 # count of serializing insts renamed 293system.cpu.rename.tempSerializingInsts 19183 # count of temporary serializing insts renamed 294system.cpu.rename.skidInsts 177423093 # count of insts added to the skid buffer 295system.cpu.memDep0.insertedLoads 969808911 # Number of loads inserted to the mem dependence unit. 296system.cpu.memDep0.insertedStores 487407647 # Number of stores inserted to the mem dependence unit. 297system.cpu.memDep0.conflictingLoads 36223294 # Number of conflicting loads. 298system.cpu.memDep0.conflictingStores 40155637 # Number of conflicting stores. 299system.cpu.iq.iqInstsAdded 2791556624 # Number of instructions added to the IQ (excludes non-spec) 300system.cpu.iq.iqNonSpecInstsAdded 29091 # Number of non-speculative instructions added to the IQ 301system.cpu.iq.iqInstsIssued 2432817301 # Number of instructions issued 302system.cpu.iq.iqSquashedInstsIssued 13264046 # Number of squashed instructions issued 303system.cpu.iq.iqSquashedInstsExamined 893693392 # Number of squashed instructions iterated over during squash; mainly for profiling 304system.cpu.iq.iqSquashedOperandsExamined 2309057295 # Number of squashed operands that are examined and possibly removed from graph 305system.cpu.iq.iqSquashedNonSpecRemoved 7707 # Number of squashed non-spec instructions that were removed 306system.cpu.iq.issued_per_cycle::samples 1212752602 # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::mean 2.006029 # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::stdev 1.872054 # Number of insts issued each cycle | 369system.cpu.rename.UndoneMaps 938500073 # Number of HB maps that are undone due to squashing 370system.cpu.rename.serializingInsts 22029 # count of serializing insts renamed 371system.cpu.rename.tempSerializingInsts 19516 # count of temporary serializing insts renamed 372system.cpu.rename.skidInsts 179002715 # count of insts added to the skid buffer 373system.cpu.memDep0.insertedLoads 971623898 # Number of loads inserted to the mem dependence unit. 374system.cpu.memDep0.insertedStores 487434291 # Number of stores inserted to the mem dependence unit. 375system.cpu.memDep0.conflictingLoads 36825257 # Number of conflicting loads. 376system.cpu.memDep0.conflictingStores 41359268 # Number of conflicting stores. 377system.cpu.iq.iqInstsAdded 2792194659 # Number of instructions added to the IQ (excludes non-spec) 378system.cpu.iq.iqNonSpecInstsAdded 28248 # Number of non-speculative instructions added to the IQ 379system.cpu.iq.iqInstsIssued 2432796766 # Number of instructions issued 380system.cpu.iq.iqSquashedInstsIssued 13281338 # Number of squashed instructions issued 381system.cpu.iq.iqSquashedInstsExamined 894337134 # Number of squashed instructions iterated over during squash; mainly for profiling 382system.cpu.iq.iqSquashedOperandsExamined 2316040320 # Number of squashed operands that are examined and possibly removed from graph 383system.cpu.iq.iqSquashedNonSpecRemoved 6864 # Number of squashed non-spec instructions that were removed 384system.cpu.iq.issued_per_cycle::samples 1215734936 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::mean 2.001091 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle |
| 309system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 387system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 310system.cpu.iq.issued_per_cycle::0 376736827 31.06% 31.06% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::1 183745627 15.15% 46.22% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::2 204018800 16.82% 63.04% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::3 169675350 13.99% 77.03% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::4 132825359 10.95% 87.98% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::5 92323584 7.61% 95.59% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::6 37944626 3.13% 98.72% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::7 12438520 1.03% 99.75% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::8 3043909 0.25% 100.00% # Number of insts issued each cycle | 388system.cpu.iq.issued_per_cycle::0 379743334 31.24% 31.24% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::1 183587297 15.10% 46.34% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::2 204204940 16.80% 63.13% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::3 169567149 13.95% 77.08% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::4 132821991 10.93% 88.01% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::5 92473374 7.61% 95.61% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::6 37933065 3.12% 98.73% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::7 12385370 1.02% 99.75% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::8 3018416 0.25% 100.00% # Number of insts issued each cycle |
| 319system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 397system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 322system.cpu.iq.issued_per_cycle::total 1212752602 # Number of insts issued each cycle | 400system.cpu.iq.issued_per_cycle::total 1215734936 # Number of insts issued each cycle |
| 323system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 401system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 324system.cpu.iq.fu_full::IntAlu 715136 0.82% 0.82% # attempts to use FU when none available 325system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available 326system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available 327system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available 328system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available 329system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available 332system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available 353system.cpu.iq.fu_full::MemRead 55109735 62.90% 63.74% # attempts to use FU when none available 354system.cpu.iq.fu_full::MemWrite 31764891 36.26% 100.00% # attempts to use FU when none available | 402system.cpu.iq.fu_full::IntAlu 717080 0.82% 0.82% # attempts to use FU when none available 403system.cpu.iq.fu_full::IntMult 24380 0.03% 0.85% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available 431system.cpu.iq.fu_full::MemRead 55165781 62.93% 63.78% # attempts to use FU when none available 432system.cpu.iq.fu_full::MemWrite 31749638 36.22% 100.00% # attempts to use FU when none available |
| 355system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 356system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 357system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 433system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 434system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 435system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 358system.cpu.iq.FU_type_0::IntAlu 1103878887 45.37% 45.37% # Type of FU issued 359system.cpu.iq.FU_type_0::IntMult 11223380 0.46% 45.84% # Type of FU issued | 436system.cpu.iq.FU_type_0::IntAlu 1103940359 45.38% 45.38% # Type of FU issued 437system.cpu.iq.FU_type_0::IntMult 11224025 0.46% 45.84% # Type of FU issued |
| 360system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued | 438system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued |
| 361system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.84% # Type of FU issued | 439system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued |
| 362system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued 363system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued 364system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued 365system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued 366system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued | 440system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued |
| 378system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.89% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.89% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatCmp 6876473 0.28% 46.18% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatCvt 5503230 0.23% 46.40% # Type of FU issued | 456system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatCvt 5502268 0.23% 46.40% # Type of FU issued |
| 382system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued | 460system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued |
| 383system.cpu.iq.FU_type_0::SimdFloatMisc 23422628 0.96% 47.36% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.36% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.36% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.36% # Type of FU issued 387system.cpu.iq.FU_type_0::MemRead 838195655 34.45% 81.82% # Type of FU issued 388system.cpu.iq.FU_type_0::MemWrite 442341757 18.18% 100.00% # Type of FU issued | 461system.cpu.iq.FU_type_0::SimdFloatMisc 23395329 0.96% 47.37% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued 465system.cpu.iq.FU_type_0::MemRead 838660213 34.47% 81.84% # Type of FU issued 466system.cpu.iq.FU_type_0::MemWrite 441822804 18.16% 100.00% # Type of FU issued |
| 389system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 390system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 467system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 468system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 391system.cpu.iq.FU_type_0::total 2432817301 # Type of FU issued 392system.cpu.iq.rate 1.938727 # Inst issue rate 393system.cpu.iq.fu_busy_cnt 87614143 # FU busy when requested 394system.cpu.iq.fu_busy_rate 0.036013 # FU busy rate (busy events/executed inst) 395system.cpu.iq.int_inst_queue_reads 6056711081 # Number of integer instruction queue reads 396system.cpu.iq.int_inst_queue_writes 3602481479 # Number of integer instruction queue writes 397system.cpu.iq.int_inst_queue_wakeup_accesses 2248827251 # Number of integer instruction queue wakeup accesses 398system.cpu.iq.fp_inst_queue_reads 122554312 # Number of floating instruction queue reads 399system.cpu.iq.fp_inst_queue_writes 82864717 # Number of floating instruction queue writes 400system.cpu.iq.fp_inst_queue_wakeup_accesses 56458852 # Number of floating instruction queue wakeup accesses 401system.cpu.iq.int_alu_accesses 2457090579 # Number of integer alu accesses 402system.cpu.iq.fp_alu_accesses 63340865 # Number of floating point alu accesses 403system.cpu.iew.lsq.thread0.forwLoads 84315452 # Number of loads that had data forwarded from stores | 469system.cpu.iq.FU_type_0::total 2432796766 # Type of FU issued 470system.cpu.iq.rate 1.933415 # Inst issue rate 471system.cpu.iq.fu_busy_cnt 87656879 # FU busy when requested 472system.cpu.iq.fu_busy_rate 0.036031 # FU busy rate (busy events/executed inst) 473system.cpu.iq.int_inst_queue_reads 6059775624 # Number of integer instruction queue reads 474system.cpu.iq.int_inst_queue_writes 3603986878 # Number of integer instruction queue writes 475system.cpu.iq.int_inst_queue_wakeup_accesses 2248220965 # Number of integer instruction queue wakeup accesses 476system.cpu.iq.fp_inst_queue_reads 122491061 # Number of floating instruction queue reads 477system.cpu.iq.fp_inst_queue_writes 82640163 # Number of floating instruction queue writes 478system.cpu.iq.fp_inst_queue_wakeup_accesses 56428970 # Number of floating instruction queue wakeup accesses 479system.cpu.iq.int_alu_accesses 2457145320 # Number of integer alu accesses 480system.cpu.iq.fp_alu_accesses 63308325 # Number of floating point alu accesses 481system.cpu.iew.lsq.thread0.forwLoads 84445856 # Number of loads that had data forwarded from stores |
| 404system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 482system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 405system.cpu.iew.lsq.thread0.squashedLoads 338421730 # Number of loads squashed 406system.cpu.iew.lsq.thread0.ignoredResponses 8530 # Number of memory responses ignored because the instruction is squashed 407system.cpu.iew.lsq.thread0.memOrderViolation 1429952 # Number of memory ordering violations 408system.cpu.iew.lsq.thread0.squashedStores 210412350 # Number of stores squashed | 483system.cpu.iew.lsq.thread0.squashedLoads 340236717 # Number of loads squashed 484system.cpu.iew.lsq.thread0.ignoredResponses 10068 # Number of memory responses ignored because the instruction is squashed 485system.cpu.iew.lsq.thread0.memOrderViolation 1429873 # Number of memory ordering violations 486system.cpu.iew.lsq.thread0.squashedStores 210438994 # Number of stores squashed |
| 409system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 410system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 487system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 488system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 411system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled 412system.cpu.iew.lsq.thread0.cacheBlocked 257 # Number of times an access to memory failed due to the cache being blocked | 489system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled 490system.cpu.iew.lsq.thread0.cacheBlocked 345 # Number of times an access to memory failed due to the cache being blocked |
| 413system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 491system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 414system.cpu.iew.iewSquashCycles 125899885 # Number of cycles IEW is squashing 415system.cpu.iew.iewBlockCycles 12642453 # Number of cycles IEW is blocking 416system.cpu.iew.iewUnblockCycles 1559188 # Number of cycles IEW is unblocking 417system.cpu.iew.iewDispatchedInsts 2791598235 # Number of instructions dispatched to IQ 418system.cpu.iew.iewDispSquashedInsts 1393439 # Number of squashed instructions skipped by dispatch 419system.cpu.iew.iewDispLoadInsts 969808911 # Number of dispatched load instructions 420system.cpu.iew.iewDispStoreInsts 487407647 # Number of dispatched store instructions 421system.cpu.iew.iewDispNonSpecInsts 19105 # Number of dispatched non-speculative instructions 422system.cpu.iew.iewIQFullEvents 1555218 # Number of times the IQ has become full, causing a stall 423system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall 424system.cpu.iew.memOrderViolationEvents 1429952 # Number of memory order violations 425system.cpu.iew.predictedTakenIncorrect 32462166 # Number of branches that were predicted taken incorrectly 426system.cpu.iew.predictedNotTakenIncorrect 1535020 # Number of branches that were predicted not taken incorrectly 427system.cpu.iew.branchMispredicts 33997186 # Number of branch mispredicts detected at execute 428system.cpu.iew.iewExecutedInsts 2358042615 # Number of executed instructions 429system.cpu.iew.iewExecLoadInsts 792538170 # Number of load instructions executed 430system.cpu.iew.iewExecSquashedInsts 74774686 # Number of squashed instructions skipped in execute | 492system.cpu.iew.iewSquashCycles 125893395 # Number of cycles IEW is squashing 493system.cpu.iew.iewBlockCycles 15644195 # Number of cycles IEW is blocking 494system.cpu.iew.iewUnblockCycles 1562618 # Number of cycles IEW is unblocking 495system.cpu.iew.iewDispatchedInsts 2792235356 # Number of instructions dispatched to IQ 496system.cpu.iew.iewDispSquashedInsts 1396921 # Number of squashed instructions skipped by dispatch 497system.cpu.iew.iewDispLoadInsts 971623898 # Number of dispatched load instructions 498system.cpu.iew.iewDispStoreInsts 487434291 # Number of dispatched store instructions 499system.cpu.iew.iewDispNonSpecInsts 18262 # Number of dispatched non-speculative instructions 500system.cpu.iew.iewIQFullEvents 1558827 # Number of times the IQ has become full, causing a stall 501system.cpu.iew.iewLSQFullEvents 2523 # Number of times the LSQ has become full, causing a stall 502system.cpu.iew.memOrderViolationEvents 1429873 # Number of memory order violations 503system.cpu.iew.predictedTakenIncorrect 32450935 # Number of branches that were predicted taken incorrectly 504system.cpu.iew.predictedNotTakenIncorrect 1518228 # Number of branches that were predicted not taken incorrectly 505system.cpu.iew.branchMispredicts 33969163 # Number of branch mispredicts detected at execute 506system.cpu.iew.iewExecutedInsts 2357455643 # Number of executed instructions 507system.cpu.iew.iewExecLoadInsts 792848546 # Number of load instructions executed 508system.cpu.iew.iewExecSquashedInsts 75341123 # Number of squashed instructions skipped in execute |
| 431system.cpu.iew.exec_swp 0 # number of swp insts executed | 509system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 432system.cpu.iew.exec_nop 12520 # number of nop insts executed 433system.cpu.iew.exec_refs 1216339727 # number of memory reference insts executed 434system.cpu.iew.exec_branches 319851158 # Number of branches executed 435system.cpu.iew.exec_stores 423801557 # Number of stores executed 436system.cpu.iew.exec_rate 1.879139 # Inst execution rate 437system.cpu.iew.wb_sent 2331014082 # cumulative count of insts sent to commit 438system.cpu.iew.wb_count 2305286103 # cumulative count of insts written-back 439system.cpu.iew.wb_producers 1347320139 # num instructions producing a value 440system.cpu.iew.wb_consumers 2523004414 # num instructions consuming a value | 510system.cpu.iew.exec_nop 12449 # number of nop insts executed 511system.cpu.iew.exec_refs 1216025241 # number of memory reference insts executed 512system.cpu.iew.exec_branches 319732380 # Number of branches executed 513system.cpu.iew.exec_stores 423176695 # Number of stores executed 514system.cpu.iew.exec_rate 1.873540 # Inst execution rate 515system.cpu.iew.wb_sent 2330413186 # cumulative count of insts sent to commit 516system.cpu.iew.wb_count 2304649935 # cumulative count of insts written-back 517system.cpu.iew.wb_producers 1347862197 # num instructions producing a value 518system.cpu.iew.wb_consumers 2523443205 # num instructions consuming a value |
| 441system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 519system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 442system.cpu.iew.wb_rate 1.837097 # insts written-back per cycle 443system.cpu.iew.wb_fanout 0.534014 # average fanout of values written-back | 520system.cpu.iew.wb_rate 1.831573 # insts written-back per cycle 521system.cpu.iew.wb_fanout 0.534136 # average fanout of values written-back |
| 444system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 522system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 445system.cpu.commit.commitSquashedInsts 906262003 # The number of squashed insts skipped by commit | 523system.cpu.commit.commitSquashedInsts 906899118 # The number of squashed insts skipped by commit |
| 446system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards | 524system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards |
| 447system.cpu.commit.branchMispredicts 30621444 # The number of times a branch was mispredicted 448system.cpu.commit.committed_per_cycle::samples 1086852717 # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::mean 1.734675 # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::stdev 2.398797 # Number of insts commited each cycle | 525system.cpu.commit.branchMispredicts 30614902 # The number of times a branch was mispredicted 526system.cpu.commit.committed_per_cycle::samples 1089841541 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::mean 1.729918 # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::stdev 2.397219 # Number of insts commited each cycle |
| 451system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 529system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 452system.cpu.commit.committed_per_cycle::0 446522418 41.08% 41.08% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::1 288653852 26.56% 67.64% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::2 95098505 8.75% 76.39% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::3 70200543 6.46% 82.85% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::4 46464549 4.28% 87.13% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::5 22199454 2.04% 89.17% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::6 15846996 1.46% 90.63% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::7 10984775 1.01% 91.64% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::8 90881625 8.36% 100.00% # Number of insts commited each cycle | 530system.cpu.commit.committed_per_cycle::0 449517068 41.25% 41.25% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::1 288638854 26.48% 67.73% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::2 95107207 8.73% 76.46% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::3 70204085 6.44% 82.90% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::4 46459856 4.26% 87.16% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::5 22200640 2.04% 89.20% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::6 15848625 1.45% 90.65% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::7 10985187 1.01% 91.66% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::8 90880019 8.34% 100.00% # Number of insts commited each cycle |
| 461system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 539system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 464system.cpu.commit.committed_per_cycle::total 1086852717 # Number of insts commited each cycle | 542system.cpu.commit.committed_per_cycle::total 1089841541 # Number of insts commited each cycle |
| 465system.cpu.commit.committedInsts 1384381606 # Number of instructions committed 466system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed 467system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 468system.cpu.commit.refs 908382478 # Number of memory references committed 469system.cpu.commit.loads 631387181 # Number of loads committed 470system.cpu.commit.membars 9986 # Number of memory barriers committed 471system.cpu.commit.branches 298259106 # Number of branches committed 472system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. 473system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. 474system.cpu.commit.function_calls 41577833 # Number of function calls committed. | 543system.cpu.commit.committedInsts 1384381606 # Number of instructions committed 544system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed 545system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 546system.cpu.commit.refs 908382478 # Number of memory references committed 547system.cpu.commit.loads 631387181 # Number of loads committed 548system.cpu.commit.membars 9986 # Number of memory barriers committed 549system.cpu.commit.branches 298259106 # Number of branches committed 550system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. 551system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. 552system.cpu.commit.function_calls 41577833 # Number of function calls committed. |
| 475system.cpu.commit.bw_lim_events 90881625 # number cycles where commit BW limit reached | 553system.cpu.commit.bw_lim_events 90880019 # number cycles where commit BW limit reached |
| 476system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 554system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 477system.cpu.rob.rob_reads 3787551108 # The number of ROB reads 478system.cpu.rob.rob_writes 5709107671 # The number of ROB writes 479system.cpu.timesIdled 353124 # Number of times that the entire CPU went into an idle state and unscheduled itself 480system.cpu.idleCycles 42100371 # Total number of cycles that the CPU has spent unscheduled due to idling | 555system.cpu.rob.rob_reads 3791178653 # The number of ROB reads 556system.cpu.rob.rob_writes 5710375191 # The number of ROB writes 557system.cpu.timesIdled 353026 # Number of times that the entire CPU went into an idle state and unscheduled itself 558system.cpu.idleCycles 42554766 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 481system.cpu.committedInsts 1384370590 # Number of Instructions Simulated 482system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated 483system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated | 559system.cpu.committedInsts 1384370590 # Number of Instructions Simulated 560system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated 561system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated |
| 484system.cpu.cpi 0.906443 # CPI: Cycles Per Instruction 485system.cpu.cpi_total 0.906443 # CPI: Total CPI of All Threads 486system.cpu.ipc 1.103213 # IPC: Instructions Per Cycle 487system.cpu.ipc_total 1.103213 # IPC: Total IPC of All Threads 488system.cpu.int_regfile_reads 11756785732 # number of integer regfile reads 489system.cpu.int_regfile_writes 2218462767 # number of integer regfile writes 490system.cpu.fp_regfile_reads 68799116 # number of floating regfile reads 491system.cpu.fp_regfile_writes 49570496 # number of floating regfile writes 492system.cpu.misc_regfile_reads 1364149303 # number of misc regfile reads | 562system.cpu.cpi 0.908925 # CPI: Cycles Per Instruction 563system.cpu.cpi_total 0.908925 # CPI: Total CPI of All Threads 564system.cpu.ipc 1.100200 # IPC: Instructions Per Cycle 565system.cpu.ipc_total 1.100200 # IPC: Total IPC of All Threads 566system.cpu.int_regfile_reads 11755248902 # number of integer regfile reads 567system.cpu.int_regfile_writes 2218571084 # number of integer regfile writes 568system.cpu.fp_regfile_reads 68795959 # number of floating regfile reads 569system.cpu.fp_regfile_writes 49541079 # number of floating regfile writes 570system.cpu.misc_regfile_reads 1363718123 # number of misc regfile reads |
| 493system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes | 571system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes |
| 494system.cpu.icache.replacements 22544 # number of replacements 495system.cpu.icache.tagsinuse 1643.593682 # Cycle average of tags in use 496system.cpu.icache.total_refs 335759855 # Total number of references to valid blocks. 497system.cpu.icache.sampled_refs 24228 # Sample count of references to valid blocks. 498system.cpu.icache.avg_refs 13858.339731 # Average number of references to valid blocks. | 572system.cpu.toL2Bus.throughput 169026080 # Throughput (bytes/s) 573system.cpu.toL2Bus.trans_dist::ReadReq 1492742 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::ReadResp 1492741 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::Writeback 96335 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::ReadExReq 72516 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadExResp 72516 # Transaction distribution 580system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52382 # Packet count per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178768 # Packet count per connected master and slave (bytes) 582system.cpu.toL2Bus.pkt_count 3231150 # Packet count per connected master and slave (bytes) 583system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1538688 # Cumulative packet size per connected master and slave (bytes) 584system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104528128 # Cumulative packet size per connected master and slave (bytes) 585system.cpu.toL2Bus.tot_pkt_size 106066816 # Cumulative packet size per connected master and slave (bytes) 586system.cpu.toL2Bus.data_through_bus 106066816 # Total data (bytes) 587system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes) 588system.cpu.toL2Bus.reqLayer0.occupancy 929281000 # Layer occupancy (ticks) 589system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 590system.cpu.toL2Bus.respLayer0.occupancy 42510998 # Layer occupancy (ticks) 591system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 592system.cpu.toL2Bus.respLayer1.occupancy 2307535978 # Layer occupancy (ticks) 593system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 594system.cpu.icache.replacements 22361 # number of replacements 595system.cpu.icache.tagsinuse 1639.588858 # Cycle average of tags in use 596system.cpu.icache.total_refs 335620121 # Total number of references to valid blocks. 597system.cpu.icache.sampled_refs 24041 # Sample count of references to valid blocks. 598system.cpu.icache.avg_refs 13960.322824 # Average number of references to valid blocks. |
| 499system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 599system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 500system.cpu.icache.occ_blocks::cpu.inst 1643.593682 # Average occupied blocks per requestor 501system.cpu.icache.occ_percent::cpu.inst 0.802536 # Average percentage of cache occupancy 502system.cpu.icache.occ_percent::total 0.802536 # Average percentage of cache occupancy 503system.cpu.icache.ReadReq_hits::cpu.inst 335766423 # number of ReadReq hits 504system.cpu.icache.ReadReq_hits::total 335766423 # number of ReadReq hits 505system.cpu.icache.demand_hits::cpu.inst 335766423 # number of demand (read+write) hits 506system.cpu.icache.demand_hits::total 335766423 # number of demand (read+write) hits 507system.cpu.icache.overall_hits::cpu.inst 335766423 # number of overall hits 508system.cpu.icache.overall_hits::total 335766423 # number of overall hits 509system.cpu.icache.ReadReq_misses::cpu.inst 31408 # number of ReadReq misses 510system.cpu.icache.ReadReq_misses::total 31408 # number of ReadReq misses 511system.cpu.icache.demand_misses::cpu.inst 31408 # number of demand (read+write) misses 512system.cpu.icache.demand_misses::total 31408 # number of demand (read+write) misses 513system.cpu.icache.overall_misses::cpu.inst 31408 # number of overall misses 514system.cpu.icache.overall_misses::total 31408 # number of overall misses 515system.cpu.icache.ReadReq_miss_latency::cpu.inst 477378999 # number of ReadReq miss cycles 516system.cpu.icache.ReadReq_miss_latency::total 477378999 # number of ReadReq miss cycles 517system.cpu.icache.demand_miss_latency::cpu.inst 477378999 # number of demand (read+write) miss cycles 518system.cpu.icache.demand_miss_latency::total 477378999 # number of demand (read+write) miss cycles 519system.cpu.icache.overall_miss_latency::cpu.inst 477378999 # number of overall miss cycles 520system.cpu.icache.overall_miss_latency::total 477378999 # number of overall miss cycles 521system.cpu.icache.ReadReq_accesses::cpu.inst 335797831 # number of ReadReq accesses(hits+misses) 522system.cpu.icache.ReadReq_accesses::total 335797831 # number of ReadReq accesses(hits+misses) 523system.cpu.icache.demand_accesses::cpu.inst 335797831 # number of demand (read+write) accesses 524system.cpu.icache.demand_accesses::total 335797831 # number of demand (read+write) accesses 525system.cpu.icache.overall_accesses::cpu.inst 335797831 # number of overall (read+write) accesses 526system.cpu.icache.overall_accesses::total 335797831 # number of overall (read+write) accesses 527system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses 528system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses 529system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses 530system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses 531system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses 532system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses 533system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15199.280406 # average ReadReq miss latency 534system.cpu.icache.ReadReq_avg_miss_latency::total 15199.280406 # average ReadReq miss latency 535system.cpu.icache.demand_avg_miss_latency::cpu.inst 15199.280406 # average overall miss latency 536system.cpu.icache.demand_avg_miss_latency::total 15199.280406 # average overall miss latency 537system.cpu.icache.overall_avg_miss_latency::cpu.inst 15199.280406 # average overall miss latency 538system.cpu.icache.overall_avg_miss_latency::total 15199.280406 # average overall miss latency 539system.cpu.icache.blocked_cycles::no_mshrs 872 # number of cycles access was blocked | 600system.cpu.icache.occ_blocks::cpu.inst 1639.588858 # Average occupied blocks per requestor 601system.cpu.icache.occ_percent::cpu.inst 0.800580 # Average percentage of cache occupancy 602system.cpu.icache.occ_percent::total 0.800580 # Average percentage of cache occupancy 603system.cpu.icache.ReadReq_hits::cpu.inst 335624135 # number of ReadReq hits 604system.cpu.icache.ReadReq_hits::total 335624135 # number of ReadReq hits 605system.cpu.icache.demand_hits::cpu.inst 335624135 # number of demand (read+write) hits 606system.cpu.icache.demand_hits::total 335624135 # number of demand (read+write) hits 607system.cpu.icache.overall_hits::cpu.inst 335624135 # number of overall hits 608system.cpu.icache.overall_hits::total 335624135 # number of overall hits 609system.cpu.icache.ReadReq_misses::cpu.inst 30883 # number of ReadReq misses 610system.cpu.icache.ReadReq_misses::total 30883 # number of ReadReq misses 611system.cpu.icache.demand_misses::cpu.inst 30883 # number of demand (read+write) misses 612system.cpu.icache.demand_misses::total 30883 # number of demand (read+write) misses 613system.cpu.icache.overall_misses::cpu.inst 30883 # number of overall misses 614system.cpu.icache.overall_misses::total 30883 # number of overall misses 615system.cpu.icache.ReadReq_miss_latency::cpu.inst 525457997 # number of ReadReq miss cycles 616system.cpu.icache.ReadReq_miss_latency::total 525457997 # number of ReadReq miss cycles 617system.cpu.icache.demand_miss_latency::cpu.inst 525457997 # number of demand (read+write) miss cycles 618system.cpu.icache.demand_miss_latency::total 525457997 # number of demand (read+write) miss cycles 619system.cpu.icache.overall_miss_latency::cpu.inst 525457997 # number of overall miss cycles 620system.cpu.icache.overall_miss_latency::total 525457997 # number of overall miss cycles 621system.cpu.icache.ReadReq_accesses::cpu.inst 335655018 # number of ReadReq accesses(hits+misses) 622system.cpu.icache.ReadReq_accesses::total 335655018 # number of ReadReq accesses(hits+misses) 623system.cpu.icache.demand_accesses::cpu.inst 335655018 # number of demand (read+write) accesses 624system.cpu.icache.demand_accesses::total 335655018 # number of demand (read+write) accesses 625system.cpu.icache.overall_accesses::cpu.inst 335655018 # number of overall (read+write) accesses 626system.cpu.icache.overall_accesses::total 335655018 # number of overall (read+write) accesses 627system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses 628system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses 629system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses 630system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses 631system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses 632system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses 633system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17014.473885 # average ReadReq miss latency 634system.cpu.icache.ReadReq_avg_miss_latency::total 17014.473885 # average ReadReq miss latency 635system.cpu.icache.demand_avg_miss_latency::cpu.inst 17014.473885 # average overall miss latency 636system.cpu.icache.demand_avg_miss_latency::total 17014.473885 # average overall miss latency 637system.cpu.icache.overall_avg_miss_latency::cpu.inst 17014.473885 # average overall miss latency 638system.cpu.icache.overall_avg_miss_latency::total 17014.473885 # average overall miss latency 639system.cpu.icache.blocked_cycles::no_mshrs 2055 # number of cycles access was blocked |
| 540system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 640system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 541system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked | 641system.cpu.icache.blocked::no_mshrs 35 # number of cycles access was blocked |
| 542system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 642system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 543system.cpu.icache.avg_blocked_cycles::no_mshrs 33.538462 # average number of cycles each access was blocked | 643system.cpu.icache.avg_blocked_cycles::no_mshrs 58.714286 # average number of cycles each access was blocked |
| 544system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 545system.cpu.icache.fast_writes 0 # number of fast writes performed 546system.cpu.icache.cache_copies 0 # number of cache copies performed | 644system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 645system.cpu.icache.fast_writes 0 # number of fast writes performed 646system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 547system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2844 # number of ReadReq MSHR hits 548system.cpu.icache.ReadReq_mshr_hits::total 2844 # number of ReadReq MSHR hits 549system.cpu.icache.demand_mshr_hits::cpu.inst 2844 # number of demand (read+write) MSHR hits 550system.cpu.icache.demand_mshr_hits::total 2844 # number of demand (read+write) MSHR hits 551system.cpu.icache.overall_mshr_hits::cpu.inst 2844 # number of overall MSHR hits 552system.cpu.icache.overall_mshr_hits::total 2844 # number of overall MSHR hits 553system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses 554system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses 555system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses 556system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses 557system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses 558system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses 559system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 383349499 # number of ReadReq MSHR miss cycles 560system.cpu.icache.ReadReq_mshr_miss_latency::total 383349499 # number of ReadReq MSHR miss cycles 561system.cpu.icache.demand_mshr_miss_latency::cpu.inst 383349499 # number of demand (read+write) MSHR miss cycles 562system.cpu.icache.demand_mshr_miss_latency::total 383349499 # number of demand (read+write) MSHR miss cycles 563system.cpu.icache.overall_mshr_miss_latency::cpu.inst 383349499 # number of overall MSHR miss cycles 564system.cpu.icache.overall_mshr_miss_latency::total 383349499 # number of overall MSHR miss cycles 565system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses 566system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000085 # mshr miss rate for ReadReq accesses 567system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses 568system.cpu.icache.demand_mshr_miss_rate::total 0.000085 # mshr miss rate for demand accesses 569system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses 570system.cpu.icache.overall_mshr_miss_rate::total 0.000085 # mshr miss rate for overall accesses 571system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13420.721853 # average ReadReq mshr miss latency 572system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13420.721853 # average ReadReq mshr miss latency 573system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13420.721853 # average overall mshr miss latency 574system.cpu.icache.demand_avg_mshr_miss_latency::total 13420.721853 # average overall mshr miss latency 575system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13420.721853 # average overall mshr miss latency 576system.cpu.icache.overall_avg_mshr_miss_latency::total 13420.721853 # average overall mshr miss latency | 647system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2543 # number of ReadReq MSHR hits 648system.cpu.icache.ReadReq_mshr_hits::total 2543 # number of ReadReq MSHR hits 649system.cpu.icache.demand_mshr_hits::cpu.inst 2543 # number of demand (read+write) MSHR hits 650system.cpu.icache.demand_mshr_hits::total 2543 # number of demand (read+write) MSHR hits 651system.cpu.icache.overall_mshr_hits::cpu.inst 2543 # number of overall MSHR hits 652system.cpu.icache.overall_mshr_hits::total 2543 # number of overall MSHR hits 653system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28340 # number of ReadReq MSHR misses 654system.cpu.icache.ReadReq_mshr_misses::total 28340 # number of ReadReq MSHR misses 655system.cpu.icache.demand_mshr_misses::cpu.inst 28340 # number of demand (read+write) MSHR misses 656system.cpu.icache.demand_mshr_misses::total 28340 # number of demand (read+write) MSHR misses 657system.cpu.icache.overall_mshr_misses::cpu.inst 28340 # number of overall MSHR misses 658system.cpu.icache.overall_mshr_misses::total 28340 # number of overall MSHR misses 659system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 421731499 # number of ReadReq MSHR miss cycles 660system.cpu.icache.ReadReq_mshr_miss_latency::total 421731499 # number of ReadReq MSHR miss cycles 661system.cpu.icache.demand_mshr_miss_latency::cpu.inst 421731499 # number of demand (read+write) MSHR miss cycles 662system.cpu.icache.demand_mshr_miss_latency::total 421731499 # number of demand (read+write) MSHR miss cycles 663system.cpu.icache.overall_mshr_miss_latency::cpu.inst 421731499 # number of overall MSHR miss cycles 664system.cpu.icache.overall_mshr_miss_latency::total 421731499 # number of overall MSHR miss cycles 665system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for ReadReq accesses 666system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadReq accesses 667system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses 668system.cpu.icache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses 669system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses 670system.cpu.icache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14881.139697 # average ReadReq mshr miss latency 672system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14881.139697 # average ReadReq mshr miss latency 673system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14881.139697 # average overall mshr miss latency 674system.cpu.icache.demand_avg_mshr_miss_latency::total 14881.139697 # average overall mshr miss latency 675system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14881.139697 # average overall mshr miss latency 676system.cpu.icache.overall_avg_mshr_miss_latency::total 14881.139697 # average overall mshr miss latency |
| 577system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 677system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 578system.cpu.l2cache.replacements 442161 # number of replacements 579system.cpu.l2cache.tagsinuse 32692.602580 # Cycle average of tags in use 580system.cpu.l2cache.total_refs 1109878 # Total number of references to valid blocks. 581system.cpu.l2cache.sampled_refs 474908 # Sample count of references to valid blocks. 582system.cpu.l2cache.avg_refs 2.337038 # Average number of references to valid blocks. | 678system.cpu.l2cache.replacements 442172 # number of replacements 679system.cpu.l2cache.tagsinuse 32679.418470 # Cycle average of tags in use 680system.cpu.l2cache.total_refs 1109399 # Total number of references to valid blocks. 681system.cpu.l2cache.sampled_refs 474919 # Sample count of references to valid blocks. 682system.cpu.l2cache.avg_refs 2.335975 # Average number of references to valid blocks. |
| 583system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 683system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 584system.cpu.l2cache.occ_blocks::writebacks 1286.251763 # Average occupied blocks per requestor 585system.cpu.l2cache.occ_blocks::cpu.inst 48.224535 # Average occupied blocks per requestor 586system.cpu.l2cache.occ_blocks::cpu.data 31358.126282 # Average occupied blocks per requestor 587system.cpu.l2cache.occ_percent::writebacks 0.039253 # Average percentage of cache occupancy 588system.cpu.l2cache.occ_percent::cpu.inst 0.001472 # Average percentage of cache occupancy 589system.cpu.l2cache.occ_percent::cpu.data 0.956974 # Average percentage of cache occupancy 590system.cpu.l2cache.occ_percent::total 0.997699 # Average percentage of cache occupancy 591system.cpu.l2cache.ReadReq_hits::cpu.inst 21816 # number of ReadReq hits 592system.cpu.l2cache.ReadReq_hits::cpu.data 1058230 # number of ReadReq hits 593system.cpu.l2cache.ReadReq_hits::total 1080046 # number of ReadReq hits 594system.cpu.l2cache.Writeback_hits::writebacks 96322 # number of Writeback hits 595system.cpu.l2cache.Writeback_hits::total 96322 # number of Writeback hits | 684system.cpu.l2cache.occ_blocks::writebacks 1315.444690 # Average occupied blocks per requestor 685system.cpu.l2cache.occ_blocks::cpu.inst 50.407521 # Average occupied blocks per requestor 686system.cpu.l2cache.occ_blocks::cpu.data 31313.566259 # Average occupied blocks per requestor 687system.cpu.l2cache.occ_percent::writebacks 0.040144 # Average percentage of cache occupancy 688system.cpu.l2cache.occ_percent::cpu.inst 0.001538 # Average percentage of cache occupancy 689system.cpu.l2cache.occ_percent::cpu.data 0.955614 # Average percentage of cache occupancy 690system.cpu.l2cache.occ_percent::total 0.997297 # Average percentage of cache occupancy 691system.cpu.l2cache.ReadReq_hits::cpu.inst 21617 # number of ReadReq hits 692system.cpu.l2cache.ReadReq_hits::cpu.data 1057925 # number of ReadReq hits 693system.cpu.l2cache.ReadReq_hits::total 1079542 # number of ReadReq hits 694system.cpu.l2cache.Writeback_hits::writebacks 96335 # number of Writeback hits 695system.cpu.l2cache.Writeback_hits::total 96335 # number of Writeback hits |
| 596system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 597system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 598system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits 599system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits | 696system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 697system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 698system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits 699system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits |
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number of demand (read+write) miss cycles 625system.cpu.l2cache.demand_miss_latency::cpu.data 32215126000 # number of demand (read+write) miss cycles 626system.cpu.l2cache.demand_miss_latency::total 32347162000 # number of demand (read+write) miss cycles 627system.cpu.l2cache.overall_miss_latency::cpu.inst 132036000 # number of overall miss cycles 628system.cpu.l2cache.overall_miss_latency::cpu.data 32215126000 # number of overall miss cycles 629system.cpu.l2cache.overall_miss_latency::total 32347162000 # number of overall miss cycles 630system.cpu.l2cache.ReadReq_accesses::cpu.inst 24231 # number of ReadReq accesses(hits+misses) 631system.cpu.l2cache.ReadReq_accesses::cpu.data 1464705 # number of ReadReq accesses(hits+misses) 632system.cpu.l2cache.ReadReq_accesses::total 1488936 # number of ReadReq accesses(hits+misses) 633system.cpu.l2cache.Writeback_accesses::writebacks 96322 # number of Writeback accesses(hits+misses) 634system.cpu.l2cache.Writeback_accesses::total 96322 # number of Writeback accesses(hits+misses) 635system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4334 # number of UpgradeReq accesses(hits+misses) 636system.cpu.l2cache.UpgradeReq_accesses::total 4334 # number of UpgradeReq accesses(hits+misses) 637system.cpu.l2cache.ReadExReq_accesses::cpu.data 72519 # number of ReadExReq accesses(hits+misses) 638system.cpu.l2cache.ReadExReq_accesses::total 72519 # number of ReadExReq accesses(hits+misses) 639system.cpu.l2cache.demand_accesses::cpu.inst 24231 # number of demand (read+write) accesses 640system.cpu.l2cache.demand_accesses::cpu.data 1537224 # number of demand (read+write) accesses 641system.cpu.l2cache.demand_accesses::total 1561455 # number of demand (read+write) accesses 642system.cpu.l2cache.overall_accesses::cpu.inst 24231 # number of overall (read+write) accesses 643system.cpu.l2cache.overall_accesses::cpu.data 1537224 # number of overall (read+write) accesses 644system.cpu.l2cache.overall_accesses::total 1561455 # number of overall (read+write) accesses 645system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099666 # miss rate for ReadReq accesses 646system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277513 # miss rate for ReadReq accesses 647system.cpu.l2cache.ReadReq_miss_rate::total 0.274619 # miss rate for ReadReq accesses 648system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999308 # miss rate for UpgradeReq accesses 649system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999308 # miss rate for UpgradeReq accesses 650system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911182 # miss rate for ReadExReq accesses 651system.cpu.l2cache.ReadExReq_miss_rate::total 0.911182 # miss rate for ReadExReq accesses 652system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099666 # miss rate for demand accesses 653system.cpu.l2cache.demand_miss_rate::cpu.data 0.307407 # miss rate for demand accesses 654system.cpu.l2cache.demand_miss_rate::total 0.304183 # miss rate for demand accesses 655system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099666 # miss rate for overall accesses 656system.cpu.l2cache.overall_miss_rate::cpu.data 0.307407 # miss rate for overall accesses 657system.cpu.l2cache.overall_miss_rate::total 0.304183 # miss rate for overall accesses 658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54673.291925 # average ReadReq miss latency 659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71445.322591 # average ReadReq miss latency 660system.cpu.l2cache.ReadReq_avg_miss_latency::total 71346.263054 # average ReadReq miss latency 661system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.020884 # average ReadExReq miss latency 662system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.020884 # average ReadExReq miss latency 663system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54673.291925 # average overall miss latency 664system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68172.513983 # average overall miss latency 665system.cpu.l2cache.demand_avg_miss_latency::total 68103.876472 # average overall miss latency 666system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54673.291925 # average overall miss latency 667system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68172.513983 # average overall miss latency 668system.cpu.l2cache.overall_avg_miss_latency::total 68103.876472 # average overall miss latency | 700system.cpu.l2cache.demand_hits::cpu.inst 21617 # number of demand (read+write) hits 701system.cpu.l2cache.demand_hits::cpu.data 1064366 # number of demand (read+write) hits 702system.cpu.l2cache.demand_hits::total 1085983 # number of demand (read+write) hits 703system.cpu.l2cache.overall_hits::cpu.inst 21617 # number of overall hits 704system.cpu.l2cache.overall_hits::cpu.data 1064366 # number of overall hits 705system.cpu.l2cache.overall_hits::total 1085983 # number of overall hits 706system.cpu.l2cache.ReadReq_misses::cpu.inst 2425 # number of ReadReq misses 707system.cpu.l2cache.ReadReq_misses::cpu.data 406477 # number of ReadReq misses 708system.cpu.l2cache.ReadReq_misses::total 408902 # number of ReadReq misses 709system.cpu.l2cache.UpgradeReq_misses::cpu.data 4296 # number of UpgradeReq misses 710system.cpu.l2cache.UpgradeReq_misses::total 4296 # number of UpgradeReq misses 711system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # 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number of ReadExReq miss cycles 724system.cpu.l2cache.demand_miss_latency::cpu.inst 172881000 # number of demand (read+write) miss cycles 725system.cpu.l2cache.demand_miss_latency::cpu.data 35353300000 # number of demand (read+write) miss cycles 726system.cpu.l2cache.demand_miss_latency::total 35526181000 # number of demand (read+write) miss cycles 727system.cpu.l2cache.overall_miss_latency::cpu.inst 172881000 # number of overall miss cycles 728system.cpu.l2cache.overall_miss_latency::cpu.data 35353300000 # number of overall miss cycles 729system.cpu.l2cache.overall_miss_latency::total 35526181000 # number of overall miss cycles 730system.cpu.l2cache.ReadReq_accesses::cpu.inst 24042 # number of ReadReq accesses(hits+misses) 731system.cpu.l2cache.ReadReq_accesses::cpu.data 1464402 # number of ReadReq accesses(hits+misses) 732system.cpu.l2cache.ReadReq_accesses::total 1488444 # number of ReadReq accesses(hits+misses) 733system.cpu.l2cache.Writeback_accesses::writebacks 96335 # number of Writeback accesses(hits+misses) 734system.cpu.l2cache.Writeback_accesses::total 96335 # number of Writeback accesses(hits+misses) 735system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4299 # number of UpgradeReq accesses(hits+misses) 736system.cpu.l2cache.UpgradeReq_accesses::total 4299 # number of UpgradeReq accesses(hits+misses) 737system.cpu.l2cache.ReadExReq_accesses::cpu.data 72516 # number of ReadExReq accesses(hits+misses) 738system.cpu.l2cache.ReadExReq_accesses::total 72516 # number of ReadExReq accesses(hits+misses) 739system.cpu.l2cache.demand_accesses::cpu.inst 24042 # number of demand (read+write) accesses 740system.cpu.l2cache.demand_accesses::cpu.data 1536918 # number of demand (read+write) accesses 741system.cpu.l2cache.demand_accesses::total 1560960 # number of demand (read+write) accesses 742system.cpu.l2cache.overall_accesses::cpu.inst 24042 # number of overall (read+write) accesses 743system.cpu.l2cache.overall_accesses::cpu.data 1536918 # number of overall (read+write) accesses 744system.cpu.l2cache.overall_accesses::total 1560960 # number of overall (read+write) accesses 745system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100865 # miss rate for ReadReq accesses 746system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277572 # miss rate for ReadReq accesses 747system.cpu.l2cache.ReadReq_miss_rate::total 0.274718 # miss rate for ReadReq accesses 748system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999302 # miss rate for UpgradeReq accesses 749system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999302 # miss rate for UpgradeReq accesses 750system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911178 # miss rate for ReadExReq accesses 751system.cpu.l2cache.ReadExReq_miss_rate::total 0.911178 # miss rate for ReadExReq accesses 752system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100865 # miss rate for demand accesses 753system.cpu.l2cache.demand_miss_rate::cpu.data 0.307467 # miss rate for demand accesses 754system.cpu.l2cache.demand_miss_rate::total 0.304285 # miss rate for demand accesses 755system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100865 # miss rate for overall accesses 756system.cpu.l2cache.overall_miss_rate::cpu.data 0.307467 # miss rate for overall accesses 757system.cpu.l2cache.overall_miss_rate::total 0.304285 # miss rate for overall accesses 758system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71291.134021 # average ReadReq miss latency 759system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75698.814447 # average ReadReq miss latency 760system.cpu.l2cache.ReadReq_avg_miss_latency::total 75672.674626 # average ReadReq miss latency 761system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69367.733636 # average ReadExReq miss latency 762system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69367.733636 # average ReadExReq miss latency 763system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71291.134021 # average overall miss latency 764system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74813.565491 # average overall miss latency 765system.cpu.l2cache.demand_avg_miss_latency::total 74795.581681 # average overall miss latency 766system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71291.134021 # average overall miss latency 767system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74813.565491 # average overall miss latency 768system.cpu.l2cache.overall_avg_miss_latency::total 74795.581681 # average overall miss latency |
| 669system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 670system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 671system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 672system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 673system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 674system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 675system.cpu.l2cache.fast_writes 0 # number of fast writes performed 676system.cpu.l2cache.cache_copies 0 # number of cache copies performed 677system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 678system.cpu.l2cache.writebacks::total 66098 # number of writebacks | 769system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 770system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 772system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 773system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 774system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.l2cache.fast_writes 0 # number of fast writes performed 776system.cpu.l2cache.cache_copies 0 # number of cache copies performed 777system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 778system.cpu.l2cache.writebacks::total 66098 # number of writebacks |
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number of ReadReq MSHR misses 691system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4331 # number of UpgradeReq MSHR misses 692system.cpu.l2cache.UpgradeReq_mshr_misses::total 4331 # number of UpgradeReq MSHR misses 693system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66078 # number of ReadExReq MSHR misses 694system.cpu.l2cache.ReadExReq_mshr_misses::total 66078 # number of ReadExReq MSHR misses 695system.cpu.l2cache.demand_mshr_misses::cpu.inst 2411 # number of demand (read+write) MSHR misses 696system.cpu.l2cache.demand_mshr_misses::cpu.data 472533 # number of demand (read+write) MSHR misses 697system.cpu.l2cache.demand_mshr_misses::total 474944 # number of demand (read+write) MSHR misses 698system.cpu.l2cache.overall_mshr_misses::cpu.inst 2411 # number of overall MSHR misses 699system.cpu.l2cache.overall_mshr_misses::cpu.data 472533 # number of overall MSHR misses 700system.cpu.l2cache.overall_mshr_misses::total 474944 # number of overall MSHR misses 701system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101979670 # 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number of overall MSHR miss cycles 712system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26342435970 # number of overall MSHR miss cycles 713system.cpu.l2cache.overall_mshr_miss_latency::total 26444415640 # number of overall MSHR miss cycles 714system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099501 # mshr miss rate for ReadReq accesses 715system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277500 # mshr miss rate for ReadReq accesses 716system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274603 # mshr miss rate for ReadReq accesses 717system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999308 # mshr miss rate for UpgradeReq accesses 718system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999308 # mshr miss rate for UpgradeReq accesses 719system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911182 # mshr miss rate for ReadExReq accesses 720system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911182 # mshr miss rate for ReadExReq accesses 721system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099501 # mshr miss rate for demand accesses 722system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307394 # mshr miss rate for demand accesses 723system.cpu.l2cache.demand_mshr_miss_rate::total 0.304168 # mshr miss rate for demand accesses 724system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099501 # mshr miss rate for overall accesses 725system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307394 # mshr miss rate for overall accesses 726system.cpu.l2cache.overall_mshr_miss_rate::total 0.304168 # mshr miss rate for overall accesses 727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42297.664869 # average ReadReq mshr miss latency 728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59010.864507 # average ReadReq mshr miss latency 729system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58912.310153 # average ReadReq mshr miss latency | 779system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 780system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 781system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits 782system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 783system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 784system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits 785system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 786system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 787system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits 788system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2423 # number of ReadReq MSHR misses 789system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406456 # number of ReadReq MSHR misses 790system.cpu.l2cache.ReadReq_mshr_misses::total 408879 # number of ReadReq MSHR misses 791system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4296 # number of UpgradeReq MSHR misses 792system.cpu.l2cache.UpgradeReq_mshr_misses::total 4296 # number of UpgradeReq MSHR misses 793system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses 794system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses 795system.cpu.l2cache.demand_mshr_misses::cpu.inst 2423 # number of demand (read+write) MSHR misses 796system.cpu.l2cache.demand_mshr_misses::cpu.data 472531 # number of demand (read+write) MSHR misses 797system.cpu.l2cache.demand_mshr_misses::total 474954 # number of demand (read+write) MSHR misses 798system.cpu.l2cache.overall_mshr_misses::cpu.inst 2423 # number of overall MSHR misses 799system.cpu.l2cache.overall_mshr_misses::cpu.data 472531 # number of overall MSHR misses 800system.cpu.l2cache.overall_mshr_misses::total 474954 # number of overall MSHR misses 801system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 142729750 # number of ReadReq MSHR miss cycles 802system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25717512250 # number of ReadReq MSHR miss cycles 803system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25860242000 # number of ReadReq MSHR miss cycles 804system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42964296 # number of UpgradeReq MSHR miss cycles 805system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42964296 # number of UpgradeReq MSHR miss cycles 806system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3766213250 # number of ReadExReq MSHR miss cycles 807system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3766213250 # number of ReadExReq MSHR miss cycles 808system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 142729750 # number of demand (read+write) MSHR miss cycles 809system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29483725500 # number of demand (read+write) MSHR miss cycles 810system.cpu.l2cache.demand_mshr_miss_latency::total 29626455250 # number of demand (read+write) MSHR miss cycles 811system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142729750 # number of overall MSHR miss cycles 812system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29483725500 # number of overall MSHR miss cycles 813system.cpu.l2cache.overall_mshr_miss_latency::total 29626455250 # number of overall MSHR miss cycles 814system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100782 # mshr miss rate for ReadReq accesses 815system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277558 # mshr miss rate for ReadReq accesses 816system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274702 # mshr miss rate for ReadReq accesses 817system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999302 # mshr miss rate for UpgradeReq accesses 818system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999302 # mshr miss rate for UpgradeReq accesses 819system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911178 # mshr miss rate for ReadExReq accesses 820system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911178 # mshr miss rate for ReadExReq accesses 821system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100782 # mshr miss rate for demand accesses 822system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307454 # mshr miss rate for demand accesses 823system.cpu.l2cache.demand_mshr_miss_rate::total 0.304270 # mshr miss rate for demand accesses 824system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100782 # mshr miss rate for overall accesses 825system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307454 # mshr miss rate for overall accesses 826system.cpu.l2cache.overall_mshr_miss_rate::total 0.304270 # mshr miss rate for overall accesses 827system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58906.211308 # average ReadReq mshr miss latency 828system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63272.561483 # average ReadReq mshr miss latency 829system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63246.686673 # average ReadReq mshr miss latency |
| 730system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 731system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 830system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 831system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| 732system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.614743 # average ReadExReq mshr miss latency 733system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.614743 # average ReadExReq mshr miss latency 734system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42297.664869 # average overall mshr miss latency 735system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55747.293776 # average overall mshr miss latency 736system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55679.018242 # average overall mshr miss latency 737system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42297.664869 # average overall mshr miss latency 738system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55747.293776 # average overall mshr miss latency 739system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55679.018242 # average overall mshr miss latency | 832system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56999.065456 # average ReadExReq mshr miss latency 833system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56999.065456 # average ReadExReq mshr miss latency 834system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58906.211308 # average overall mshr miss latency 835system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62395.325386 # average overall mshr miss latency 836system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62377.525508 # average overall mshr miss latency 837system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58906.211308 # average overall mshr miss latency 838system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62395.325386 # average overall mshr miss latency 839system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62377.525508 # average overall mshr miss latency |
| 740system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 840system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 741system.cpu.dcache.replacements 1533127 # number of replacements 742system.cpu.dcache.tagsinuse 4094.655328 # Cycle average of tags in use 743system.cpu.dcache.total_refs 969949757 # Total number of references to valid blocks. 744system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks. 745system.cpu.dcache.avg_refs 630.975309 # Average number of references to valid blocks. 746system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit. 747system.cpu.dcache.occ_blocks::cpu.data 4094.655328 # Average occupied blocks per requestor 748system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy 749system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy 750system.cpu.dcache.ReadReq_hits::cpu.data 693823143 # number of ReadReq hits 751system.cpu.dcache.ReadReq_hits::total 693823143 # number of ReadReq hits 752system.cpu.dcache.WriteReq_hits::cpu.data 276093651 # number of WriteReq hits 753system.cpu.dcache.WriteReq_hits::total 276093651 # number of WriteReq hits 754system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits 755system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits | 841system.cpu.dcache.replacements 1532821 # number of replacements 842system.cpu.dcache.tagsinuse 4094.414072 # Cycle average of tags in use 843system.cpu.dcache.total_refs 970116115 # Total number of references to valid blocks. 844system.cpu.dcache.sampled_refs 1536917 # Sample count of references to valid blocks. 845system.cpu.dcache.avg_refs 631.209177 # Average number of references to valid blocks. 846system.cpu.dcache.warmup_cycle 390600000 # Cycle when the warmup percentage was hit. 847system.cpu.dcache.occ_blocks::cpu.data 4094.414072 # Average occupied blocks per requestor 848system.cpu.dcache.occ_percent::cpu.data 0.999613 # Average percentage of cache occupancy 849system.cpu.dcache.occ_percent::total 0.999613 # Average percentage of cache occupancy 850system.cpu.dcache.ReadReq_hits::cpu.data 693989998 # number of ReadReq hits 851system.cpu.dcache.ReadReq_hits::total 693989998 # number of ReadReq hits 852system.cpu.dcache.WriteReq_hits::cpu.data 276093265 # number of WriteReq hits 853system.cpu.dcache.WriteReq_hits::total 276093265 # number of WriteReq hits 854system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits 855system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits |
| 756system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits 757system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits | 856system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits 857system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits |
| 758system.cpu.dcache.demand_hits::cpu.data 969916794 # number of demand (read+write) hits 759system.cpu.dcache.demand_hits::total 969916794 # number of demand (read+write) hits 760system.cpu.dcache.overall_hits::cpu.data 969916794 # number of overall hits 761system.cpu.dcache.overall_hits::total 969916794 # number of overall hits 762system.cpu.dcache.ReadReq_misses::cpu.data 1953499 # number of ReadReq misses 763system.cpu.dcache.ReadReq_misses::total 1953499 # number of ReadReq misses 764system.cpu.dcache.WriteReq_misses::cpu.data 842027 # number of WriteReq misses 765system.cpu.dcache.WriteReq_misses::total 842027 # number of WriteReq misses | 858system.cpu.dcache.demand_hits::cpu.data 970083263 # number of demand (read+write) hits 859system.cpu.dcache.demand_hits::total 970083263 # number of demand (read+write) hits 860system.cpu.dcache.overall_hits::cpu.data 970083263 # number of overall hits 861system.cpu.dcache.overall_hits::total 970083263 # number of overall hits 862system.cpu.dcache.ReadReq_misses::cpu.data 1953007 # number of ReadReq misses 863system.cpu.dcache.ReadReq_misses::total 1953007 # number of ReadReq misses 864system.cpu.dcache.WriteReq_misses::cpu.data 842413 # number of WriteReq misses 865system.cpu.dcache.WriteReq_misses::total 842413 # number of WriteReq misses |
| 766system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 767system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses | 866system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 867system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses |
| 768system.cpu.dcache.demand_misses::cpu.data 2795526 # number of demand (read+write) misses 769system.cpu.dcache.demand_misses::total 2795526 # number of demand (read+write) misses 770system.cpu.dcache.overall_misses::cpu.data 2795526 # number of overall misses 771system.cpu.dcache.overall_misses::total 2795526 # number of overall misses 772system.cpu.dcache.ReadReq_miss_latency::cpu.data 66742188500 # number of ReadReq miss cycles 773system.cpu.dcache.ReadReq_miss_latency::total 66742188500 # number of ReadReq miss cycles 774system.cpu.dcache.WriteReq_miss_latency::cpu.data 39429860969 # number of WriteReq miss cycles 775system.cpu.dcache.WriteReq_miss_latency::total 39429860969 # number of WriteReq miss cycles 776system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles 777system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles 778system.cpu.dcache.demand_miss_latency::cpu.data 106172049469 # number of demand (read+write) miss cycles 779system.cpu.dcache.demand_miss_latency::total 106172049469 # number of demand (read+write) miss cycles 780system.cpu.dcache.overall_miss_latency::cpu.data 106172049469 # number of overall miss cycles 781system.cpu.dcache.overall_miss_latency::total 106172049469 # number of overall miss cycles 782system.cpu.dcache.ReadReq_accesses::cpu.data 695776642 # number of ReadReq accesses(hits+misses) 783system.cpu.dcache.ReadReq_accesses::total 695776642 # number of ReadReq accesses(hits+misses) | 868system.cpu.dcache.demand_misses::cpu.data 2795420 # number of demand (read+write) misses 869system.cpu.dcache.demand_misses::total 2795420 # number of demand (read+write) misses 870system.cpu.dcache.overall_misses::cpu.data 2795420 # number of overall misses 871system.cpu.dcache.overall_misses::total 2795420 # number of overall misses 872system.cpu.dcache.ReadReq_miss_latency::cpu.data 79048557500 # number of ReadReq miss cycles 873system.cpu.dcache.ReadReq_miss_latency::total 79048557500 # number of ReadReq miss cycles 874system.cpu.dcache.WriteReq_miss_latency::cpu.data 56325650469 # number of WriteReq miss cycles 875system.cpu.dcache.WriteReq_miss_latency::total 56325650469 # number of WriteReq miss cycles 876system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 203500 # number of LoadLockedReq miss cycles 877system.cpu.dcache.LoadLockedReq_miss_latency::total 203500 # number of LoadLockedReq miss cycles 878system.cpu.dcache.demand_miss_latency::cpu.data 135374207969 # number of demand (read+write) miss cycles 879system.cpu.dcache.demand_miss_latency::total 135374207969 # number of demand (read+write) miss cycles 880system.cpu.dcache.overall_miss_latency::cpu.data 135374207969 # number of overall miss cycles 881system.cpu.dcache.overall_miss_latency::total 135374207969 # number of overall miss cycles 882system.cpu.dcache.ReadReq_accesses::cpu.data 695943005 # number of ReadReq accesses(hits+misses) 883system.cpu.dcache.ReadReq_accesses::total 695943005 # number of ReadReq accesses(hits+misses) |
| 784system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 785system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) | 884system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 885system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) |
| 786system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) 787system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) | 886system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) 887system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) |
| 788system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) 789system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) | 888system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) 889system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) |
| 790system.cpu.dcache.demand_accesses::cpu.data 972712320 # number of demand (read+write) accesses 791system.cpu.dcache.demand_accesses::total 972712320 # number of demand (read+write) accesses 792system.cpu.dcache.overall_accesses::cpu.data 972712320 # number of overall (read+write) accesses 793system.cpu.dcache.overall_accesses::total 972712320 # number of overall (read+write) accesses 794system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses 795system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses 796system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003041 # miss rate for WriteReq accesses 797system.cpu.dcache.WriteReq_miss_rate::total 0.003041 # miss rate for WriteReq accesses | 890system.cpu.dcache.demand_accesses::cpu.data 972878683 # number of demand (read+write) accesses 891system.cpu.dcache.demand_accesses::total 972878683 # number of demand (read+write) accesses 892system.cpu.dcache.overall_accesses::cpu.data 972878683 # number of overall (read+write) accesses 893system.cpu.dcache.overall_accesses::total 972878683 # number of overall (read+write) accesses 894system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002806 # miss rate for ReadReq accesses 895system.cpu.dcache.ReadReq_miss_rate::total 0.002806 # miss rate for ReadReq accesses 896system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses 897system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses |
| 798system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses 799system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses | 898system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses 899system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses |
| 800system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 # miss rate for demand accesses 801system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses 802system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses 803system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses 804system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34165.458237 # average ReadReq miss latency 805system.cpu.dcache.ReadReq_avg_miss_latency::total 34165.458237 # average ReadReq miss latency 806system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46827.311914 # average WriteReq miss latency 807system.cpu.dcache.WriteReq_avg_miss_latency::total 46827.311914 # average WriteReq miss latency 808system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency 809system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency 810system.cpu.dcache.demand_avg_miss_latency::cpu.data 37979.274551 # average overall miss latency 811system.cpu.dcache.demand_avg_miss_latency::total 37979.274551 # average overall miss latency 812system.cpu.dcache.overall_avg_miss_latency::cpu.data 37979.274551 # average overall miss latency 813system.cpu.dcache.overall_avg_miss_latency::total 37979.274551 # average overall miss latency 814system.cpu.dcache.blocked_cycles::no_mshrs 1535 # number of cycles access was blocked 815system.cpu.dcache.blocked_cycles::no_targets 741 # number of cycles access was blocked 816system.cpu.dcache.blocked::no_mshrs 54 # number of cycles access was blocked | 900system.cpu.dcache.demand_miss_rate::cpu.data 0.002873 # miss rate for demand accesses 901system.cpu.dcache.demand_miss_rate::total 0.002873 # miss rate for demand accesses 902system.cpu.dcache.overall_miss_rate::cpu.data 0.002873 # miss rate for overall accesses 903system.cpu.dcache.overall_miss_rate::total 0.002873 # miss rate for overall accesses 904system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40475.306796 # average ReadReq miss latency 905system.cpu.dcache.ReadReq_avg_miss_latency::total 40475.306796 # average ReadReq miss latency 906system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66862.275949 # average WriteReq miss latency 907system.cpu.dcache.WriteReq_avg_miss_latency::total 66862.275949 # average WriteReq miss latency 908system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67833.333333 # average LoadLockedReq miss latency 909system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67833.333333 # average LoadLockedReq miss latency 910system.cpu.dcache.demand_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency 911system.cpu.dcache.demand_avg_miss_latency::total 48427.144389 # average overall miss latency 912system.cpu.dcache.overall_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency 913system.cpu.dcache.overall_avg_miss_latency::total 48427.144389 # average overall miss latency 914system.cpu.dcache.blocked_cycles::no_mshrs 2558 # number of cycles access was blocked 915system.cpu.dcache.blocked_cycles::no_targets 879 # number of cycles access was blocked 916system.cpu.dcache.blocked::no_mshrs 58 # number of cycles access was blocked |
| 817system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked | 917system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked |
| 818system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.425926 # average number of cycles each access was blocked 819system.cpu.dcache.avg_blocked_cycles::no_targets 8.325843 # average number of cycles each access was blocked | 918system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.103448 # average number of cycles each access was blocked 919system.cpu.dcache.avg_blocked_cycles::no_targets 9.876404 # average number of cycles each access was blocked |
| 820system.cpu.dcache.fast_writes 0 # number of fast writes performed 821system.cpu.dcache.cache_copies 0 # number of cache copies performed | 920system.cpu.dcache.fast_writes 0 # number of fast writes performed 921system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 822system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks 823system.cpu.dcache.writebacks::total 96322 # number of writebacks 824system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488793 # number of ReadReq MSHR hits 825system.cpu.dcache.ReadReq_mshr_hits::total 488793 # number of ReadReq MSHR hits 826system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765175 # number of WriteReq MSHR hits 827system.cpu.dcache.WriteReq_mshr_hits::total 765175 # number of WriteReq MSHR hits | 922system.cpu.dcache.writebacks::writebacks 96335 # number of writebacks 923system.cpu.dcache.writebacks::total 96335 # number of writebacks 924system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488604 # number of ReadReq MSHR hits 925system.cpu.dcache.ReadReq_mshr_hits::total 488604 # number of ReadReq MSHR hits 926system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765599 # number of WriteReq MSHR hits 927system.cpu.dcache.WriteReq_mshr_hits::total 765599 # number of WriteReq MSHR hits |
| 828system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 829system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits | 928system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 929system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits |
| 830system.cpu.dcache.demand_mshr_hits::cpu.data 1253968 # number of demand (read+write) MSHR hits 831system.cpu.dcache.demand_mshr_hits::total 1253968 # number of demand (read+write) MSHR hits 832system.cpu.dcache.overall_mshr_hits::cpu.data 1253968 # number of overall MSHR hits 833system.cpu.dcache.overall_mshr_hits::total 1253968 # number of overall MSHR hits 834system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464706 # number of ReadReq MSHR misses 835system.cpu.dcache.ReadReq_mshr_misses::total 1464706 # number of ReadReq MSHR misses 836system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76852 # number of WriteReq MSHR misses 837system.cpu.dcache.WriteReq_mshr_misses::total 76852 # number of WriteReq MSHR misses 838system.cpu.dcache.demand_mshr_misses::cpu.data 1541558 # number of demand (read+write) MSHR misses 839system.cpu.dcache.demand_mshr_misses::total 1541558 # number of demand (read+write) MSHR misses 840system.cpu.dcache.overall_mshr_misses::cpu.data 1541558 # number of overall MSHR misses 841system.cpu.dcache.overall_mshr_misses::total 1541558 # number of overall MSHR misses 842system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41088591000 # number of ReadReq MSHR miss cycles 843system.cpu.dcache.ReadReq_mshr_miss_latency::total 41088591000 # number of ReadReq MSHR miss cycles 844system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3410048000 # number of WriteReq MSHR miss cycles 845system.cpu.dcache.WriteReq_mshr_miss_latency::total 3410048000 # number of WriteReq MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44498639000 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.demand_mshr_miss_latency::total 44498639000 # number of demand (read+write) MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44498639000 # number of overall MSHR miss cycles 849system.cpu.dcache.overall_mshr_miss_latency::total 44498639000 # number of overall MSHR miss cycles 850system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses 852system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses 854system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses 855system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses 856system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses 857system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses 858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28052.449434 # average ReadReq mshr miss latency 859system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28052.449434 # average ReadReq mshr miss latency 860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44371.623380 # average WriteReq mshr miss latency 861system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44371.623380 # average WriteReq mshr miss latency 862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency 863system.cpu.dcache.demand_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency 864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency 865system.cpu.dcache.overall_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency | 930system.cpu.dcache.demand_mshr_hits::cpu.data 1254203 # number of demand (read+write) MSHR hits 931system.cpu.dcache.demand_mshr_hits::total 1254203 # number of demand (read+write) MSHR hits 932system.cpu.dcache.overall_mshr_hits::cpu.data 1254203 # number of overall MSHR hits 933system.cpu.dcache.overall_mshr_hits::total 1254203 # number of overall MSHR hits 934system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464403 # number of ReadReq MSHR misses 935system.cpu.dcache.ReadReq_mshr_misses::total 1464403 # number of ReadReq MSHR misses 936system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses 937system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses 938system.cpu.dcache.demand_mshr_misses::cpu.data 1541217 # number of demand (read+write) MSHR misses 939system.cpu.dcache.demand_mshr_misses::total 1541217 # number of demand (read+write) MSHR misses 940system.cpu.dcache.overall_mshr_misses::cpu.data 1541217 # number of overall MSHR misses 941system.cpu.dcache.overall_mshr_misses::total 1541217 # number of overall MSHR misses 942system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42813858522 # number of ReadReq MSHR miss cycles 943system.cpu.dcache.ReadReq_mshr_miss_latency::total 42813858522 # number of ReadReq MSHR miss cycles 944system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4818359000 # number of WriteReq MSHR miss cycles 945system.cpu.dcache.WriteReq_mshr_miss_latency::total 4818359000 # number of WriteReq MSHR miss cycles 946system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47632217522 # number of demand (read+write) MSHR miss cycles 947system.cpu.dcache.demand_mshr_miss_latency::total 47632217522 # number of demand (read+write) MSHR miss cycles 948system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47632217522 # number of overall MSHR miss cycles 949system.cpu.dcache.overall_mshr_miss_latency::total 47632217522 # number of overall MSHR miss cycles 950system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses 951system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002104 # mshr miss rate for ReadReq accesses 952system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses 953system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses 954system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses 955system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses 956system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses 957system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses 958system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29236.390886 # average ReadReq mshr miss latency 959system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29236.390886 # average ReadReq mshr miss latency 960system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62727.614758 # average WriteReq mshr miss latency 961system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62727.614758 # average WriteReq mshr miss latency 962system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency 963system.cpu.dcache.demand_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency 964system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency 965system.cpu.dcache.overall_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency |
| 866system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 867 868---------- End Simulation Statistics ---------- | 966system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 967 968---------- End Simulation Statistics ---------- |