Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.627778 # Number of seconds simulated
4sim_ticks 627777658000 # Number of ticks simulated
5final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.627439 # Number of seconds simulated
4sim_ticks 627439125000 # Number of ticks simulated
5final_tick 627439125000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 109787 # Simulator instruction rate (inst/s)
8host_op_rate 149515 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 49785649 # Simulator tick rate (ticks/s)
10host_mem_usage 262368 # Number of bytes of host memory used
11host_seconds 12609.61 # Real time elapsed on the host

7host_inst_rate 96597 # Simulator instruction rate (inst/s)
8host_op_rate 131552 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 43780556 # Simulator tick rate (ticks/s)
10host_mem_usage 260984 # Number of bytes of host memory used
11host_seconds 14331.46 # Real time elapsed on the host

12sim_insts 1384370590 # Number of instructions simulated
13sim_ops 1885325342 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory
16system.physmem.bytes_read::total 30397824 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory

14system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 30242368 # Number of bytes read from this memory
16system.physmem.bytes_read::total 30397376 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory

19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
20system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory

21system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 474966 # Number of read requests responded to by this memory

21system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 472537 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 474959 # Number of read requests responded to by this memory

24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory

26system.physmem.bw_read::cpu.inst 246813 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 48174508 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 48421322 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 246813 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 246813 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 6738488 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 6738488 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 6738488 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 246813 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 48174508 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 474966 # Total number of read requests seen

26system.physmem.bw_read::cpu.inst 247049 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 48199685 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 48446733 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 247049 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 247049 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 6742123 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 6742123 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 6742123 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 247049 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 48199685 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 55188857 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 474959 # Total number of read requests seen

38system.physmem.writeReqs 66098 # Total number of write requests seen

39system.physmem.cpureqs 545372 # Reqs generatd by CPU via cache - shady
40system.physmem.bytesRead 30397824 # Total number of bytes read from memory

39system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady
40system.physmem.bytesRead 30397376 # Total number of bytes read from memory

41system.physmem.bytesWritten 4230272 # Total number of bytes written to memory

42system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize()

42system.physmem.bytesConsumedRd 30397376 # bytesRead derated as per pkt->getSize()

43system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()

44system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q
45system.physmem.neitherReadNorWrite 4308 # Reqs where no action is needed
46system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis

44system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q
45system.physmem.neitherReadNorWrite 4291 # Reqs where no action is needed
46system.physmem.perBankRdReqs::0 29712 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::1 29706 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::2 29691 # Track reads on a per bank basis

49system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis

50system.physmem.perBankRdReqs::4 29687 # Track reads on a per bank basis

50system.physmem.perBankRdReqs::4 29689 # Track reads on a per bank basis

51system.physmem.perBankRdReqs::5 29720 # Track reads on a per bank basis

52system.physmem.perBankRdReqs::6 29750 # Track reads on a per bank basis

52system.physmem.perBankRdReqs::6 29747 # Track reads on a per bank basis

53system.physmem.perBankRdReqs::7 29651 # Track reads on a per bank basis

54system.physmem.perBankRdReqs::8 29637 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::9 29680 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::10 29627 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::11 29600 # Track reads on a per bank basis

54system.physmem.perBankRdReqs::8 29640 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::9 29682 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::10 29629 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::11 29602 # Track reads on a per bank basis

58system.physmem.perBankRdReqs::12 29611 # Track reads on a per bank basis

59system.physmem.perBankRdReqs::13 29633 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::14 29689 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::15 29652 # Track reads on a per bank basis

59system.physmem.perBankRdReqs::13 29628 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::14 29687 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::15 29649 # Track reads on a per bank basis

62system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::3 4159 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::4 4130 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::5 4128 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::6 4130 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::7 4131 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::8 4119 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::9 4145 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::10 4136 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::11 4104 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::12 4108 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::13 4104 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::14 4133 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis
78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

80system.physmem.totGap 627777588500 # Total gap between requests

80system.physmem.totGap 627439056500 # Total gap between requests

81system.physmem.readPktSize::0 0 # Categorize read packet sizes
82system.physmem.readPktSize::1 0 # Categorize read packet sizes
83system.physmem.readPktSize::2 0 # Categorize read packet sizes
84system.physmem.readPktSize::3 0 # Categorize read packet sizes
85system.physmem.readPktSize::4 0 # Categorize read packet sizes
86system.physmem.readPktSize::5 0 # Categorize read packet sizes

87system.physmem.readPktSize::6 474966 # Categorize read packet sizes

87system.physmem.readPktSize::6 474959 # Categorize read packet sizes

88system.physmem.writePktSize::0 0 # Categorize write packet sizes
89system.physmem.writePktSize::1 0 # Categorize write packet sizes
90system.physmem.writePktSize::2 0 # Categorize write packet sizes
91system.physmem.writePktSize::3 0 # Categorize write packet sizes
92system.physmem.writePktSize::4 0 # Categorize write packet sizes
93system.physmem.writePktSize::5 0 # Categorize write packet sizes
94system.physmem.writePktSize::6 66098 # Categorize write packet sizes

95system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see

95system.physmem.rdQLenPdf::0 405906 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::1 66678 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::2 2122 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see

101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see

--- 42 unchanged lines hidden (view full) ---

151system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see

159system.physmem.totQLat 3182824500 # Total cycles spent in queuing delays
160system.physmem.totMemAccLat 21162788250 # Sum of mem lat for all requests
161system.physmem.totBusLat 2374030000 # Total cycles spent in databus access
162system.physmem.totBankLat 15605933750 # Total cycles spent in bank access
163system.physmem.avgQLat 6703.42 # Average queueing delay per request
164system.physmem.avgBankLat 32868.02 # Average bank access latency per request

159system.physmem.totQLat 3462811500 # Total cycles spent in queuing delays
160system.physmem.totMemAccLat 21441489000 # Sum of mem lat for all requests
161system.physmem.totBusLat 2374050000 # Total cycles spent in databus access
162system.physmem.totBankLat 15604627500 # Total cycles spent in bank access
163system.physmem.avgQLat 7293.05 # Average queueing delay per request
164system.physmem.avgBankLat 32864.99 # Average bank access latency per request

165system.physmem.avgBusLat 5000.00 # Average bus latency per request

166system.physmem.avgMemAccLat 44571.44 # Average memory access latency
167system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s

166system.physmem.avgMemAccLat 45158.04 # Average memory access latency
167system.physmem.avgRdBW 48.45 # Average achieved read bandwidth in MB/s

168system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s

169system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s

169system.physmem.avgConsumedRdBW 48.45 # Average consumed read bandwidth in MB/s

170system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s
171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
172system.physmem.busUtil 0.43 # Data bus utilization in percentage
173system.physmem.avgRdQLen 0.03 # Average read queue length over time
174system.physmem.avgWrQLen 17.42 # Average write queue length over time

175system.physmem.readRowHits 143321 # Number of row buffer hits during reads
176system.physmem.writeRowHits 45521 # Number of row buffer hits during writes

175system.physmem.readRowHits 143341 # Number of row buffer hits during reads
176system.physmem.writeRowHits 45511 # Number of row buffer hits during writes

177system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads

178system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes
179system.physmem.avgGap 1160264.94 # Average gap between requests
180system.cpu.branchPred.lookups 438315942 # Number of BP lookups
181system.cpu.branchPred.condPredicted 349727890 # Number of conditional branches predicted
182system.cpu.branchPred.condIncorrect 30635219 # Number of conditional branches incorrect
183system.cpu.branchPred.BTBLookups 247833723 # Number of BTB lookups
184system.cpu.branchPred.BTBHits 226959266 # Number of BTB hits

178system.physmem.writeRowHitRate 68.85 # Row buffer hit rate for writes
179system.physmem.avgGap 1159654.26 # Average gap between requests
180system.cpu.branchPred.lookups 440649573 # Number of BP lookups
181system.cpu.branchPred.condPredicted 353682166 # Number of conditional branches predicted
182system.cpu.branchPred.condIncorrect 30631043 # Number of conditional branches incorrect
183system.cpu.branchPred.BTBLookups 252533039 # Number of BTB lookups
184system.cpu.branchPred.BTBHits 230279415 # Number of BTB hits

185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

186system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage
187system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target.
188system.cpu.branchPred.RASInCorrect 2806740 # Number of incorrect RAS predictions.

186system.cpu.branchPred.BTBHitPct 91.187837 # BTB Hit Percentage
187system.cpu.branchPred.usedRAS 51764959 # Number of times the RAS was used to get a target.
188system.cpu.branchPred.RASInCorrect 2806562 # Number of incorrect RAS predictions.

189system.cpu.dtb.inst_hits 0 # ITB inst hits
190system.cpu.dtb.inst_misses 0 # ITB inst misses
191system.cpu.dtb.read_hits 0 # DTB read hits
192system.cpu.dtb.read_misses 0 # DTB read misses
193system.cpu.dtb.write_hits 0 # DTB write hits
194system.cpu.dtb.write_misses 0 # DTB write misses
195system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
196system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 27 unchanged lines hidden (view full) ---

224system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
225system.cpu.itb.read_accesses 0 # DTB read accesses
226system.cpu.itb.write_accesses 0 # DTB write accesses
227system.cpu.itb.inst_accesses 0 # ITB inst accesses
228system.cpu.itb.hits 0 # DTB hits
229system.cpu.itb.misses 0 # DTB misses
230system.cpu.itb.accesses 0 # DTB accesses
231system.cpu.workload.num_syscalls 1411 # Number of system calls

232system.cpu.numCycles 1255555317 # number of cpu cycles simulated

232system.cpu.numCycles 1254878251 # number of cpu cycles simulated

233system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
234system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

235system.cpu.fetch.icacheStallCycles 353470076 # Number of cycles fetch is stalled on an Icache miss
236system.cpu.fetch.Insts 2285596018 # Number of instructions fetch has processed
237system.cpu.fetch.Branches 438315942 # Number of branches that fetch encountered
238system.cpu.fetch.predictedBranches 279264180 # Number of branches that fetch has predicted taken
239system.cpu.fetch.Cycles 600835401 # Number of cycles fetch has run and was not squashing or blocked
240system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing
241system.cpu.fetch.BlockedCycles 132517239 # Number of cycles fetch has spent blocked
242system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
243system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps
244system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR
245system.cpu.fetch.CacheLines 333121635 # Number of cache lines fetched
246system.cpu.fetch.IcacheSquashes 10719821 # Number of outstanding Icache misses that were squashed
247system.cpu.fetch.rateDist::samples 1213961612 # Number of instructions fetched each cycle (Total)
248system.cpu.fetch.rateDist::mean 2.592462 # Number of instructions fetched each cycle (Total)
249system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total)

235system.cpu.fetch.icacheStallCycles 354654463 # Number of cycles fetch is stalled on an Icache miss
236system.cpu.fetch.Insts 2286055838 # Number of instructions fetch has processed
237system.cpu.fetch.Branches 440649573 # Number of branches that fetch encountered
238system.cpu.fetch.predictedBranches 282044374 # Number of branches that fetch has predicted taken
239system.cpu.fetch.Cycles 601927539 # Number of cycles fetch has run and was not squashing or blocked
240system.cpu.fetch.SquashCycles 156613440 # Number of cycles fetch has spent squashing
241system.cpu.fetch.BlockedCycles 130193180 # Number of cycles fetch has spent blocked
242system.cpu.fetch.MiscStallCycles 518 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
243system.cpu.fetch.PendingTrapStallCycles 10572 # Number of stall cycles due to pending traps
244system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR
245system.cpu.fetch.CacheLines 335557697 # Number of cache lines fetched
246system.cpu.fetch.IcacheSquashes 11970074 # Number of outstanding Icache misses that were squashed
247system.cpu.fetch.rateDist::samples 1212716808 # Number of instructions fetched each cycle (Total)
248system.cpu.fetch.rateDist::mean 2.588686 # Number of instructions fetched each cycle (Total)
249system.cpu.fetch.rateDist::stdev 3.181757 # Number of instructions fetched each cycle (Total)

250system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

251system.cpu.fetch.rateDist::0 613170569 50.51% 50.51% # Number of instructions fetched each cycle (Total)
252system.cpu.fetch.rateDist::1 42771992 3.52% 54.03% # Number of instructions fetched each cycle (Total)
253system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total)
254system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total)
255system.cpu.fetch.rateDist::4 71974346 5.93% 72.42% # Number of instructions fetched each cycle (Total)
256system.cpu.fetch.rateDist::5 42167023 3.47% 75.89% # Number of instructions fetched each cycle (Total)
257system.cpu.fetch.rateDist::6 30997748 2.55% 78.45% # Number of instructions fetched each cycle (Total)
258system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total)
259system.cpu.fetch.rateDist::8 230060886 18.95% 100.00% # Number of instructions fetched each cycle (Total)

251system.cpu.fetch.rateDist::0 610833811 50.37% 50.37% # Number of instructions fetched each cycle (Total)
252system.cpu.fetch.rateDist::1 43093126 3.55% 53.92% # Number of instructions fetched each cycle (Total)
253system.cpu.fetch.rateDist::2 96161904 7.93% 61.85% # Number of instructions fetched each cycle (Total)
254system.cpu.fetch.rateDist::3 57061464 4.71% 66.56% # Number of instructions fetched each cycle (Total)
255system.cpu.fetch.rateDist::4 71748155 5.92% 72.47% # Number of instructions fetched each cycle (Total)
256system.cpu.fetch.rateDist::5 43390011 3.58% 76.05% # Number of instructions fetched each cycle (Total)
257system.cpu.fetch.rateDist::6 30893705 2.55% 78.60% # Number of instructions fetched each cycle (Total)
258system.cpu.fetch.rateDist::7 32839857 2.71% 81.31% # Number of instructions fetched each cycle (Total)
259system.cpu.fetch.rateDist::8 226694775 18.69% 100.00% # Number of instructions fetched each cycle (Total)

260system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
261system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
262system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

263system.cpu.fetch.rateDist::total 1213961612 # Number of instructions fetched each cycle (Total)
264system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle
265system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle
266system.cpu.decode.IdleCycles 402973570 # Number of cycles decode is idle
267system.cpu.decode.BlockedCycles 105164432 # Number of cycles decode is blocked
268system.cpu.decode.RunCycles 561876513 # Number of cycles decode is running
269system.cpu.decode.UnblockCycles 16833922 # Number of cycles decode is unblocking
270system.cpu.decode.SquashCycles 127113175 # Number of cycles decode is squashing
271system.cpu.decode.BranchResolved 44705454 # Number of times decode resolved a branch
272system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction
273system.cpu.decode.DecodedInsts 3047243320 # Number of instructions handled by decode
274system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode
275system.cpu.rename.SquashCycles 127113175 # Number of cycles rename is squashing
276system.cpu.rename.IdleCycles 438520828 # Number of cycles rename is idle
277system.cpu.rename.BlockCycles 34437480 # Number of cycles rename is blocking
278system.cpu.rename.serializeStallCycles 439400 # count of cycles rename stalled for serializing inst
279system.cpu.rename.RunCycles 541081761 # Number of cycles rename is running
280system.cpu.rename.UnblockCycles 72368968 # Number of cycles rename is unblocking
281system.cpu.rename.RenamedInsts 2975054899 # Number of instructions processed by rename
282system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full
283system.cpu.rename.IQFullEvents 4810930 # Number of times rename has blocked due to IQ full
284system.cpu.rename.LSQFullEvents 57090211 # Number of times rename has blocked due to LSQ full

263system.cpu.fetch.rateDist::total 1212716808 # Number of instructions fetched each cycle (Total)
264system.cpu.fetch.branchRate 0.351149 # Number of branch fetches per cycle
265system.cpu.fetch.rate 1.821735 # Number of inst fetches per cycle
266system.cpu.decode.IdleCycles 405646781 # Number of cycles decode is idle
267system.cpu.decode.BlockedCycles 102637713 # Number of cycles decode is blocked
268system.cpu.decode.RunCycles 561793047 # Number of cycles decode is running
269system.cpu.decode.UnblockCycles 16722466 # Number of cycles decode is unblocking
270system.cpu.decode.SquashCycles 125916801 # Number of cycles decode is squashing
271system.cpu.decode.BranchResolved 44665335 # Number of times decode resolved a branch
272system.cpu.decode.BranchMispred 13931 # Number of times decode detected a branch misprediction
273system.cpu.decode.DecodedInsts 3029413956 # Number of instructions handled by decode
274system.cpu.decode.SquashedInsts 28108 # Number of squashed instructions handled by decode
275system.cpu.rename.SquashCycles 125916801 # Number of cycles rename is squashing
276system.cpu.rename.IdleCycles 441580002 # Number of cycles rename is idle
277system.cpu.rename.BlockCycles 34476908 # Number of cycles rename is blocking
278system.cpu.rename.serializeStallCycles 437379 # count of cycles rename stalled for serializing inst
279system.cpu.rename.RunCycles 540507560 # Number of cycles rename is running
280system.cpu.rename.UnblockCycles 69798158 # Number of cycles rename is unblocking
281system.cpu.rename.RenamedInsts 2946364126 # Number of instructions processed by rename
282system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full
283system.cpu.rename.IQFullEvents 4812832 # Number of times rename has blocked due to IQ full
284system.cpu.rename.LSQFullEvents 54672934 # Number of times rename has blocked due to LSQ full

285system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers

286system.cpu.rename.RenamedOperands 2946030115 # Number of destination operands rename has renamed
287system.cpu.rename.RenameLookups 14164064845 # Number of register rename lookups that rename has made
288system.cpu.rename.int_rename_lookups 13593631976 # Number of integer rename lookups
289system.cpu.rename.fp_rename_lookups 570432869 # Number of floating rename lookups

286system.cpu.rename.RenamedOperands 2931066413 # Number of destination operands rename has renamed
287system.cpu.rename.RenameLookups 14023290204 # Number of register rename lookups that rename has made
288system.cpu.rename.int_rename_lookups 13452684524 # Number of integer rename lookups
289system.cpu.rename.fp_rename_lookups 570605680 # Number of floating rename lookups

290system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed

291system.cpu.rename.UndoneMaps 952890025 # Number of HB maps that are undone due to squashing
292system.cpu.rename.serializingInsts 25236 # count of serializing insts renamed
293system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed
294system.cpu.rename.skidInsts 195466614 # count of insts added to the skid buffer
295system.cpu.memDep0.insertedLoads 973207403 # Number of loads inserted to the mem dependence unit.
296system.cpu.memDep0.insertedStores 490834559 # Number of stores inserted to the mem dependence unit.
297system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads.
298system.cpu.memDep0.conflictingStores 40613980 # Number of conflicting stores.
299system.cpu.iq.iqInstsAdded 2806590515 # Number of instructions added to the IQ (excludes non-spec)
300system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ
301system.cpu.iq.iqInstsIssued 2437414876 # Number of instructions issued
302system.cpu.iq.iqSquashedInstsIssued 13391013 # Number of squashed instructions issued
303system.cpu.iq.iqSquashedInstsExamined 908731819 # Number of squashed instructions iterated over during squash; mainly for profiling
304system.cpu.iq.iqSquashedOperandsExamined 2361150824 # Number of squashed operands that are examined and possibly removed from graph
305system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed
306system.cpu.iq.issued_per_cycle::samples 1213961612 # Number of insts issued each cycle
307system.cpu.iq.issued_per_cycle::mean 2.007819 # Number of insts issued each cycle
308system.cpu.iq.issued_per_cycle::stdev 1.875089 # Number of insts issued each cycle

291system.cpu.rename.UndoneMaps 937926323 # Number of HB maps that are undone due to squashing
292system.cpu.rename.serializingInsts 22415 # count of serializing insts renamed
293system.cpu.rename.tempSerializingInsts 19926 # count of temporary serializing insts renamed
294system.cpu.rename.skidInsts 179121288 # count of insts added to the skid buffer
295system.cpu.memDep0.insertedLoads 970649993 # Number of loads inserted to the mem dependence unit.
296system.cpu.memDep0.insertedStores 487168712 # Number of stores inserted to the mem dependence unit.
297system.cpu.memDep0.conflictingLoads 36377618 # Number of conflicting loads.
298system.cpu.memDep0.conflictingStores 40069949 # Number of conflicting stores.
299system.cpu.iq.iqInstsAdded 2792240287 # Number of instructions added to the IQ (excludes non-spec)
300system.cpu.iq.iqNonSpecInstsAdded 29328 # Number of non-speculative instructions added to the IQ
301system.cpu.iq.iqInstsIssued 2432835777 # Number of instructions issued
302system.cpu.iq.iqSquashedInstsIssued 13263841 # Number of squashed instructions issued
303system.cpu.iq.iqSquashedInstsExamined 894381457 # Number of squashed instructions iterated over during squash; mainly for profiling
304system.cpu.iq.iqSquashedOperandsExamined 2312630775 # Number of squashed operands that are examined and possibly removed from graph
305system.cpu.iq.iqSquashedNonSpecRemoved 7944 # Number of squashed non-spec instructions that were removed
306system.cpu.iq.issued_per_cycle::samples 1212716808 # Number of insts issued each cycle
307system.cpu.iq.issued_per_cycle::mean 2.006104 # Number of insts issued each cycle
308system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle

309system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

310system.cpu.iq.issued_per_cycle::0 377942739 31.13% 31.13% # Number of insts issued each cycle
311system.cpu.iq.issued_per_cycle::1 183591536 15.12% 46.26% # Number of insts issued each cycle
312system.cpu.iq.issued_per_cycle::2 202672014 16.70% 62.95% # Number of insts issued each cycle
313system.cpu.iq.issued_per_cycle::3 169721523 13.98% 76.93% # Number of insts issued each cycle
314system.cpu.iq.issued_per_cycle::4 132842970 10.94% 87.88% # Number of insts issued each cycle
315system.cpu.iq.issued_per_cycle::5 93759245 7.72% 95.60% # Number of insts issued each cycle
316system.cpu.iq.issued_per_cycle::6 37926008 3.12% 98.72% # Number of insts issued each cycle
317system.cpu.iq.issued_per_cycle::7 12454026 1.03% 99.75% # Number of insts issued each cycle
318system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle

310system.cpu.iq.issued_per_cycle::0 376728714 31.06% 31.06% # Number of insts issued each cycle
311system.cpu.iq.issued_per_cycle::1 183811265 15.16% 46.22% # Number of insts issued each cycle
312system.cpu.iq.issued_per_cycle::2 203907049 16.81% 63.04% # Number of insts issued each cycle
313system.cpu.iq.issued_per_cycle::3 169580498 13.98% 77.02% # Number of insts issued each cycle
314system.cpu.iq.issued_per_cycle::4 132860198 10.96% 87.98% # Number of insts issued each cycle
315system.cpu.iq.issued_per_cycle::5 92416507 7.62% 95.60% # Number of insts issued each cycle
316system.cpu.iq.issued_per_cycle::6 37964146 3.13% 98.73% # Number of insts issued each cycle
317system.cpu.iq.issued_per_cycle::7 12426731 1.02% 99.75% # Number of insts issued each cycle
318system.cpu.iq.issued_per_cycle::8 3021700 0.25% 100.00% # Number of insts issued each cycle

319system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
320system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
321system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

322system.cpu.iq.issued_per_cycle::total 1213961612 # Number of insts issued each cycle

322system.cpu.iq.issued_per_cycle::total 1212716808 # Number of insts issued each cycle

323system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

324system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available
325system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available

324system.cpu.iq.fu_full::IntAlu 716116 0.82% 0.82% # attempts to use FU when none available
325system.cpu.iq.fu_full::IntMult 24381 0.03% 0.85% # attempts to use FU when none available

326system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available
327system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available
328system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available
329system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available
330system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available
331system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available
332system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
333system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available

--- 11 unchanged lines hidden (view full) ---

345system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available
346system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available
347system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available
348system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available
349system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available
350system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available
351system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available
352system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available

353system.cpu.iq.fu_full::MemRead 55152382 62.89% 63.74% # attempts to use FU when none available
354system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available

353system.cpu.iq.fu_full::MemRead 55122687 62.92% 63.76% # attempts to use FU when none available
354system.cpu.iq.fu_full::MemWrite 31746374 36.24% 100.00% # attempts to use FU when none available

355system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
356system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
357system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

358system.cpu.iq.FU_type_0::IntAlu 1108357154 45.47% 45.47% # Type of FU issued
359system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued
360system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued
361system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued
362system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.93% # Type of FU issued
363system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.93% # Type of FU issued
364system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.93% # Type of FU issued
365system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.93% # Type of FU issued
366system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.93% # Type of FU issued
367system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.93% # Type of FU issued
368system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.93% # Type of FU issued
369system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.93% # Type of FU issued
370system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.93% # Type of FU issued
371system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.93% # Type of FU issued
372system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.93% # Type of FU issued
373system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.93% # Type of FU issued
374system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.93% # Type of FU issued
375system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.93% # Type of FU issued
376system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.93% # Type of FU issued
377system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Type of FU issued
378system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued
379system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued
380system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued
381system.cpu.iq.FU_type_0::SimdFloatCvt 5502588 0.23% 46.50% # Type of FU issued
382system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued
383system.cpu.iq.FU_type_0::SimdFloatMisc 23405386 0.96% 47.46% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
387system.cpu.iq.FU_type_0::MemRead 838249094 34.39% 81.85% # Type of FU issued
388system.cpu.iq.FU_type_0::MemWrite 442425361 18.15% 100.00% # Type of FU issued

358system.cpu.iq.FU_type_0::IntAlu 1103971506 45.38% 45.38% # Type of FU issued
359system.cpu.iq.FU_type_0::IntMult 11223452 0.46% 45.84% # Type of FU issued
360system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued
361system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.84% # Type of FU issued
362system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued
363system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued
364system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued
365system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued
366system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued
367system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued
368system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued
369system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued
370system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued
371system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued
372system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued
373system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued
374system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued
375system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued
376system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued
377system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued
378system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued
379system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued
380system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued
381system.cpu.iq.FU_type_0::SimdFloatCvt 5502427 0.23% 46.40% # Type of FU issued
382system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued
383system.cpu.iq.FU_type_0::SimdFloatMisc 23409752 0.96% 47.37% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued
387system.cpu.iq.FU_type_0::MemRead 838269607 34.46% 81.82% # Type of FU issued
388system.cpu.iq.FU_type_0::MemWrite 442207267 18.18% 100.00% # Type of FU issued

389system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
390system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

391system.cpu.iq.FU_type_0::total 2437414876 # Type of FU issued
392system.cpu.iq.rate 1.941304 # Inst issue rate
393system.cpu.iq.fu_busy_cnt 87694306 # FU busy when requested
394system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst)
395system.cpu.iq.int_inst_queue_reads 6067362312 # Number of integer instruction queue reads
396system.cpu.iq.int_inst_queue_writes 3632711697 # Number of integer instruction queue writes
397system.cpu.iq.int_inst_queue_wakeup_accesses 2254358254 # Number of integer instruction queue wakeup accesses
398system.cpu.iq.fp_inst_queue_reads 122514371 # Number of floating instruction queue reads
399system.cpu.iq.fp_inst_queue_writes 82707334 # Number of floating instruction queue writes
400system.cpu.iq.fp_inst_queue_wakeup_accesses 56439819 # Number of floating instruction queue wakeup accesses
401system.cpu.iq.int_alu_accesses 2461788341 # Number of integer alu accesses
402system.cpu.iq.fp_alu_accesses 63320841 # Number of floating point alu accesses
403system.cpu.iew.lsq.thread0.forwLoads 84306513 # Number of loads that had data forwarded from stores

391system.cpu.iq.FU_type_0::total 2432835777 # Type of FU issued
392system.cpu.iq.rate 1.938703 # Inst issue rate
393system.cpu.iq.fu_busy_cnt 87609558 # FU busy when requested
394system.cpu.iq.fu_busy_rate 0.036011 # FU busy rate (busy events/executed inst)
395system.cpu.iq.int_inst_queue_reads 6056740662 # Number of integer instruction queue reads
396system.cpu.iq.int_inst_queue_writes 3603968769 # Number of integer instruction queue writes
397system.cpu.iq.int_inst_queue_wakeup_accesses 2248867979 # Number of integer instruction queue wakeup accesses
398system.cpu.iq.fp_inst_queue_reads 122521099 # Number of floating instruction queue reads
399system.cpu.iq.fp_inst_queue_writes 82749412 # Number of floating instruction queue writes
400system.cpu.iq.fp_inst_queue_wakeup_accesses 56444030 # Number of floating instruction queue wakeup accesses
401system.cpu.iq.int_alu_accesses 2457121441 # Number of integer alu accesses
402system.cpu.iq.fp_alu_accesses 63323894 # Number of floating point alu accesses
403system.cpu.iew.lsq.thread0.forwLoads 84335781 # Number of loads that had data forwarded from stores

404system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

405system.cpu.iew.lsq.thread0.squashedLoads 341820222 # Number of loads squashed
406system.cpu.iew.lsq.thread0.ignoredResponses 8583 # Number of memory responses ignored because the instruction is squashed
407system.cpu.iew.lsq.thread0.memOrderViolation 1429956 # Number of memory ordering violations
408system.cpu.iew.lsq.thread0.squashedStores 213839262 # Number of stores squashed

405system.cpu.iew.lsq.thread0.squashedLoads 339262812 # Number of loads squashed
406system.cpu.iew.lsq.thread0.ignoredResponses 8485 # Number of memory responses ignored because the instruction is squashed
407system.cpu.iew.lsq.thread0.memOrderViolation 1431215 # Number of memory ordering violations
408system.cpu.iew.lsq.thread0.squashedStores 210173415 # Number of stores squashed

409system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
410system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
411system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled

412system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked

412system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked

413system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

414system.cpu.iew.iewSquashCycles 127113175 # Number of cycles IEW is squashing
415system.cpu.iew.iewBlockCycles 12638633 # Number of cycles IEW is blocking
416system.cpu.iew.iewUnblockCycles 1558332 # Number of cycles IEW is unblocking
417system.cpu.iew.iewDispatchedInsts 2806632387 # Number of instructions dispatched to IQ
418system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch
419system.cpu.iew.iewDispLoadInsts 973207403 # Number of dispatched load instructions
420system.cpu.iew.iewDispStoreInsts 490834559 # Number of dispatched store instructions
421system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions
422system.cpu.iew.iewIQFullEvents 1554341 # Number of times the IQ has become full, causing a stall

414system.cpu.iew.iewSquashCycles 125916801 # Number of cycles IEW is squashing
415system.cpu.iew.iewBlockCycles 12646480 # Number of cycles IEW is blocking
416system.cpu.iew.iewUnblockCycles 1559895 # Number of cycles IEW is unblocking
417system.cpu.iew.iewDispatchedInsts 2792282007 # Number of instructions dispatched to IQ
418system.cpu.iew.iewDispSquashedInsts 1384453 # Number of squashed instructions skipped by dispatch
419system.cpu.iew.iewDispLoadInsts 970649993 # Number of dispatched load instructions
420system.cpu.iew.iewDispStoreInsts 487168712 # Number of dispatched store instructions
421system.cpu.iew.iewDispNonSpecInsts 19342 # Number of dispatched non-speculative instructions
422system.cpu.iew.iewIQFullEvents 1555909 # Number of times the IQ has become full, causing a stall

423system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall

424system.cpu.iew.memOrderViolationEvents 1429956 # Number of memory order violations
425system.cpu.iew.predictedTakenIncorrect 32461974 # Number of branches that were predicted taken incorrectly
426system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly
427system.cpu.iew.branchMispredicts 33956380 # Number of branch mispredicts detected at execute
428system.cpu.iew.iewExecutedInsts 2363518752 # Number of executed instructions
429system.cpu.iew.iewExecLoadInsts 792548156 # Number of load instructions executed
430system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute

424system.cpu.iew.memOrderViolationEvents 1431215 # Number of memory order violations
425system.cpu.iew.predictedTakenIncorrect 32433063 # Number of branches that were predicted taken incorrectly
426system.cpu.iew.predictedNotTakenIncorrect 1530059 # Number of branches that were predicted not taken incorrectly
427system.cpu.iew.branchMispredicts 33963122 # Number of branch mispredicts detected at execute
428system.cpu.iew.iewExecutedInsts 2358070725 # Number of executed instructions
429system.cpu.iew.iewExecLoadInsts 792574818 # Number of load instructions executed
430system.cpu.iew.iewExecSquashedInsts 74765052 # Number of squashed instructions skipped in execute

431system.cpu.iew.exec_swp 0 # number of swp insts executed

432system.cpu.iew.exec_nop 12468 # number of nop insts executed
433system.cpu.iew.exec_refs 1216269086 # number of memory reference insts executed
434system.cpu.iew.exec_branches 322574286 # Number of branches executed
435system.cpu.iew.exec_stores 423720930 # Number of stores executed
436system.cpu.iew.exec_rate 1.882449 # Inst execution rate
437system.cpu.iew.wb_sent 2336489228 # cumulative count of insts sent to commit
438system.cpu.iew.wb_count 2310798073 # cumulative count of insts written-back
439system.cpu.iew.wb_producers 1347631579 # num instructions producing a value
440system.cpu.iew.wb_consumers 2523967689 # num instructions consuming a value

432system.cpu.iew.exec_nop 12392 # number of nop insts executed
433system.cpu.iew.exec_refs 1216182478 # number of memory reference insts executed
434system.cpu.iew.exec_branches 319878188 # Number of branches executed
435system.cpu.iew.exec_stores 423607660 # Number of stores executed
436system.cpu.iew.exec_rate 1.879123 # Inst execution rate
437system.cpu.iew.wb_sent 2331089515 # cumulative count of insts sent to commit
438system.cpu.iew.wb_count 2305312009 # cumulative count of insts written-back
439system.cpu.iew.wb_producers 1347373640 # num instructions producing a value
440system.cpu.iew.wb_consumers 2522763992 # num instructions consuming a value

441system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

442system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle
443system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back

442system.cpu.iew.wb_rate 1.837080 # insts written-back per cycle
443system.cpu.iew.wb_fanout 0.534086 # average fanout of values written-back

444system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

445system.cpu.commit.commitSquashedInsts 921296175 # The number of squashed insts skipped by commit

445system.cpu.commit.commitSquashedInsts 906945779 # The number of squashed insts skipped by commit

446system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards

447system.cpu.commit.branchMispredicts 30621418 # The number of times a branch was mispredicted
448system.cpu.commit.committed_per_cycle::samples 1086848437 # Number of insts commited each cycle
449system.cpu.commit.committed_per_cycle::mean 1.734682 # Number of insts commited each cycle
450system.cpu.commit.committed_per_cycle::stdev 2.398805 # Number of insts commited each cycle

447system.cpu.commit.branchMispredicts 30617374 # The number of times a branch was mispredicted
448system.cpu.commit.committed_per_cycle::samples 1086800007 # Number of insts commited each cycle
449system.cpu.commit.committed_per_cycle::mean 1.734759 # Number of insts commited each cycle
450system.cpu.commit.committed_per_cycle::stdev 2.398832 # Number of insts commited each cycle

451system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

452system.cpu.commit.committed_per_cycle::0 446548721 41.09% 41.09% # Number of insts commited each cycle
453system.cpu.commit.committed_per_cycle::1 288590719 26.55% 67.64% # Number of insts commited each cycle
454system.cpu.commit.committed_per_cycle::2 95114953 8.75% 76.39% # Number of insts commited each cycle
455system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle
456system.cpu.commit.committed_per_cycle::4 46461870 4.27% 87.13% # Number of insts commited each cycle
457system.cpu.commit.committed_per_cycle::5 22187798 2.04% 89.17% # Number of insts commited each cycle
458system.cpu.commit.committed_per_cycle::6 15847039 1.46% 90.63% # Number of insts commited each cycle
459system.cpu.commit.committed_per_cycle::7 10983692 1.01% 91.64% # Number of insts commited each cycle
460system.cpu.commit.committed_per_cycle::8 90884050 8.36% 100.00% # Number of insts commited each cycle

452system.cpu.commit.committed_per_cycle::0 446471329 41.08% 41.08% # Number of insts commited each cycle
453system.cpu.commit.committed_per_cycle::1 288644992 26.56% 67.64% # Number of insts commited each cycle
454system.cpu.commit.committed_per_cycle::2 95109223 8.75% 76.39% # Number of insts commited each cycle
455system.cpu.commit.committed_per_cycle::3 70211025 6.46% 82.85% # Number of insts commited each cycle
456system.cpu.commit.committed_per_cycle::4 46444999 4.27% 87.13% # Number of insts commited each cycle
457system.cpu.commit.committed_per_cycle::5 22203598 2.04% 89.17% # Number of insts commited each cycle
458system.cpu.commit.committed_per_cycle::6 15846659 1.46% 90.63% # Number of insts commited each cycle
459system.cpu.commit.committed_per_cycle::7 10983551 1.01% 91.64% # Number of insts commited each cycle
460system.cpu.commit.committed_per_cycle::8 90884631 8.36% 100.00% # Number of insts commited each cycle

461system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
462system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
463system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

464system.cpu.commit.committed_per_cycle::total 1086848437 # Number of insts commited each cycle

464system.cpu.commit.committed_per_cycle::total 1086800007 # Number of insts commited each cycle

465system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
466system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
467system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
468system.cpu.commit.refs 908382478 # Number of memory references committed
469system.cpu.commit.loads 631387181 # Number of loads committed
470system.cpu.commit.membars 9986 # Number of memory barriers committed

471system.cpu.commit.branches 299634395 # Number of branches committed

471system.cpu.commit.branches 298259106 # Number of branches committed

472system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
473system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
474system.cpu.commit.function_calls 41577833 # Number of function calls committed.

475system.cpu.commit.bw_lim_events 90884050 # number cycles where commit BW limit reached

475system.cpu.commit.bw_lim_events 90884631 # number cycles where commit BW limit reached

476system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

477system.cpu.rob.rob_reads 3802578575 # The number of ROB reads
478system.cpu.rob.rob_writes 5740389473 # The number of ROB writes
479system.cpu.timesIdled 353174 # Number of times that the entire CPU went into an idle state and unscheduled itself
480system.cpu.idleCycles 41593705 # Total number of cycles that the CPU has spent unscheduled due to idling

477system.cpu.rob.rob_reads 3788179168 # The number of ROB reads
478system.cpu.rob.rob_writes 5710492063 # The number of ROB writes
479system.cpu.timesIdled 353297 # Number of times that the entire CPU went into an idle state and unscheduled itself
480system.cpu.idleCycles 42161443 # Total number of cycles that the CPU has spent unscheduled due to idling

481system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
482system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
483system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated

484system.cpu.cpi 0.906950 # CPI: Cycles Per Instruction
485system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads
486system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle
487system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads
488system.cpu.int_regfile_reads 11774707263 # number of integer regfile reads
489system.cpu.int_regfile_writes 2226782267 # number of integer regfile writes
490system.cpu.fp_regfile_reads 68797357 # number of floating regfile reads
491system.cpu.fp_regfile_writes 49551943 # number of floating regfile writes
492system.cpu.misc_regfile_reads 1364040345 # number of misc regfile reads

484system.cpu.cpi 0.906461 # CPI: Cycles Per Instruction
485system.cpu.cpi_total 0.906461 # CPI: Total CPI of All Threads
486system.cpu.ipc 1.103191 # IPC: Instructions Per Cycle
487system.cpu.ipc_total 1.103191 # IPC: Total IPC of All Threads
488system.cpu.int_regfile_reads 11756795674 # number of integer regfile reads
489system.cpu.int_regfile_writes 2218922402 # number of integer regfile writes
490system.cpu.fp_regfile_reads 68796713 # number of floating regfile reads
491system.cpu.fp_regfile_writes 49556201 # number of floating regfile writes
492system.cpu.misc_regfile_reads 1363984791 # number of misc regfile reads

493system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes

494system.cpu.icache.replacements 22740 # number of replacements
495system.cpu.icache.tagsinuse 1642.119596 # Cycle average of tags in use
496system.cpu.icache.total_refs 333085977 # Total number of references to valid blocks.
497system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks.
498system.cpu.icache.avg_refs 13639.884398 # Average number of references to valid blocks.

494system.cpu.icache.replacements 22806 # number of replacements
495system.cpu.icache.tagsinuse 1643.708828 # Cycle average of tags in use
496system.cpu.icache.total_refs 335522072 # Total number of references to valid blocks.
497system.cpu.icache.sampled_refs 24489 # Sample count of references to valid blocks.
498system.cpu.icache.avg_refs 13700.929887 # Average number of references to valid blocks.

499system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

500system.cpu.icache.occ_blocks::cpu.inst 1642.119596 # Average occupied blocks per requestor
501system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy
502system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy
503system.cpu.icache.ReadReq_hits::cpu.inst 333090004 # number of ReadReq hits
504system.cpu.icache.ReadReq_hits::total 333090004 # number of ReadReq hits
505system.cpu.icache.demand_hits::cpu.inst 333090004 # number of demand (read+write) hits
506system.cpu.icache.demand_hits::total 333090004 # number of demand (read+write) hits
507system.cpu.icache.overall_hits::cpu.inst 333090004 # number of overall hits
508system.cpu.icache.overall_hits::total 333090004 # number of overall hits
509system.cpu.icache.ReadReq_misses::cpu.inst 31630 # number of ReadReq misses
510system.cpu.icache.ReadReq_misses::total 31630 # number of ReadReq misses
511system.cpu.icache.demand_misses::cpu.inst 31630 # number of demand (read+write) misses
512system.cpu.icache.demand_misses::total 31630 # number of demand (read+write) misses
513system.cpu.icache.overall_misses::cpu.inst 31630 # number of overall misses
514system.cpu.icache.overall_misses::total 31630 # number of overall misses
515system.cpu.icache.ReadReq_miss_latency::cpu.inst 481232999 # number of ReadReq miss cycles
516system.cpu.icache.ReadReq_miss_latency::total 481232999 # number of ReadReq miss cycles
517system.cpu.icache.demand_miss_latency::cpu.inst 481232999 # number of demand (read+write) miss cycles
518system.cpu.icache.demand_miss_latency::total 481232999 # number of demand (read+write) miss cycles
519system.cpu.icache.overall_miss_latency::cpu.inst 481232999 # number of overall miss cycles
520system.cpu.icache.overall_miss_latency::total 481232999 # number of overall miss cycles
521system.cpu.icache.ReadReq_accesses::cpu.inst 333121634 # number of ReadReq accesses(hits+misses)
522system.cpu.icache.ReadReq_accesses::total 333121634 # number of ReadReq accesses(hits+misses)
523system.cpu.icache.demand_accesses::cpu.inst 333121634 # number of demand (read+write) accesses
524system.cpu.icache.demand_accesses::total 333121634 # number of demand (read+write) accesses
525system.cpu.icache.overall_accesses::cpu.inst 333121634 # number of overall (read+write) accesses
526system.cpu.icache.overall_accesses::total 333121634 # number of overall (read+write) accesses
527system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses
528system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses
529system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses
530system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses
531system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses
532system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses
533system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15214.448277 # average ReadReq miss latency
534system.cpu.icache.ReadReq_avg_miss_latency::total 15214.448277 # average ReadReq miss latency
535system.cpu.icache.demand_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency
536system.cpu.icache.demand_avg_miss_latency::total 15214.448277 # average overall miss latency
537system.cpu.icache.overall_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency
538system.cpu.icache.overall_avg_miss_latency::total 15214.448277 # average overall miss latency
539system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked

500system.cpu.icache.occ_blocks::cpu.inst 1643.708828 # Average occupied blocks per requestor
501system.cpu.icache.occ_percent::cpu.inst 0.802592 # Average percentage of cache occupancy
502system.cpu.icache.occ_percent::total 0.802592 # Average percentage of cache occupancy
503system.cpu.icache.ReadReq_hits::cpu.inst 335526084 # number of ReadReq hits
504system.cpu.icache.ReadReq_hits::total 335526084 # number of ReadReq hits
505system.cpu.icache.demand_hits::cpu.inst 335526084 # number of demand (read+write) hits
506system.cpu.icache.demand_hits::total 335526084 # number of demand (read+write) hits
507system.cpu.icache.overall_hits::cpu.inst 335526084 # number of overall hits
508system.cpu.icache.overall_hits::total 335526084 # number of overall hits
509system.cpu.icache.ReadReq_misses::cpu.inst 31612 # number of ReadReq misses
510system.cpu.icache.ReadReq_misses::total 31612 # number of ReadReq misses
511system.cpu.icache.demand_misses::cpu.inst 31612 # number of demand (read+write) misses
512system.cpu.icache.demand_misses::total 31612 # number of demand (read+write) misses
513system.cpu.icache.overall_misses::cpu.inst 31612 # number of overall misses
514system.cpu.icache.overall_misses::total 31612 # number of overall misses
515system.cpu.icache.ReadReq_miss_latency::cpu.inst 479792499 # number of ReadReq miss cycles
516system.cpu.icache.ReadReq_miss_latency::total 479792499 # number of ReadReq miss cycles
517system.cpu.icache.demand_miss_latency::cpu.inst 479792499 # number of demand (read+write) miss cycles
518system.cpu.icache.demand_miss_latency::total 479792499 # number of demand (read+write) miss cycles
519system.cpu.icache.overall_miss_latency::cpu.inst 479792499 # number of overall miss cycles
520system.cpu.icache.overall_miss_latency::total 479792499 # number of overall miss cycles
521system.cpu.icache.ReadReq_accesses::cpu.inst 335557696 # number of ReadReq accesses(hits+misses)
522system.cpu.icache.ReadReq_accesses::total 335557696 # number of ReadReq accesses(hits+misses)
523system.cpu.icache.demand_accesses::cpu.inst 335557696 # number of demand (read+write) accesses
524system.cpu.icache.demand_accesses::total 335557696 # number of demand (read+write) accesses
525system.cpu.icache.overall_accesses::cpu.inst 335557696 # number of overall (read+write) accesses
526system.cpu.icache.overall_accesses::total 335557696 # number of overall (read+write) accesses
527system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses
528system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses
529system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses
530system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses
531system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses
532system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses
533system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15177.543306 # average ReadReq miss latency
534system.cpu.icache.ReadReq_avg_miss_latency::total 15177.543306 # average ReadReq miss latency
535system.cpu.icache.demand_avg_miss_latency::cpu.inst 15177.543306 # average overall miss latency
536system.cpu.icache.demand_avg_miss_latency::total 15177.543306 # average overall miss latency
537system.cpu.icache.overall_avg_miss_latency::cpu.inst 15177.543306 # average overall miss latency
538system.cpu.icache.overall_avg_miss_latency::total 15177.543306 # average overall miss latency
539system.cpu.icache.blocked_cycles::no_mshrs 835 # number of cycles access was blocked

540system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

541system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked

541system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked

542system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

543system.cpu.icache.avg_blocked_cycles::no_mshrs 32.692308 # average number of cycles each access was blocked

543system.cpu.icache.avg_blocked_cycles::no_mshrs 33.400000 # average number of cycles each access was blocked

544system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
545system.cpu.icache.fast_writes 0 # number of fast writes performed
546system.cpu.icache.cache_copies 0 # number of cache copies performed

547system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2899 # number of ReadReq MSHR hits
548system.cpu.icache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits
549system.cpu.icache.demand_mshr_hits::cpu.inst 2899 # number of demand (read+write) MSHR hits
550system.cpu.icache.demand_mshr_hits::total 2899 # number of demand (read+write) MSHR hits
551system.cpu.icache.overall_mshr_hits::cpu.inst 2899 # number of overall MSHR hits
552system.cpu.icache.overall_mshr_hits::total 2899 # number of overall MSHR hits
553system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28731 # number of ReadReq MSHR misses
554system.cpu.icache.ReadReq_mshr_misses::total 28731 # number of ReadReq MSHR misses
555system.cpu.icache.demand_mshr_misses::cpu.inst 28731 # number of demand (read+write) MSHR misses
556system.cpu.icache.demand_mshr_misses::total 28731 # number of demand (read+write) MSHR misses
557system.cpu.icache.overall_mshr_misses::cpu.inst 28731 # number of overall MSHR misses
558system.cpu.icache.overall_mshr_misses::total 28731 # number of overall MSHR misses
559system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386564499 # number of ReadReq MSHR miss cycles
560system.cpu.icache.ReadReq_mshr_miss_latency::total 386564499 # number of ReadReq MSHR miss cycles
561system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386564499 # number of demand (read+write) MSHR miss cycles
562system.cpu.icache.demand_mshr_miss_latency::total 386564499 # number of demand (read+write) MSHR miss cycles
563system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386564499 # number of overall MSHR miss cycles
564system.cpu.icache.overall_mshr_miss_latency::total 386564499 # number of overall MSHR miss cycles

547system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2827 # number of ReadReq MSHR hits
548system.cpu.icache.ReadReq_mshr_hits::total 2827 # number of ReadReq MSHR hits
549system.cpu.icache.demand_mshr_hits::cpu.inst 2827 # number of demand (read+write) MSHR hits
550system.cpu.icache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits
551system.cpu.icache.overall_mshr_hits::cpu.inst 2827 # number of overall MSHR hits
552system.cpu.icache.overall_mshr_hits::total 2827 # number of overall MSHR hits
553system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28785 # number of ReadReq MSHR misses
554system.cpu.icache.ReadReq_mshr_misses::total 28785 # number of ReadReq MSHR misses
555system.cpu.icache.demand_mshr_misses::cpu.inst 28785 # number of demand (read+write) MSHR misses
556system.cpu.icache.demand_mshr_misses::total 28785 # number of demand (read+write) MSHR misses
557system.cpu.icache.overall_mshr_misses::cpu.inst 28785 # number of overall MSHR misses
558system.cpu.icache.overall_mshr_misses::total 28785 # number of overall MSHR misses
559system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386126499 # number of ReadReq MSHR miss cycles
560system.cpu.icache.ReadReq_mshr_miss_latency::total 386126499 # number of ReadReq MSHR miss cycles
561system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386126499 # number of demand (read+write) MSHR miss cycles
562system.cpu.icache.demand_mshr_miss_latency::total 386126499 # number of demand (read+write) MSHR miss cycles
563system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386126499 # number of overall MSHR miss cycles
564system.cpu.icache.overall_mshr_miss_latency::total 386126499 # number of overall MSHR miss cycles

565system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
566system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
567system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
568system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
569system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
570system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses

571system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13454.613449 # average ReadReq mshr miss latency
572system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13454.613449 # average ReadReq mshr miss latency
573system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency
574system.cpu.icache.demand_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency
575system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency
576system.cpu.icache.overall_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency

571system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13414.156644 # average ReadReq mshr miss latency
572system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13414.156644 # average ReadReq mshr miss latency
573system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13414.156644 # average overall mshr miss latency
574system.cpu.icache.demand_avg_mshr_miss_latency::total 13414.156644 # average overall mshr miss latency
575system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13414.156644 # average overall mshr miss latency
576system.cpu.icache.overall_avg_mshr_miss_latency::total 13414.156644 # average overall mshr miss latency

577system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

578system.cpu.l2cache.replacements 442184 # number of replacements
579system.cpu.l2cache.tagsinuse 32692.574562 # Cycle average of tags in use
580system.cpu.l2cache.total_refs 1110053 # Total number of references to valid blocks.
581system.cpu.l2cache.sampled_refs 474931 # Sample count of references to valid blocks.
582system.cpu.l2cache.avg_refs 2.337293 # Average number of references to valid blocks.

578system.cpu.l2cache.replacements 442178 # number of replacements
579system.cpu.l2cache.tagsinuse 32692.553116 # Cycle average of tags in use
580system.cpu.l2cache.total_refs 1110010 # Total number of references to valid blocks.
581system.cpu.l2cache.sampled_refs 474925 # Sample count of references to valid blocks.
582system.cpu.l2cache.avg_refs 2.337232 # Average number of references to valid blocks.

583system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

584system.cpu.l2cache.occ_blocks::writebacks 1286.532429 # Average occupied blocks per requestor
585system.cpu.l2cache.occ_blocks::cpu.inst 50.222145 # Average occupied blocks per requestor
586system.cpu.l2cache.occ_blocks::cpu.data 31355.819987 # Average occupied blocks per requestor
587system.cpu.l2cache.occ_percent::writebacks 0.039262 # Average percentage of cache occupancy

584system.cpu.l2cache.occ_blocks::writebacks 1287.010485 # Average occupied blocks per requestor
585system.cpu.l2cache.occ_blocks::cpu.inst 50.235756 # Average occupied blocks per requestor
586system.cpu.l2cache.occ_blocks::cpu.data 31355.306875 # Average occupied blocks per requestor
587system.cpu.l2cache.occ_percent::writebacks 0.039276 # Average percentage of cache occupancy

588system.cpu.l2cache.occ_percent::cpu.inst 0.001533 # Average percentage of cache occupancy

589system.cpu.l2cache.occ_percent::cpu.data 0.956904 # Average percentage of cache occupancy

589system.cpu.l2cache.occ_percent::cpu.data 0.956888 # Average percentage of cache occupancy

590system.cpu.l2cache.occ_percent::total 0.997698 # Average percentage of cache occupancy

591system.cpu.l2cache.ReadReq_hits::cpu.inst 21996 # number of ReadReq hits
592system.cpu.l2cache.ReadReq_hits::cpu.data 1058215 # number of ReadReq hits
593system.cpu.l2cache.ReadReq_hits::total 1080211 # number of ReadReq hits
594system.cpu.l2cache.Writeback_hits::writebacks 96321 # number of Writeback hits
595system.cpu.l2cache.Writeback_hits::total 96321 # number of Writeback hits
596system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
597system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
598system.cpu.l2cache.ReadExReq_hits::cpu.data 6442 # number of ReadExReq hits
599system.cpu.l2cache.ReadExReq_hits::total 6442 # number of ReadExReq hits
600system.cpu.l2cache.demand_hits::cpu.inst 21996 # number of demand (read+write) hits
601system.cpu.l2cache.demand_hits::cpu.data 1064657 # number of demand (read+write) hits
602system.cpu.l2cache.demand_hits::total 1086653 # number of demand (read+write) hits
603system.cpu.l2cache.overall_hits::cpu.inst 21996 # number of overall hits
604system.cpu.l2cache.overall_hits::cpu.data 1064657 # number of overall hits
605system.cpu.l2cache.overall_hits::total 1086653 # number of overall hits
606system.cpu.l2cache.ReadReq_misses::cpu.inst 2425 # number of ReadReq misses
607system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses
608system.cpu.l2cache.ReadReq_misses::total 408916 # number of ReadReq misses
609system.cpu.l2cache.UpgradeReq_misses::cpu.data 4308 # number of UpgradeReq misses
610system.cpu.l2cache.UpgradeReq_misses::total 4308 # number of UpgradeReq misses
611system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
612system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
613system.cpu.l2cache.demand_misses::cpu.inst 2425 # number of demand (read+write) misses
614system.cpu.l2cache.demand_misses::cpu.data 472566 # number of demand (read+write) misses
615system.cpu.l2cache.demand_misses::total 474991 # number of demand (read+write) misses
616system.cpu.l2cache.overall_misses::cpu.inst 2425 # number of overall misses
617system.cpu.l2cache.overall_misses::cpu.data 472566 # number of overall misses
618system.cpu.l2cache.overall_misses::total 474991 # number of overall misses
619system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 133322500 # number of ReadReq miss cycles
620system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783806000 # number of ReadReq miss cycles
621system.cpu.l2cache.ReadReq_miss_latency::total 28917128500 # number of ReadReq miss cycles
622system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174251000 # number of ReadExReq miss cycles
623system.cpu.l2cache.ReadExReq_miss_latency::total 3174251000 # number of ReadExReq miss cycles
624system.cpu.l2cache.demand_miss_latency::cpu.inst 133322500 # number of demand (read+write) miss cycles
625system.cpu.l2cache.demand_miss_latency::cpu.data 31958057000 # number of demand (read+write) miss cycles
626system.cpu.l2cache.demand_miss_latency::total 32091379500 # number of demand (read+write) miss cycles
627system.cpu.l2cache.overall_miss_latency::cpu.inst 133322500 # number of overall miss cycles
628system.cpu.l2cache.overall_miss_latency::cpu.data 31958057000 # number of overall miss cycles
629system.cpu.l2cache.overall_miss_latency::total 32091379500 # number of overall miss cycles
630system.cpu.l2cache.ReadReq_accesses::cpu.inst 24421 # number of ReadReq accesses(hits+misses)
631system.cpu.l2cache.ReadReq_accesses::cpu.data 1464706 # number of ReadReq accesses(hits+misses)
632system.cpu.l2cache.ReadReq_accesses::total 1489127 # number of ReadReq accesses(hits+misses)
633system.cpu.l2cache.Writeback_accesses::writebacks 96321 # number of Writeback accesses(hits+misses)
634system.cpu.l2cache.Writeback_accesses::total 96321 # number of Writeback accesses(hits+misses)
635system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4311 # number of UpgradeReq accesses(hits+misses)
636system.cpu.l2cache.UpgradeReq_accesses::total 4311 # number of UpgradeReq accesses(hits+misses)
637system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses)
638system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses)
639system.cpu.l2cache.demand_accesses::cpu.inst 24421 # number of demand (read+write) accesses
640system.cpu.l2cache.demand_accesses::cpu.data 1537223 # number of demand (read+write) accesses
641system.cpu.l2cache.demand_accesses::total 1561644 # number of demand (read+write) accesses
642system.cpu.l2cache.overall_accesses::cpu.inst 24421 # number of overall (read+write) accesses
643system.cpu.l2cache.overall_accesses::cpu.data 1537223 # number of overall (read+write) accesses
644system.cpu.l2cache.overall_accesses::total 1561644 # number of overall (read+write) accesses
645system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099300 # miss rate for ReadReq accesses
646system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277524 # miss rate for ReadReq accesses
647system.cpu.l2cache.ReadReq_miss_rate::total 0.274601 # miss rate for ReadReq accesses
648system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999304 # miss rate for UpgradeReq accesses
649system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999304 # miss rate for UpgradeReq accesses
650system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911166 # miss rate for ReadExReq accesses
651system.cpu.l2cache.ReadExReq_miss_rate::total 0.911166 # miss rate for ReadExReq accesses
652system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099300 # miss rate for demand accesses
653system.cpu.l2cache.demand_miss_rate::cpu.data 0.307415 # miss rate for demand accesses
654system.cpu.l2cache.demand_miss_rate::total 0.304161 # miss rate for demand accesses
655system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099300 # miss rate for overall accesses
656system.cpu.l2cache.overall_miss_rate::cpu.data 0.307415 # miss rate for overall accesses
657system.cpu.l2cache.overall_miss_rate::total 0.304161 # miss rate for overall accesses
658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54978.350515 # average ReadReq miss latency
659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.438607 # average ReadReq miss latency
660system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.549365 # average ReadReq miss latency
661system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.121075 # average ReadExReq miss latency
662system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.121075 # average ReadExReq miss latency
663system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency
664system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency
665system.cpu.l2cache.demand_avg_miss_latency::total 67562.079071 # average overall miss latency
666system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency
667system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency
668system.cpu.l2cache.overall_avg_miss_latency::total 67562.079071 # average overall miss latency

591system.cpu.l2cache.ReadReq_hits::cpu.inst 22064 # number of ReadReq hits
592system.cpu.l2cache.ReadReq_hits::cpu.data 1058101 # number of ReadReq hits
593system.cpu.l2cache.ReadReq_hits::total 1080165 # number of ReadReq hits
594system.cpu.l2cache.Writeback_hits::writebacks 96323 # number of Writeback hits
595system.cpu.l2cache.Writeback_hits::total 96323 # number of Writeback hits
596system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
597system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
598system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits
599system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits
600system.cpu.l2cache.demand_hits::cpu.inst 22064 # number of demand (read+write) hits
601system.cpu.l2cache.demand_hits::cpu.data 1064542 # number of demand (read+write) hits
602system.cpu.l2cache.demand_hits::total 1086606 # number of demand (read+write) hits
603system.cpu.l2cache.overall_hits::cpu.inst 22064 # number of overall hits
604system.cpu.l2cache.overall_hits::cpu.data 1064542 # number of overall hits
605system.cpu.l2cache.overall_hits::total 1086606 # number of overall hits
606system.cpu.l2cache.ReadReq_misses::cpu.inst 2426 # number of ReadReq misses
607system.cpu.l2cache.ReadReq_misses::cpu.data 406486 # number of ReadReq misses
608system.cpu.l2cache.ReadReq_misses::total 408912 # number of ReadReq misses
609system.cpu.l2cache.UpgradeReq_misses::cpu.data 4291 # number of UpgradeReq misses
610system.cpu.l2cache.UpgradeReq_misses::total 4291 # number of UpgradeReq misses
611system.cpu.l2cache.ReadExReq_misses::cpu.data 66074 # number of ReadExReq misses
612system.cpu.l2cache.ReadExReq_misses::total 66074 # number of ReadExReq misses
613system.cpu.l2cache.demand_misses::cpu.inst 2426 # number of demand (read+write) misses
614system.cpu.l2cache.demand_misses::cpu.data 472560 # number of demand (read+write) misses
615system.cpu.l2cache.demand_misses::total 474986 # number of demand (read+write) misses
616system.cpu.l2cache.overall_misses::cpu.inst 2426 # number of overall misses
617system.cpu.l2cache.overall_misses::cpu.data 472560 # number of overall misses
618system.cpu.l2cache.overall_misses::total 474986 # number of overall misses
619system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132157500 # number of ReadReq miss cycles
620system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29065267000 # number of ReadReq miss cycles
621system.cpu.l2cache.ReadReq_miss_latency::total 29197424500 # number of ReadReq miss cycles
622system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174202000 # number of ReadExReq miss cycles
623system.cpu.l2cache.ReadExReq_miss_latency::total 3174202000 # number of ReadExReq miss cycles
624system.cpu.l2cache.demand_miss_latency::cpu.inst 132157500 # number of demand (read+write) miss cycles
625system.cpu.l2cache.demand_miss_latency::cpu.data 32239469000 # number of demand (read+write) miss cycles
626system.cpu.l2cache.demand_miss_latency::total 32371626500 # number of demand (read+write) miss cycles
627system.cpu.l2cache.overall_miss_latency::cpu.inst 132157500 # number of overall miss cycles
628system.cpu.l2cache.overall_miss_latency::cpu.data 32239469000 # number of overall miss cycles
629system.cpu.l2cache.overall_miss_latency::total 32371626500 # number of overall miss cycles
630system.cpu.l2cache.ReadReq_accesses::cpu.inst 24490 # number of ReadReq accesses(hits+misses)
631system.cpu.l2cache.ReadReq_accesses::cpu.data 1464587 # number of ReadReq accesses(hits+misses)
632system.cpu.l2cache.ReadReq_accesses::total 1489077 # number of ReadReq accesses(hits+misses)
633system.cpu.l2cache.Writeback_accesses::writebacks 96323 # number of Writeback accesses(hits+misses)
634system.cpu.l2cache.Writeback_accesses::total 96323 # number of Writeback accesses(hits+misses)
635system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4296 # number of UpgradeReq accesses(hits+misses)
636system.cpu.l2cache.UpgradeReq_accesses::total 4296 # number of UpgradeReq accesses(hits+misses)
637system.cpu.l2cache.ReadExReq_accesses::cpu.data 72515 # number of ReadExReq accesses(hits+misses)
638system.cpu.l2cache.ReadExReq_accesses::total 72515 # number of ReadExReq accesses(hits+misses)
639system.cpu.l2cache.demand_accesses::cpu.inst 24490 # number of demand (read+write) accesses
640system.cpu.l2cache.demand_accesses::cpu.data 1537102 # number of demand (read+write) accesses
641system.cpu.l2cache.demand_accesses::total 1561592 # number of demand (read+write) accesses
642system.cpu.l2cache.overall_accesses::cpu.inst 24490 # number of overall (read+write) accesses
643system.cpu.l2cache.overall_accesses::cpu.data 1537102 # number of overall (read+write) accesses
644system.cpu.l2cache.overall_accesses::total 1561592 # number of overall (read+write) accesses
645system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099061 # miss rate for ReadReq accesses
646system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277543 # miss rate for ReadReq accesses
647system.cpu.l2cache.ReadReq_miss_rate::total 0.274608 # miss rate for ReadReq accesses
648system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.998836 # miss rate for UpgradeReq accesses
649system.cpu.l2cache.UpgradeReq_miss_rate::total 0.998836 # miss rate for UpgradeReq accesses
650system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911177 # miss rate for ReadExReq accesses
651system.cpu.l2cache.ReadExReq_miss_rate::total 0.911177 # miss rate for ReadExReq accesses
652system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099061 # miss rate for demand accesses
653system.cpu.l2cache.demand_miss_rate::cpu.data 0.307436 # miss rate for demand accesses
654system.cpu.l2cache.demand_miss_rate::total 0.304168 # miss rate for demand accesses
655system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099061 # miss rate for overall accesses
656system.cpu.l2cache.overall_miss_rate::cpu.data 0.307436 # miss rate for overall accesses
657system.cpu.l2cache.overall_miss_rate::total 0.304168 # miss rate for overall accesses
658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54475.474031 # average ReadReq miss latency
659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71503.734446 # average ReadReq miss latency
660system.cpu.l2cache.ReadReq_avg_miss_latency::total 71402.708896 # average ReadReq miss latency
661system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.106547 # average ReadExReq miss latency
662system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.106547 # average ReadExReq miss latency
663system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54475.474031 # average overall miss latency
664system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68223.017183 # average overall miss latency
665system.cpu.l2cache.demand_avg_miss_latency::total 68152.801346 # average overall miss latency
666system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54475.474031 # average overall miss latency
667system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68223.017183 # average overall miss latency
668system.cpu.l2cache.overall_avg_miss_latency::total 68152.801346 # average overall miss latency

669system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
670system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
671system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
672system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
673system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
674system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
675system.cpu.l2cache.fast_writes 0 # number of fast writes performed
676system.cpu.l2cache.cache_copies 0 # number of cache copies performed
677system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
678system.cpu.l2cache.writebacks::total 66098 # number of writebacks
679system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits

680system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
681system.cpu.l2cache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits

680system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
681system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits

682system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits

683system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
684system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits

683system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
684system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits

685system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits

686system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
687system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits
688system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2421 # number of ReadReq MSHR misses
689system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406470 # number of ReadReq MSHR misses
690system.cpu.l2cache.ReadReq_mshr_misses::total 408891 # number of ReadReq MSHR misses
691system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4308 # number of UpgradeReq MSHR misses
692system.cpu.l2cache.UpgradeReq_mshr_misses::total 4308 # number of UpgradeReq MSHR misses
693system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
694system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
695system.cpu.l2cache.demand_mshr_misses::cpu.inst 2421 # number of demand (read+write) MSHR misses
696system.cpu.l2cache.demand_mshr_misses::cpu.data 472545 # number of demand (read+write) MSHR misses
697system.cpu.l2cache.demand_mshr_misses::total 474966 # number of demand (read+write) MSHR misses
698system.cpu.l2cache.overall_mshr_misses::cpu.inst 2421 # number of overall MSHR misses
699system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses
700system.cpu.l2cache.overall_mshr_misses::total 474966 # number of overall MSHR misses
701system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103134689 # number of ReadReq MSHR miss cycles
702system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729007693 # number of ReadReq MSHR miss cycles
703system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832142382 # number of ReadReq MSHR miss cycles
704system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43084308 # number of UpgradeReq MSHR miss cycles
705system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43084308 # number of UpgradeReq MSHR miss cycles
706system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357071286 # number of ReadExReq MSHR miss cycles
707system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357071286 # number of ReadExReq MSHR miss cycles
708system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103134689 # number of demand (read+write) MSHR miss cycles
709system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086078979 # number of demand (read+write) MSHR miss cycles
710system.cpu.l2cache.demand_mshr_miss_latency::total 26189213668 # number of demand (read+write) MSHR miss cycles
711system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103134689 # number of overall MSHR miss cycles
712system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086078979 # number of overall MSHR miss cycles
713system.cpu.l2cache.overall_mshr_miss_latency::total 26189213668 # number of overall MSHR miss cycles
714system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for ReadReq accesses
715system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277510 # mshr miss rate for ReadReq accesses
716system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274584 # mshr miss rate for ReadReq accesses
717system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999304 # mshr miss rate for UpgradeReq accesses
718system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999304 # mshr miss rate for UpgradeReq accesses
719system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses
720system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses
721system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for demand accesses
722system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for demand accesses
723system.cpu.l2cache.demand_mshr_miss_rate::total 0.304145 # mshr miss rate for demand accesses
724system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for overall accesses
725system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for overall accesses
726system.cpu.l2cache.overall_mshr_miss_rate::total 0.304145 # mshr miss rate for overall accesses
727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.036762 # average ReadReq mshr miss latency
728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58378.251022 # average ReadReq mshr miss latency
729system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58284.829898 # average ReadReq mshr miss latency

686system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
687system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
688system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2422 # number of ReadReq MSHR misses
689system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406463 # number of ReadReq MSHR misses
690system.cpu.l2cache.ReadReq_mshr_misses::total 408885 # number of ReadReq MSHR misses
691system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4291 # number of UpgradeReq MSHR misses
692system.cpu.l2cache.UpgradeReq_mshr_misses::total 4291 # number of UpgradeReq MSHR misses
693system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66074 # number of ReadExReq MSHR misses
694system.cpu.l2cache.ReadExReq_mshr_misses::total 66074 # number of ReadExReq MSHR misses
695system.cpu.l2cache.demand_mshr_misses::cpu.inst 2422 # number of demand (read+write) MSHR misses
696system.cpu.l2cache.demand_mshr_misses::cpu.data 472537 # number of demand (read+write) MSHR misses
697system.cpu.l2cache.demand_mshr_misses::total 474959 # number of demand (read+write) MSHR misses
698system.cpu.l2cache.overall_mshr_misses::cpu.inst 2422 # number of overall MSHR misses
699system.cpu.l2cache.overall_mshr_misses::cpu.data 472537 # number of overall MSHR misses
700system.cpu.l2cache.overall_mshr_misses::total 474959 # number of overall MSHR misses
701system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101956685 # number of ReadReq MSHR miss cycles
702system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24008915183 # number of ReadReq MSHR miss cycles
703system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24110871868 # number of ReadReq MSHR miss cycles
704system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42914291 # number of UpgradeReq MSHR miss cycles
705system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42914291 # number of UpgradeReq MSHR miss cycles
706system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357034286 # number of ReadExReq MSHR miss cycles
707system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357034286 # number of ReadExReq MSHR miss cycles
708system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101956685 # number of demand (read+write) MSHR miss cycles
709system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26365949469 # number of demand (read+write) MSHR miss cycles
710system.cpu.l2cache.demand_mshr_miss_latency::total 26467906154 # number of demand (read+write) MSHR miss cycles
711system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101956685 # number of overall MSHR miss cycles
712system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26365949469 # number of overall MSHR miss cycles
713system.cpu.l2cache.overall_mshr_miss_latency::total 26467906154 # number of overall MSHR miss cycles
714system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098898 # mshr miss rate for ReadReq accesses
715system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277527 # mshr miss rate for ReadReq accesses
716system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274590 # mshr miss rate for ReadReq accesses
717system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998836 # mshr miss rate for UpgradeReq accesses
718system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.998836 # mshr miss rate for UpgradeReq accesses
719system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911177 # mshr miss rate for ReadExReq accesses
720system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911177 # mshr miss rate for ReadExReq accesses
721system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098898 # mshr miss rate for demand accesses
722system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307421 # mshr miss rate for demand accesses
723system.cpu.l2cache.demand_mshr_miss_rate::total 0.304151 # mshr miss rate for demand accesses
724system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098898 # mshr miss rate for overall accesses
725system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307421 # mshr miss rate for overall accesses
726system.cpu.l2cache.overall_mshr_miss_rate::total 0.304151 # mshr miss rate for overall accesses
727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42096.071429 # average ReadReq mshr miss latency
728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59067.898389 # average ReadReq mshr miss latency
729system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58967.367030 # average ReadReq mshr miss latency

730system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
731system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency

732system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.664185 # average ReadExReq mshr miss latency
733system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.664185 # average ReadExReq mshr miss latency
734system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency
735system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency
736system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency
737system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency
738system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency
739system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency

732system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.644096 # average ReadExReq mshr miss latency
733system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.644096 # average ReadExReq mshr miss latency
734system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42096.071429 # average overall mshr miss latency
735system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55796.582001 # average overall mshr miss latency
736system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55726.717788 # average overall mshr miss latency
737system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42096.071429 # average overall mshr miss latency
738system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55796.582001 # average overall mshr miss latency
739system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55726.717788 # average overall mshr miss latency

740system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

741system.cpu.dcache.replacements 1533127 # number of replacements
742system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use
743system.cpu.dcache.total_refs 969988245 # Total number of references to valid blocks.
744system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks.
745system.cpu.dcache.avg_refs 631.000346 # Average number of references to valid blocks.

741system.cpu.dcache.replacements 1533005 # number of replacements
742system.cpu.dcache.tagsinuse 4094.655355 # Cycle average of tags in use
743system.cpu.dcache.total_refs 969956043 # Total number of references to valid blocks.
744system.cpu.dcache.sampled_refs 1537101 # Sample count of references to valid blocks.
745system.cpu.dcache.avg_refs 631.029479 # Average number of references to valid blocks.

746system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit.

747system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor

747system.cpu.dcache.occ_blocks::cpu.data 4094.655355 # Average occupied blocks per requestor

748system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy
749system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy

750system.cpu.dcache.ReadReq_hits::cpu.data 693861536 # number of ReadReq hits
751system.cpu.dcache.ReadReq_hits::total 693861536 # number of ReadReq hits
752system.cpu.dcache.WriteReq_hits::cpu.data 276093810 # number of WriteReq hits
753system.cpu.dcache.WriteReq_hits::total 276093810 # number of WriteReq hits

750system.cpu.dcache.ReadReq_hits::cpu.data 693829407 # number of ReadReq hits
751system.cpu.dcache.ReadReq_hits::total 693829407 # number of ReadReq hits
752system.cpu.dcache.WriteReq_hits::cpu.data 276093791 # number of WriteReq hits
753system.cpu.dcache.WriteReq_hits::total 276093791 # number of WriteReq hits

754system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits
755system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits
756system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
757system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits

758system.cpu.dcache.demand_hits::cpu.data 969955346 # number of demand (read+write) hits
759system.cpu.dcache.demand_hits::total 969955346 # number of demand (read+write) hits
760system.cpu.dcache.overall_hits::cpu.data 969955346 # number of overall hits
761system.cpu.dcache.overall_hits::total 969955346 # number of overall hits
762system.cpu.dcache.ReadReq_misses::cpu.data 1953541 # number of ReadReq misses
763system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses
764system.cpu.dcache.WriteReq_misses::cpu.data 841868 # number of WriteReq misses
765system.cpu.dcache.WriteReq_misses::total 841868 # number of WriteReq misses

758system.cpu.dcache.demand_hits::cpu.data 969923198 # number of demand (read+write) hits
759system.cpu.dcache.demand_hits::total 969923198 # number of demand (read+write) hits
760system.cpu.dcache.overall_hits::cpu.data 969923198 # number of overall hits
761system.cpu.dcache.overall_hits::total 969923198 # number of overall hits
762system.cpu.dcache.ReadReq_misses::cpu.data 1953276 # number of ReadReq misses
763system.cpu.dcache.ReadReq_misses::total 1953276 # number of ReadReq misses
764system.cpu.dcache.WriteReq_misses::cpu.data 841887 # number of WriteReq misses
765system.cpu.dcache.WriteReq_misses::total 841887 # number of WriteReq misses

766system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
767system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses

768system.cpu.dcache.demand_misses::cpu.data 2795409 # number of demand (read+write) misses
769system.cpu.dcache.demand_misses::total 2795409 # number of demand (read+write) misses
770system.cpu.dcache.overall_misses::cpu.data 2795409 # number of overall misses
771system.cpu.dcache.overall_misses::total 2795409 # number of overall misses
772system.cpu.dcache.ReadReq_miss_latency::cpu.data 66484216000 # number of ReadReq miss cycles
773system.cpu.dcache.ReadReq_miss_latency::total 66484216000 # number of ReadReq miss cycles
774system.cpu.dcache.WriteReq_miss_latency::cpu.data 39427025969 # number of WriteReq miss cycles
775system.cpu.dcache.WriteReq_miss_latency::total 39427025969 # number of WriteReq miss cycles
776system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles
777system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles
778system.cpu.dcache.demand_miss_latency::cpu.data 105911241969 # number of demand (read+write) miss cycles
779system.cpu.dcache.demand_miss_latency::total 105911241969 # number of demand (read+write) miss cycles
780system.cpu.dcache.overall_miss_latency::cpu.data 105911241969 # number of overall miss cycles
781system.cpu.dcache.overall_miss_latency::total 105911241969 # number of overall miss cycles
782system.cpu.dcache.ReadReq_accesses::cpu.data 695815077 # number of ReadReq accesses(hits+misses)
783system.cpu.dcache.ReadReq_accesses::total 695815077 # number of ReadReq accesses(hits+misses)

768system.cpu.dcache.demand_misses::cpu.data 2795163 # number of demand (read+write) misses
769system.cpu.dcache.demand_misses::total 2795163 # number of demand (read+write) misses
770system.cpu.dcache.overall_misses::cpu.data 2795163 # number of overall misses
771system.cpu.dcache.overall_misses::total 2795163 # number of overall misses
772system.cpu.dcache.ReadReq_miss_latency::cpu.data 66762023500 # number of ReadReq miss cycles
773system.cpu.dcache.ReadReq_miss_latency::total 66762023500 # number of ReadReq miss cycles
774system.cpu.dcache.WriteReq_miss_latency::cpu.data 39426392469 # number of WriteReq miss cycles
775system.cpu.dcache.WriteReq_miss_latency::total 39426392469 # number of WriteReq miss cycles
776system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles
777system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles
778system.cpu.dcache.demand_miss_latency::cpu.data 106188415969 # number of demand (read+write) miss cycles
779system.cpu.dcache.demand_miss_latency::total 106188415969 # number of demand (read+write) miss cycles
780system.cpu.dcache.overall_miss_latency::cpu.data 106188415969 # number of overall miss cycles
781system.cpu.dcache.overall_miss_latency::total 106188415969 # number of overall miss cycles
782system.cpu.dcache.ReadReq_accesses::cpu.data 695782683 # number of ReadReq accesses(hits+misses)
783system.cpu.dcache.ReadReq_accesses::total 695782683 # number of ReadReq accesses(hits+misses)

784system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
785system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
786system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses)
787system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses)
788system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
789system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)

790system.cpu.dcache.demand_accesses::cpu.data 972750755 # number of demand (read+write) accesses
791system.cpu.dcache.demand_accesses::total 972750755 # number of demand (read+write) accesses
792system.cpu.dcache.overall_accesses::cpu.data 972750755 # number of overall (read+write) accesses
793system.cpu.dcache.overall_accesses::total 972750755 # number of overall (read+write) accesses
794system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses
795system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses

790system.cpu.dcache.demand_accesses::cpu.data 972718361 # number of demand (read+write) accesses
791system.cpu.dcache.demand_accesses::total 972718361 # number of demand (read+write) accesses
792system.cpu.dcache.overall_accesses::cpu.data 972718361 # number of overall (read+write) accesses
793system.cpu.dcache.overall_accesses::total 972718361 # number of overall (read+write) accesses
794system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
795system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses

796system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses
797system.cpu.dcache.WriteReq_miss_rate::total 0.003040 # miss rate for WriteReq accesses
798system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
799system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
800system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 # miss rate for demand accesses
801system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses
802system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses
803system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses

804system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34032.669906 # average ReadReq miss latency
805system.cpu.dcache.ReadReq_avg_miss_latency::total 34032.669906 # average ReadReq miss latency
806system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46832.788476 # average WriteReq miss latency
807system.cpu.dcache.WriteReq_avg_miss_latency::total 46832.788476 # average WriteReq miss latency
808system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency
809system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency
810system.cpu.dcache.demand_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency
811system.cpu.dcache.demand_avg_miss_latency::total 37887.565637 # average overall miss latency
812system.cpu.dcache.overall_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency
813system.cpu.dcache.overall_avg_miss_latency::total 37887.565637 # average overall miss latency

804system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34179.513545 # average ReadReq miss latency
805system.cpu.dcache.ReadReq_avg_miss_latency::total 34179.513545 # average ReadReq miss latency
806system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46830.979061 # average WriteReq miss latency
807system.cpu.dcache.WriteReq_avg_miss_latency::total 46830.979061 # average WriteReq miss latency
808system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency
809system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency
810system.cpu.dcache.demand_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency
811system.cpu.dcache.demand_avg_miss_latency::total 37990.062107 # average overall miss latency
812system.cpu.dcache.overall_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency
813system.cpu.dcache.overall_avg_miss_latency::total 37990.062107 # average overall miss latency

814system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked

815system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked

815system.cpu.dcache.blocked_cycles::no_targets 726 # number of cycles access was blocked

816system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked

817system.cpu.dcache.blocked::no_targets 90 # number of cycles access was blocked

817system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked

818system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807018 # average number of cycles each access was blocked

819system.cpu.dcache.avg_blocked_cycles::no_targets 8.300000 # average number of cycles each access was blocked

819system.cpu.dcache.avg_blocked_cycles::no_targets 8.157303 # average number of cycles each access was blocked

820system.cpu.dcache.fast_writes 0 # number of fast writes performed
821system.cpu.dcache.cache_copies 0 # number of cache copies performed

822system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks
823system.cpu.dcache.writebacks::total 96321 # number of writebacks
824system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits
825system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits
826system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765041 # number of WriteReq MSHR hits
827system.cpu.dcache.WriteReq_mshr_hits::total 765041 # number of WriteReq MSHR hits

822system.cpu.dcache.writebacks::writebacks 96323 # number of writebacks
823system.cpu.dcache.writebacks::total 96323 # number of writebacks
824system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488688 # number of ReadReq MSHR hits
825system.cpu.dcache.ReadReq_mshr_hits::total 488688 # number of ReadReq MSHR hits
826system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765077 # number of WriteReq MSHR hits
827system.cpu.dcache.WriteReq_mshr_hits::total 765077 # number of WriteReq MSHR hits

828system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
829system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits

830system.cpu.dcache.demand_mshr_hits::cpu.data 1253875 # number of demand (read+write) MSHR hits
831system.cpu.dcache.demand_mshr_hits::total 1253875 # number of demand (read+write) MSHR hits
832system.cpu.dcache.overall_mshr_hits::cpu.data 1253875 # number of overall MSHR hits
833system.cpu.dcache.overall_mshr_hits::total 1253875 # number of overall MSHR hits
834system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses
835system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses
836system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76827 # number of WriteReq MSHR misses
837system.cpu.dcache.WriteReq_mshr_misses::total 76827 # number of WriteReq MSHR misses
838system.cpu.dcache.demand_mshr_misses::cpu.data 1541534 # number of demand (read+write) MSHR misses
839system.cpu.dcache.demand_mshr_misses::total 1541534 # number of demand (read+write) MSHR misses
840system.cpu.dcache.overall_mshr_misses::cpu.data 1541534 # number of overall MSHR misses
841system.cpu.dcache.overall_mshr_misses::total 1541534 # number of overall MSHR misses
842system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831573000 # number of ReadReq MSHR miss cycles
843system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831573000 # number of ReadReq MSHR miss cycles
844system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409419500 # number of WriteReq MSHR miss cycles
845system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409419500 # number of WriteReq MSHR miss cycles
846system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240992500 # number of demand (read+write) MSHR miss cycles
847system.cpu.dcache.demand_mshr_miss_latency::total 44240992500 # number of demand (read+write) MSHR miss cycles
848system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240992500 # number of overall MSHR miss cycles
849system.cpu.dcache.overall_mshr_miss_latency::total 44240992500 # number of overall MSHR miss cycles

830system.cpu.dcache.demand_mshr_hits::cpu.data 1253765 # number of demand (read+write) MSHR hits
831system.cpu.dcache.demand_mshr_hits::total 1253765 # number of demand (read+write) MSHR hits
832system.cpu.dcache.overall_mshr_hits::cpu.data 1253765 # number of overall MSHR hits
833system.cpu.dcache.overall_mshr_hits::total 1253765 # number of overall MSHR hits
834system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464588 # number of ReadReq MSHR misses
835system.cpu.dcache.ReadReq_mshr_misses::total 1464588 # number of ReadReq MSHR misses
836system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76810 # number of WriteReq MSHR misses
837system.cpu.dcache.WriteReq_mshr_misses::total 76810 # number of WriteReq MSHR misses
838system.cpu.dcache.demand_mshr_misses::cpu.data 1541398 # number of demand (read+write) MSHR misses
839system.cpu.dcache.demand_mshr_misses::total 1541398 # number of demand (read+write) MSHR misses
840system.cpu.dcache.overall_mshr_misses::cpu.data 1541398 # number of overall MSHR misses
841system.cpu.dcache.overall_mshr_misses::total 1541398 # number of overall MSHR misses
842system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41111704000 # number of ReadReq MSHR miss cycles
843system.cpu.dcache.ReadReq_mshr_miss_latency::total 41111704000 # number of ReadReq MSHR miss cycles
844system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3408970500 # number of WriteReq MSHR miss cycles
845system.cpu.dcache.WriteReq_mshr_miss_latency::total 3408970500 # number of WriteReq MSHR miss cycles
846system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44520674500 # number of demand (read+write) MSHR miss cycles
847system.cpu.dcache.demand_mshr_miss_latency::total 44520674500 # number of demand (read+write) MSHR miss cycles
848system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44520674500 # number of overall MSHR miss cycles
849system.cpu.dcache.overall_mshr_miss_latency::total 44520674500 # number of overall MSHR miss cycles

850system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
851system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
852system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
853system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
854system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
855system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
856system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
857system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses

858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.956279 # average ReadReq mshr miss latency
859system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.956279 # average ReadReq mshr miss latency
860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44377.881474 # average WriteReq mshr miss latency
861system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44377.881474 # average WriteReq mshr miss latency
862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency
863system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency
864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency
865system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency

858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28070.490814 # average ReadReq mshr miss latency
859system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28070.490814 # average ReadReq mshr miss latency
860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44381.857831 # average WriteReq mshr miss latency
861system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44381.857831 # average WriteReq mshr miss latency
862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency
863system.cpu.dcache.demand_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency
864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency
865system.cpu.dcache.overall_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency