Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.624868 # Number of seconds simulated
4sim_ticks 624867585500 # Number of ticks simulated
5final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.625047 # Number of seconds simulated
4sim_ticks 625047295000 # Number of ticks simulated
5final_tick 625047295000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 53257 # Simulator instruction rate (inst/s)
8host_op_rate 72528 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 24038469 # Simulator tick rate (ticks/s)
10host_mem_usage 255596 # Number of bytes of host memory used
11host_seconds 25994.48 # Real time elapsed on the host
12sim_insts 1384379060 # Number of instructions simulated
13sim_ops 1885333812 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 30242752 # Number of bytes read from this memory

7host_inst_rate 94484 # Simulator instruction rate (inst/s)
8host_op_rate 128674 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 42659692 # Simulator tick rate (ticks/s)
10host_mem_usage 264788 # Number of bytes of host memory used
11host_seconds 14651.94 # Real time elapsed on the host
12sim_insts 1384370590 # Number of instructions simulated
13sim_ops 1885325342 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 155456 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory

16system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory

17system.physmem.bytes_inst_read::cpu.inst 155584 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 155584 # Number of instructions bytes read from this memory

17system.physmem.bytes_inst_read::cpu.inst 155456 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 155456 # Number of instructions bytes read from this memory

19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
20system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory

21system.physmem.num_reads::cpu.inst 2431 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 472543 # Number of read requests responded to by this memory

21system.physmem.num_reads::cpu.inst 2429 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory

23system.physmem.num_reads::total 474974 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory

26system.physmem.bw_read::cpu.inst 248987 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 48398657 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 48647644 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 248987 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 248987 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 6769869 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 6769869 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 6769869 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 248987 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 48398657 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 55417514 # Total bandwidth to/from this memory (bytes/s)

26system.physmem.bw_read::cpu.inst 248711 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 48384947 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 48633657 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 248711 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 248711 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 6767923 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 6767923 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 6767923 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 248711 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 48384947 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 55401580 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.readReqs 474974 # Total number of read requests seen
38system.physmem.writeReqs 66098 # Total number of write requests seen

39system.physmem.cpureqs 545402 # Reqs generatd by CPU via cache - shady

39system.physmem.cpureqs 545412 # Reqs generatd by CPU via cache - shady

40system.physmem.bytesRead 30398336 # Total number of bytes read from memory
41system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
42system.physmem.bytesConsumedRd 30398336 # bytesRead derated as per pkt->getSize()
43system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()

44system.physmem.servicedByWrQ 146 # Number of read reqs serviced by write Q
45system.physmem.neitherReadNorWrite 4330 # Reqs where no action is needed
46system.physmem.perBankRdReqs::0 29668 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::1 29687 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::2 29628 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::3 29545 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::4 29653 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::5 29623 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::6 29618 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::7 29734 # Track reads on a per bank basis

44system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q
45system.physmem.neitherReadNorWrite 4340 # Reqs where no action is needed
46system.physmem.perBankRdReqs::0 29671 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::1 29693 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::3 29543 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::4 29652 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::5 29628 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::6 29613 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::7 29731 # Track reads on a per bank basis

54system.physmem.perBankRdReqs::8 29744 # Track reads on a per bank basis

55system.physmem.perBankRdReqs::9 29769 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::10 29790 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::11 29857 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::12 29669 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::13 29606 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::14 29627 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::15 29610 # Track reads on a per bank basis

55system.physmem.perBankRdReqs::9 29771 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::10 29793 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::12 29658 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::13 29603 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::14 29624 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::15 29606 # Track reads on a per bank basis

62system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::3 4102 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::4 4129 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::5 4105 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::6 4104 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::7 4141 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::8 4162 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::9 4162 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis
78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

80system.physmem.totGap 624867514500 # Total gap between requests

80system.physmem.totGap 625047219500 # Total gap between requests

81system.physmem.readPktSize::0 0 # Categorize read packet sizes
82system.physmem.readPktSize::1 0 # Categorize read packet sizes
83system.physmem.readPktSize::2 0 # Categorize read packet sizes
84system.physmem.readPktSize::3 0 # Categorize read packet sizes
85system.physmem.readPktSize::4 0 # Categorize read packet sizes
86system.physmem.readPktSize::5 0 # Categorize read packet sizes
87system.physmem.readPktSize::6 474974 # Categorize read packet sizes
88system.physmem.readPktSize::7 0 # Categorize read packet sizes

--- 8 unchanged lines hidden (view full) ---

97system.physmem.writePktSize::7 0 # categorize write packet sizes
98system.physmem.writePktSize::8 0 # categorize write packet sizes
99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes

105system.physmem.neitherpktsize::6 4330 # categorize neither packet sizes

105system.physmem.neitherpktsize::6 4340 # categorize neither packet sizes

106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes

108system.physmem.rdQLenPdf::0 407769 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::1 66657 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::2 297 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see

108system.physmem.rdQLenPdf::0 407751 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::1 66647 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::2 302 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see

113system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see

114system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see

114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see

115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see

--- 43 unchanged lines hidden (view full) ---

166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see

174system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays
175system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests
176system.physmem.totBusLat 1899312000 # Total cycles spent in databus access
177system.physmem.totBankLat 12874638000 # Total cycles spent in bank access
178system.physmem.avgQLat 6984.13 # Average queueing delay per request
179system.physmem.avgBankLat 27114.32 # Average bank access latency per request

174system.physmem.totQLat 3340611483 # Total cycles spent in queuing delays
175system.physmem.totMemAccLat 18115671483 # Sum of mem lat for all requests
176system.physmem.totBusLat 1899232000 # Total cycles spent in databus access
177system.physmem.totBankLat 12875828000 # Total cycles spent in bank access
178system.physmem.avgQLat 7035.71 # Average queueing delay per request
179system.physmem.avgBankLat 27117.97 # Average bank access latency per request

180system.physmem.avgBusLat 4000.00 # Average bus latency per request

181system.physmem.avgMemAccLat 38098.44 # Average memory access latency
182system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s

181system.physmem.avgMemAccLat 38153.68 # Average memory access latency
182system.physmem.avgRdBW 48.63 # Average achieved read bandwidth in MB/s

183system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s

184system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s

184system.physmem.avgConsumedRdBW 48.63 # Average consumed read bandwidth in MB/s

185system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s
186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
187system.physmem.busUtil 0.35 # Data bus utilization in percentage
188system.physmem.avgRdQLen 0.03 # Average read queue length over time

189system.physmem.avgWrQLen 17.43 # Average write queue length over time
190system.physmem.readRowHits 249202 # Number of row buffer hits during reads
191system.physmem.writeRowHits 48033 # Number of row buffer hits during writes
192system.physmem.readRowHitRate 52.48 # Row buffer hit rate for reads

189system.physmem.avgWrQLen 17.44 # Average write queue length over time
190system.physmem.readRowHits 249146 # Number of row buffer hits during reads
191system.physmem.writeRowHits 48036 # Number of row buffer hits during writes
192system.physmem.readRowHitRate 52.47 # Row buffer hit rate for reads

193system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes

194system.physmem.avgGap 1154869.43 # Average gap between requests

194system.physmem.avgGap 1155201.56 # Average gap between requests

195system.cpu.dtb.inst_hits 0 # ITB inst hits
196system.cpu.dtb.inst_misses 0 # ITB inst misses
197system.cpu.dtb.read_hits 0 # DTB read hits
198system.cpu.dtb.read_misses 0 # DTB read misses
199system.cpu.dtb.write_hits 0 # DTB write hits
200system.cpu.dtb.write_misses 0 # DTB write misses
201system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
202system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 27 unchanged lines hidden (view full) ---

230system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
231system.cpu.itb.read_accesses 0 # DTB read accesses
232system.cpu.itb.write_accesses 0 # DTB write accesses
233system.cpu.itb.inst_accesses 0 # ITB inst accesses
234system.cpu.itb.hits 0 # DTB hits
235system.cpu.itb.misses 0 # DTB misses
236system.cpu.itb.accesses 0 # DTB accesses
237system.cpu.workload.num_syscalls 1411 # Number of system calls

238system.cpu.numCycles 1249735172 # number of cpu cycles simulated

238system.cpu.numCycles 1250094591 # number of cpu cycles simulated

239system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
240system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

241system.cpu.BPredUnit.lookups 439117025 # Number of BP lookups
242system.cpu.BPredUnit.condPredicted 350578524 # Number of conditional branches predicted
243system.cpu.BPredUnit.condIncorrect 30630316 # Number of conditional branches incorrect
244system.cpu.BPredUnit.BTBLookups 248764319 # Number of BTB lookups
245system.cpu.BPredUnit.BTBHits 227490785 # Number of BTB hits

241system.cpu.BPredUnit.lookups 438808047 # Number of BP lookups
242system.cpu.BPredUnit.condPredicted 349805436 # Number of conditional branches predicted
243system.cpu.BPredUnit.condIncorrect 30625316 # Number of conditional branches incorrect
244system.cpu.BPredUnit.BTBLookups 249957064 # Number of BTB lookups
245system.cpu.BPredUnit.BTBHits 227370417 # Number of BTB hits

246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

247system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target.
248system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions.
249system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss
250system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed
251system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered
252system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken
253system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked
254system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing
255system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked
256system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
257system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps
258system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR
259system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched
260system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed
261system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total)
262system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total)
263system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total)

247system.cpu.BPredUnit.usedRAS 52357585 # Number of times the RAS was used to get a target.
248system.cpu.BPredUnit.RASInCorrect 2806128 # Number of incorrect RAS predictions.
249system.cpu.fetch.icacheStallCycles 353851966 # Number of cycles fetch is stalled on an Icache miss
250system.cpu.fetch.Insts 2287455875 # Number of instructions fetch has processed
251system.cpu.fetch.Branches 438808047 # Number of branches that fetch encountered
252system.cpu.fetch.predictedBranches 279728002 # Number of branches that fetch has predicted taken
253system.cpu.fetch.Cycles 600743262 # Number of cycles fetch has run and was not squashing or blocked
254system.cpu.fetch.SquashCycles 158308312 # Number of cycles fetch has spent squashing
255system.cpu.fetch.BlockedCycles 133148695 # Number of cycles fetch has spent blocked
256system.cpu.fetch.MiscStallCycles 568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
257system.cpu.fetch.PendingTrapStallCycles 11515 # Number of stall cycles due to pending traps
258system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR
259system.cpu.fetch.CacheLines 333206369 # Number of cache lines fetched
260system.cpu.fetch.IcacheSquashes 10414827 # Number of outstanding Icache misses that were squashed
261system.cpu.fetch.rateDist::samples 1215386936 # Number of instructions fetched each cycle (Total)
262system.cpu.fetch.rateDist::mean 2.589820 # Number of instructions fetched each cycle (Total)
263system.cpu.fetch.rateDist::stdev 3.189306 # Number of instructions fetched each cycle (Total)

264system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

265system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total)
266system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total)
267system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total)
268system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total)
269system.cpu.fetch.rateDist::4 72457573 5.96% 72.48% # Number of instructions fetched each cycle (Total)
270system.cpu.fetch.rateDist::5 42599927 3.51% 75.99% # Number of instructions fetched each cycle (Total)
271system.cpu.fetch.rateDist::6 31039765 2.55% 78.54% # Number of instructions fetched each cycle (Total)
272system.cpu.fetch.rateDist::7 31697654 2.61% 81.15% # Number of instructions fetched each cycle (Total)
273system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Number of instructions fetched each cycle (Total)

265system.cpu.fetch.rateDist::0 614688205 50.58% 50.58% # Number of instructions fetched each cycle (Total)
266system.cpu.fetch.rateDist::1 42445352 3.49% 54.07% # Number of instructions fetched each cycle (Total)
267system.cpu.fetch.rateDist::2 95116159 7.83% 61.89% # Number of instructions fetched each cycle (Total)
268system.cpu.fetch.rateDist::3 55675580 4.58% 66.47% # Number of instructions fetched each cycle (Total)
269system.cpu.fetch.rateDist::4 72776602 5.99% 72.46% # Number of instructions fetched each cycle (Total)
270system.cpu.fetch.rateDist::5 42276531 3.48% 75.94% # Number of instructions fetched each cycle (Total)
271system.cpu.fetch.rateDist::6 31131234 2.56% 78.50% # Number of instructions fetched each cycle (Total)
272system.cpu.fetch.rateDist::7 31565180 2.60% 81.10% # Number of instructions fetched each cycle (Total)
273system.cpu.fetch.rateDist::8 229712093 18.90% 100.00% # Number of instructions fetched each cycle (Total)

274system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
275system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
276system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

277system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total)
278system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle
279system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle
280system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle
281system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked
282system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running
283system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking
284system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing
285system.cpu.decode.BranchResolved 44615078 # Number of times decode resolved a branch
286system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction
287system.cpu.decode.DecodedInsts 3041090435 # Number of instructions handled by decode
288system.cpu.decode.SquashedInsts 27022 # Number of squashed instructions handled by decode
289system.cpu.rename.SquashCycles 127217578 # Number of cycles rename is squashing
290system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle
291system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking
292system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst
293system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running
294system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking
295system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename
296system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full
297system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full
298system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full
299system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed
300system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made
301system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups
302system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups
303system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed
304system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing
305system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed
306system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed
307system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer
308system.cpu.memDep0.insertedLoads 972715984 # Number of loads inserted to the mem dependence unit.
309system.cpu.memDep0.insertedStores 490205592 # Number of stores inserted to the mem dependence unit.
310system.cpu.memDep0.conflictingLoads 36288460 # Number of conflicting loads.
311system.cpu.memDep0.conflictingStores 40771047 # Number of conflicting stores.
312system.cpu.iq.iqInstsAdded 2804297042 # Number of instructions added to the IQ (excludes non-spec)
313system.cpu.iq.iqNonSpecInstsAdded 31006 # Number of non-speculative instructions added to the IQ
314system.cpu.iq.iqInstsIssued 2436370950 # Number of instructions issued
315system.cpu.iq.iqSquashedInstsIssued 13311855 # Number of squashed instructions issued
316system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling
317system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph
318system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed
319system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle
320system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle
321system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle

277system.cpu.fetch.rateDist::total 1215386936 # Number of instructions fetched each cycle (Total)
278system.cpu.fetch.branchRate 0.351020 # Number of branch fetches per cycle
279system.cpu.fetch.rate 1.829826 # Number of inst fetches per cycle
280system.cpu.decode.IdleCycles 402796361 # Number of cycles decode is idle
281system.cpu.decode.BlockedCycles 106301870 # Number of cycles decode is blocked
282system.cpu.decode.RunCycles 561862491 # Number of cycles decode is running
283system.cpu.decode.UnblockCycles 16807396 # Number of cycles decode is unblocking
284system.cpu.decode.SquashCycles 127618818 # Number of cycles decode is squashing
285system.cpu.decode.BranchResolved 44638184 # Number of times decode resolved a branch
286system.cpu.decode.BranchMispred 12819 # Number of times decode detected a branch misprediction
287system.cpu.decode.DecodedInsts 3046676123 # Number of instructions handled by decode
288system.cpu.decode.SquashedInsts 27895 # Number of squashed instructions handled by decode
289system.cpu.rename.SquashCycles 127618818 # Number of cycles rename is squashing
290system.cpu.rename.IdleCycles 438124604 # Number of cycles rename is idle
291system.cpu.rename.BlockCycles 35349497 # Number of cycles rename is blocking
292system.cpu.rename.serializeStallCycles 425259 # count of cycles rename stalled for serializing inst
293system.cpu.rename.RunCycles 541326873 # Number of cycles rename is running
294system.cpu.rename.UnblockCycles 72541885 # Number of cycles rename is unblocking
295system.cpu.rename.RenamedInsts 2975830632 # Number of instructions processed by rename
296system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full
297system.cpu.rename.IQFullEvents 4806802 # Number of times rename has blocked due to IQ full
298system.cpu.rename.LSQFullEvents 56918075 # Number of times rename has blocked due to LSQ full
299system.cpu.rename.RenamedOperands 2945274289 # Number of destination operands rename has renamed
300system.cpu.rename.RenameLookups 14167459331 # Number of register rename lookups that rename has made
301system.cpu.rename.int_rename_lookups 13596684512 # Number of integer rename lookups
302system.cpu.rename.fp_rename_lookups 570774819 # Number of floating rename lookups
303system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
304system.cpu.rename.UndoneMaps 952134199 # Number of HB maps that are undone due to squashing
305system.cpu.rename.serializingInsts 23805 # count of serializing insts renamed
306system.cpu.rename.tempSerializingInsts 21281 # count of temporary serializing insts renamed
307system.cpu.rename.skidInsts 197120926 # count of insts added to the skid buffer
308system.cpu.memDep0.insertedLoads 972834043 # Number of loads inserted to the mem dependence unit.
309system.cpu.memDep0.insertedStores 492760757 # Number of stores inserted to the mem dependence unit.
310system.cpu.memDep0.conflictingLoads 36385181 # Number of conflicting loads.
311system.cpu.memDep0.conflictingStores 42690468 # Number of conflicting stores.
312system.cpu.iq.iqInstsAdded 2809386355 # Number of instructions added to the IQ (excludes non-spec)
313system.cpu.iq.iqNonSpecInstsAdded 28039 # Number of non-speculative instructions added to the IQ
314system.cpu.iq.iqInstsIssued 2437787250 # Number of instructions issued
315system.cpu.iq.iqSquashedInstsIssued 13304140 # Number of squashed instructions issued
316system.cpu.iq.iqSquashedInstsExamined 911537771 # Number of squashed instructions iterated over during squash; mainly for profiling
317system.cpu.iq.iqSquashedOperandsExamined 2374413817 # Number of squashed operands that are examined and possibly removed from graph
318system.cpu.iq.iqSquashedNonSpecRemoved 6655 # Number of squashed non-spec instructions that were removed
319system.cpu.iq.issued_per_cycle::samples 1215386936 # Number of insts issued each cycle
320system.cpu.iq.issued_per_cycle::mean 2.005770 # Number of insts issued each cycle
321system.cpu.iq.issued_per_cycle::stdev 1.875210 # Number of insts issued each cycle

322system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

323system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle
324system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle
325system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle
326system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle
327system.cpu.iq.issued_per_cycle::4 132635579 10.92% 87.90% # Number of insts issued each cycle
328system.cpu.iq.issued_per_cycle::5 93723777 7.71% 95.61% # Number of insts issued each cycle
329system.cpu.iq.issued_per_cycle::6 37883178 3.12% 98.73% # Number of insts issued each cycle
330system.cpu.iq.issued_per_cycle::7 12361449 1.02% 99.75% # Number of insts issued each cycle
331system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Number of insts issued each cycle

323system.cpu.iq.issued_per_cycle::0 379434397 31.22% 31.22% # Number of insts issued each cycle
324system.cpu.iq.issued_per_cycle::1 183109361 15.07% 46.29% # Number of insts issued each cycle
325system.cpu.iq.issued_per_cycle::2 202931100 16.70% 62.98% # Number of insts issued each cycle
326system.cpu.iq.issued_per_cycle::3 170113731 14.00% 76.98% # Number of insts issued each cycle
327system.cpu.iq.issued_per_cycle::4 132526126 10.90% 87.88% # Number of insts issued each cycle
328system.cpu.iq.issued_per_cycle::5 93839529 7.72% 95.60% # Number of insts issued each cycle
329system.cpu.iq.issued_per_cycle::6 37911750 3.12% 98.72% # Number of insts issued each cycle
330system.cpu.iq.issued_per_cycle::7 12465689 1.03% 99.75% # Number of insts issued each cycle
331system.cpu.iq.issued_per_cycle::8 3055253 0.25% 100.00% # Number of insts issued each cycle

332system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
333system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
334system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

335system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle

335system.cpu.iq.issued_per_cycle::total 1215386936 # Number of insts issued each cycle

336system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

337system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available
338system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available

337system.cpu.iq.fu_full::IntAlu 714674 0.82% 0.82% # attempts to use FU when none available
338system.cpu.iq.fu_full::IntMult 24388 0.03% 0.84% # attempts to use FU when none available

339system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
340system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
341system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
342system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
343system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
344system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
345system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
346system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available

--- 11 unchanged lines hidden (view full) ---

358system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
360system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
361system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
362system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
363system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available

366system.cpu.iq.fu_full::MemRead 55143304 62.90% 63.75% # attempts to use FU when none available
367system.cpu.iq.fu_full::MemWrite 31782308 36.25% 100.00% # attempts to use FU when none available

366system.cpu.iq.fu_full::MemRead 55116913 62.89% 63.74% # attempts to use FU when none available
367system.cpu.iq.fu_full::MemWrite 31779800 36.26% 100.00% # attempts to use FU when none available

368system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
369system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
370system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

371system.cpu.iq.FU_type_0::IntAlu 1107294192 45.45% 45.45% # Type of FU issued
372system.cpu.iq.FU_type_0::IntMult 11224034 0.46% 45.91% # Type of FU issued
373system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.91% # Type of FU issued
374system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.91% # Type of FU issued
375system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.91% # Type of FU issued
376system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.91% # Type of FU issued
377system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.91% # Type of FU issued
378system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.91% # Type of FU issued
379system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.91% # Type of FU issued
380system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.91% # Type of FU issued
381system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.91% # Type of FU issued
382system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.91% # Type of FU issued
383system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.91% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.91% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.91% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.91% # Type of FU issued
387system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.91% # Type of FU issued
388system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.91% # Type of FU issued
389system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.91% # Type of FU issued
390system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.91% # Type of FU issued
391system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.97% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.97% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.25% # Type of FU issued
394system.cpu.iq.FU_type_0::SimdFloatCvt 5502357 0.23% 46.47% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.47% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdFloatMisc 23404551 0.96% 47.43% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.43% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued
400system.cpu.iq.FU_type_0::MemRead 838357967 34.41% 81.84% # Type of FU issued
401system.cpu.iq.FU_type_0::MemWrite 442336083 18.16% 100.00% # Type of FU issued

371system.cpu.iq.FU_type_0::IntAlu 1108876695 45.49% 45.49% # Type of FU issued
372system.cpu.iq.FU_type_0::IntMult 11224297 0.46% 45.95% # Type of FU issued
373system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.95% # Type of FU issued
374system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.95% # Type of FU issued
375system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.95% # Type of FU issued
376system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.95% # Type of FU issued
377system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.95% # Type of FU issued
378system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.95% # Type of FU issued
379system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.95% # Type of FU issued
380system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.95% # Type of FU issued
381system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.95% # Type of FU issued
382system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.95% # Type of FU issued
383system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.95% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.95% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.95% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.95% # Type of FU issued
387system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.95% # Type of FU issued
388system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.95% # Type of FU issued
389system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.95% # Type of FU issued
390system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.95% # Type of FU issued
391system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.00% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.00% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.29% # Type of FU issued
394system.cpu.iq.FU_type_0::SimdFloatCvt 5502220 0.23% 46.51% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.51% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdFloatMisc 23416324 0.96% 47.47% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued
400system.cpu.iq.FU_type_0::MemRead 838276108 34.39% 81.86% # Type of FU issued
401system.cpu.iq.FU_type_0::MemWrite 442239839 18.14% 100.00% # Type of FU issued

402system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
403system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

404system.cpu.iq.FU_type_0::total 2436370950 # Type of FU issued
405system.cpu.iq.rate 1.949510 # Inst issue rate
406system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested
407system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst)
408system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads
409system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes
410system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses
411system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads
412system.cpu.iq.fp_inst_queue_writes 82717236 # Number of floating instruction queue writes
413system.cpu.iq.fp_inst_queue_wakeup_accesses 56437909 # Number of floating instruction queue wakeup accesses
414system.cpu.iq.int_alu_accesses 2460715459 # Number of integer alu accesses
415system.cpu.iq.fp_alu_accesses 63320089 # Number of floating point alu accesses
416system.cpu.iew.lsq.thread0.forwLoads 84361835 # Number of loads that had data forwarded from stores

404system.cpu.iq.FU_type_0::total 2437787250 # Type of FU issued
405system.cpu.iq.rate 1.950082 # Inst issue rate
406system.cpu.iq.fu_busy_cnt 87635775 # FU busy when requested
407system.cpu.iq.fu_busy_rate 0.035949 # FU busy rate (busy events/executed inst)
408system.cpu.iq.int_inst_queue_reads 6069393440 # Number of integer instruction queue reads
409system.cpu.iq.int_inst_queue_writes 3638225906 # Number of integer instruction queue writes
410system.cpu.iq.int_inst_queue_wakeup_accesses 2254362609 # Number of integer instruction queue wakeup accesses
411system.cpu.iq.fp_inst_queue_reads 122507911 # Number of floating instruction queue reads
412system.cpu.iq.fp_inst_queue_writes 82793715 # Number of floating instruction queue writes
413system.cpu.iq.fp_inst_queue_wakeup_accesses 56449336 # Number of floating instruction queue wakeup accesses
414system.cpu.iq.int_alu_accesses 2462106345 # Number of integer alu accesses
415system.cpu.iq.fp_alu_accesses 63316680 # Number of floating point alu accesses
416system.cpu.iew.lsq.thread0.forwLoads 84343916 # Number of loads that had data forwarded from stores

417system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

418system.cpu.iew.lsq.thread0.squashedLoads 341327109 # Number of loads squashed
419system.cpu.iew.lsq.thread0.ignoredResponses 8250 # Number of memory responses ignored because the instruction is squashed
420system.cpu.iew.lsq.thread0.memOrderViolation 1428808 # Number of memory ordering violations
421system.cpu.iew.lsq.thread0.squashedStores 213208601 # Number of stores squashed

418system.cpu.iew.lsq.thread0.squashedLoads 341446862 # Number of loads squashed
419system.cpu.iew.lsq.thread0.ignoredResponses 7743 # Number of memory responses ignored because the instruction is squashed
420system.cpu.iew.lsq.thread0.memOrderViolation 1429272 # Number of memory ordering violations
421system.cpu.iew.lsq.thread0.squashedStores 215765460 # Number of stores squashed

422system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
423system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
424system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled

425system.cpu.iew.lsq.thread0.cacheBlocked 221 # Number of times an access to memory failed due to the cache being blocked

425system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked

426system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

427system.cpu.iew.iewSquashCycles 127217578 # Number of cycles IEW is squashing
428system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking
429system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking
430system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ
431system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch
432system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions
433system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions
434system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions
435system.cpu.iew.iewIQFullEvents 1558593 # Number of times the IQ has become full, causing a stall
436system.cpu.iew.iewLSQFullEvents 2526 # Number of times the LSQ has become full, causing a stall
437system.cpu.iew.memOrderViolationEvents 1428808 # Number of memory order violations
438system.cpu.iew.predictedTakenIncorrect 32521161 # Number of branches that were predicted taken incorrectly
439system.cpu.iew.predictedNotTakenIncorrect 1512713 # Number of branches that were predicted not taken incorrectly
440system.cpu.iew.branchMispredicts 34033874 # Number of branch mispredicts detected at execute
441system.cpu.iew.iewExecutedInsts 2362219907 # Number of executed instructions
442system.cpu.iew.iewExecLoadInsts 792646926 # Number of load instructions executed
443system.cpu.iew.iewExecSquashedInsts 74151043 # Number of squashed instructions skipped in execute

427system.cpu.iew.iewSquashCycles 127618818 # Number of cycles IEW is squashing
428system.cpu.iew.iewBlockCycles 13752826 # Number of cycles IEW is blocking
429system.cpu.iew.iewUnblockCycles 1562574 # Number of cycles IEW is unblocking
430system.cpu.iew.iewDispatchedInsts 2809426795 # Number of instructions dispatched to IQ
431system.cpu.iew.iewDispSquashedInsts 1398231 # Number of squashed instructions skipped by dispatch
432system.cpu.iew.iewDispLoadInsts 972834043 # Number of dispatched load instructions
433system.cpu.iew.iewDispStoreInsts 492760757 # Number of dispatched store instructions
434system.cpu.iew.iewDispNonSpecInsts 18053 # Number of dispatched non-speculative instructions
435system.cpu.iew.iewIQFullEvents 1558945 # Number of times the IQ has become full, causing a stall
436system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall
437system.cpu.iew.memOrderViolationEvents 1429272 # Number of memory order violations
438system.cpu.iew.predictedTakenIncorrect 32529008 # Number of branches that were predicted taken incorrectly
439system.cpu.iew.predictedNotTakenIncorrect 1513965 # Number of branches that were predicted not taken incorrectly
440system.cpu.iew.branchMispredicts 34042973 # Number of branch mispredicts detected at execute
441system.cpu.iew.iewExecutedInsts 2363631235 # Number of executed instructions
442system.cpu.iew.iewExecLoadInsts 792642751 # Number of load instructions executed
443system.cpu.iew.iewExecSquashedInsts 74156015 # Number of squashed instructions skipped in execute

444system.cpu.iew.exec_swp 0 # number of swp insts executed

445system.cpu.iew.exec_nop 12429 # number of nop insts executed
446system.cpu.iew.exec_refs 1216288233 # number of memory reference insts executed
447system.cpu.iew.exec_branches 322226431 # Number of branches executed
448system.cpu.iew.exec_stores 423641307 # Number of stores executed
449system.cpu.iew.exec_rate 1.890176 # Inst execution rate
450system.cpu.iew.wb_sent 2335115057 # cumulative count of insts sent to commit
451system.cpu.iew.wb_count 2309436326 # cumulative count of insts written-back
452system.cpu.iew.wb_producers 1347701281 # num instructions producing a value
453system.cpu.iew.wb_consumers 2523709653 # num instructions consuming a value

445system.cpu.iew.exec_nop 12401 # number of nop insts executed
446system.cpu.iew.exec_refs 1216279993 # number of memory reference insts executed
447system.cpu.iew.exec_branches 322475744 # Number of branches executed
448system.cpu.iew.exec_stores 423637242 # Number of stores executed
449system.cpu.iew.exec_rate 1.890762 # Inst execution rate
450system.cpu.iew.wb_sent 2336496726 # cumulative count of insts sent to commit
451system.cpu.iew.wb_count 2310811945 # cumulative count of insts written-back
452system.cpu.iew.wb_producers 1347866502 # num instructions producing a value
453system.cpu.iew.wb_consumers 2524860722 # num instructions consuming a value

454system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

455system.cpu.iew.wb_rate 1.847941 # insts written-back per cycle
456system.cpu.iew.wb_fanout 0.534016 # average fanout of values written-back

455system.cpu.iew.wb_rate 1.848510 # insts written-back per cycle
456system.cpu.iew.wb_fanout 0.533838 # average fanout of values written-back

457system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

458system.cpu.commit.commitSquashedInsts 918995782 # The number of squashed insts skipped by commit
459system.cpu.commit.commitNonSpecStalls 23078 # The number of times commit has been forced to stall to communicate backwards
460system.cpu.commit.branchMispredicts 30617997 # The number of times a branch was mispredicted
461system.cpu.commit.committed_per_cycle::samples 1087855788 # Number of insts commited each cycle
462system.cpu.commit.committed_per_cycle::mean 1.733083 # Number of insts commited each cycle
463system.cpu.commit.committed_per_cycle::stdev 2.398277 # Number of insts commited each cycle

458system.cpu.commit.commitSquashedInsts 924090552 # The number of squashed insts skipped by commit
459system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
460system.cpu.commit.branchMispredicts 30613261 # The number of times a branch was mispredicted
461system.cpu.commit.committed_per_cycle::samples 1087768118 # Number of insts commited each cycle
462system.cpu.commit.committed_per_cycle::mean 1.733215 # Number of insts commited each cycle
463system.cpu.commit.committed_per_cycle::stdev 2.398367 # Number of insts commited each cycle

464system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

465system.cpu.commit.committed_per_cycle::0 447553397 41.14% 41.14% # Number of insts commited each cycle
466system.cpu.commit.committed_per_cycle::1 288592120 26.53% 67.67% # Number of insts commited each cycle
467system.cpu.commit.committed_per_cycle::2 95115403 8.74% 76.41% # Number of insts commited each cycle
468system.cpu.commit.committed_per_cycle::3 70228058 6.46% 82.87% # Number of insts commited each cycle
469system.cpu.commit.committed_per_cycle::4 46464545 4.27% 87.14% # Number of insts commited each cycle
470system.cpu.commit.committed_per_cycle::5 22184894 2.04% 89.18% # Number of insts commited each cycle
471system.cpu.commit.committed_per_cycle::6 15849617 1.46% 90.64% # Number of insts commited each cycle
472system.cpu.commit.committed_per_cycle::7 10984656 1.01% 91.65% # Number of insts commited each cycle
473system.cpu.commit.committed_per_cycle::8 90883098 8.35% 100.00% # Number of insts commited each cycle

465system.cpu.commit.committed_per_cycle::0 447474994 41.14% 41.14% # Number of insts commited each cycle
466system.cpu.commit.committed_per_cycle::1 288616071 26.53% 67.67% # Number of insts commited each cycle
467system.cpu.commit.committed_per_cycle::2 95091930 8.74% 76.41% # Number of insts commited each cycle
468system.cpu.commit.committed_per_cycle::3 70192926 6.45% 82.86% # Number of insts commited each cycle
469system.cpu.commit.committed_per_cycle::4 46475898 4.27% 87.14% # Number of insts commited each cycle
470system.cpu.commit.committed_per_cycle::5 22197093 2.04% 89.18% # Number of insts commited each cycle
471system.cpu.commit.committed_per_cycle::6 15849951 1.46% 90.64% # Number of insts commited each cycle
472system.cpu.commit.committed_per_cycle::7 10985154 1.01% 91.64% # Number of insts commited each cycle
473system.cpu.commit.committed_per_cycle::8 90884101 8.36% 100.00% # Number of insts commited each cycle

474system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
475system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
476system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

477system.cpu.commit.committed_per_cycle::total 1087855788 # Number of insts commited each cycle
478system.cpu.commit.committedInsts 1384390076 # Number of instructions committed
479system.cpu.commit.committedOps 1885344828 # Number of ops (including micro ops) committed

477system.cpu.commit.committed_per_cycle::total 1087768118 # Number of insts commited each cycle
478system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
479system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed

480system.cpu.commit.swp_count 0 # Number of s/w prefetches committed

481system.cpu.commit.refs 908385866 # Number of memory references committed
482system.cpu.commit.loads 631388875 # Number of loads committed

481system.cpu.commit.refs 908382478 # Number of memory references committed
482system.cpu.commit.loads 631387181 # Number of loads committed

483system.cpu.commit.membars 9986 # Number of memory barriers committed

484system.cpu.commit.branches 299636089 # Number of branches committed

484system.cpu.commit.branches 299634395 # Number of branches committed

485system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.

486system.cpu.commit.int_insts 1653705643 # Number of committed integer instructions.

486system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.

487system.cpu.commit.function_calls 41577833 # Number of function calls committed.

488system.cpu.commit.bw_lim_events 90883098 # number cycles where commit BW limit reached

488system.cpu.commit.bw_lim_events 90884101 # number cycles where commit BW limit reached

489system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

490system.cpu.rob.rob_reads 3801294955 # The number of ROB reads
491system.cpu.rob.rob_writes 5735909866 # The number of ROB writes
492system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself
493system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling
494system.cpu.committedInsts 1384379060 # Number of Instructions Simulated
495system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated
496system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated
497system.cpu.cpi 0.902741 # CPI: Cycles Per Instruction
498system.cpu.cpi_total 0.902741 # CPI: Total CPI of All Threads
499system.cpu.ipc 1.107738 # IPC: Instructions Per Cycle
500system.cpu.ipc_total 1.107738 # IPC: Total IPC of All Threads
501system.cpu.int_regfile_reads 11770471325 # number of integer regfile reads
502system.cpu.int_regfile_writes 2224868034 # number of integer regfile writes
503system.cpu.fp_regfile_reads 68796296 # number of floating regfile reads
504system.cpu.fp_regfile_writes 49549961 # number of floating regfile writes
505system.cpu.misc_regfile_reads 1363964167 # number of misc regfile reads
506system.cpu.misc_regfile_writes 13776290 # number of misc regfile writes
507system.cpu.icache.replacements 22546 # number of replacements
508system.cpu.icache.tagsinuse 1642.542137 # Cycle average of tags in use
509system.cpu.icache.total_refs 333790581 # Total number of references to valid blocks.
510system.cpu.icache.sampled_refs 24232 # Sample count of references to valid blocks.
511system.cpu.icache.avg_refs 13774.784624 # Average number of references to valid blocks.

490system.cpu.rob.rob_reads 3806292582 # The number of ROB reads
491system.cpu.rob.rob_writes 5746483501 # The number of ROB writes
492system.cpu.timesIdled 353075 # Number of times that the entire CPU went into an idle state and unscheduled itself
493system.cpu.idleCycles 34707655 # Total number of cycles that the CPU has spent unscheduled due to idling
494system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
495system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
496system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
497system.cpu.cpi 0.903006 # CPI: Cycles Per Instruction
498system.cpu.cpi_total 0.903006 # CPI: Total CPI of All Threads
499system.cpu.ipc 1.107413 # IPC: Instructions Per Cycle
500system.cpu.ipc_total 1.107413 # IPC: Total IPC of All Threads
501system.cpu.int_regfile_reads 11775193288 # number of integer regfile reads
502system.cpu.int_regfile_writes 2227107160 # number of integer regfile writes
503system.cpu.fp_regfile_reads 68795849 # number of floating regfile reads
504system.cpu.fp_regfile_writes 49561296 # number of floating regfile writes
505system.cpu.misc_regfile_reads 1363965830 # number of misc regfile reads
506system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
507system.cpu.icache.replacements 22468 # number of replacements
508system.cpu.icache.tagsinuse 1641.255803 # Cycle average of tags in use
509system.cpu.icache.total_refs 333171598 # Total number of references to valid blocks.
510system.cpu.icache.sampled_refs 24150 # Sample count of references to valid blocks.
511system.cpu.icache.avg_refs 13795.925383 # Average number of references to valid blocks.

512system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

513system.cpu.icache.occ_blocks::cpu.inst 1642.542137 # Average occupied blocks per requestor
514system.cpu.icache.occ_percent::cpu.inst 0.802023 # Average percentage of cache occupancy
515system.cpu.icache.occ_percent::total 0.802023 # Average percentage of cache occupancy
516system.cpu.icache.ReadReq_hits::cpu.inst 333794637 # number of ReadReq hits
517system.cpu.icache.ReadReq_hits::total 333794637 # number of ReadReq hits
518system.cpu.icache.demand_hits::cpu.inst 333794637 # number of demand (read+write) hits
519system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits
520system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits
521system.cpu.icache.overall_hits::total 333794637 # number of overall hits
522system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses
523system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses
524system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses
525system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses
526system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses
527system.cpu.icache.overall_misses::total 30837 # number of overall misses
528system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles
529system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles
530system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles
531system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles
532system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles
533system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles
534system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses)
535system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses)
536system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses
537system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses
538system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses
539system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses

513system.cpu.icache.occ_blocks::cpu.inst 1641.255803 # Average occupied blocks per requestor
514system.cpu.icache.occ_percent::cpu.inst 0.801394 # Average percentage of cache occupancy
515system.cpu.icache.occ_percent::total 0.801394 # Average percentage of cache occupancy
516system.cpu.icache.ReadReq_hits::cpu.inst 333175666 # number of ReadReq hits
517system.cpu.icache.ReadReq_hits::total 333175666 # number of ReadReq hits
518system.cpu.icache.demand_hits::cpu.inst 333175666 # number of demand (read+write) hits
519system.cpu.icache.demand_hits::total 333175666 # number of demand (read+write) hits
520system.cpu.icache.overall_hits::cpu.inst 333175666 # number of overall hits
521system.cpu.icache.overall_hits::total 333175666 # number of overall hits
522system.cpu.icache.ReadReq_misses::cpu.inst 30702 # number of ReadReq misses
523system.cpu.icache.ReadReq_misses::total 30702 # number of ReadReq misses
524system.cpu.icache.demand_misses::cpu.inst 30702 # number of demand (read+write) misses
525system.cpu.icache.demand_misses::total 30702 # number of demand (read+write) misses
526system.cpu.icache.overall_misses::cpu.inst 30702 # number of overall misses
527system.cpu.icache.overall_misses::total 30702 # number of overall misses
528system.cpu.icache.ReadReq_miss_latency::cpu.inst 468488500 # number of ReadReq miss cycles
529system.cpu.icache.ReadReq_miss_latency::total 468488500 # number of ReadReq miss cycles
530system.cpu.icache.demand_miss_latency::cpu.inst 468488500 # number of demand (read+write) miss cycles
531system.cpu.icache.demand_miss_latency::total 468488500 # number of demand (read+write) miss cycles
532system.cpu.icache.overall_miss_latency::cpu.inst 468488500 # number of overall miss cycles
533system.cpu.icache.overall_miss_latency::total 468488500 # number of overall miss cycles
534system.cpu.icache.ReadReq_accesses::cpu.inst 333206368 # number of ReadReq accesses(hits+misses)
535system.cpu.icache.ReadReq_accesses::total 333206368 # number of ReadReq accesses(hits+misses)
536system.cpu.icache.demand_accesses::cpu.inst 333206368 # number of demand (read+write) accesses
537system.cpu.icache.demand_accesses::total 333206368 # number of demand (read+write) accesses
538system.cpu.icache.overall_accesses::cpu.inst 333206368 # number of overall (read+write) accesses
539system.cpu.icache.overall_accesses::total 333206368 # number of overall (read+write) accesses

540system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
541system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
542system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
543system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
544system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
545system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses

546system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15233.615397 # average ReadReq miss latency
547system.cpu.icache.ReadReq_avg_miss_latency::total 15233.615397 # average ReadReq miss latency
548system.cpu.icache.demand_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
549system.cpu.icache.demand_avg_miss_latency::total 15233.615397 # average overall miss latency
550system.cpu.icache.overall_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
551system.cpu.icache.overall_avg_miss_latency::total 15233.615397 # average overall miss latency
552system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked

546system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15259.217641 # average ReadReq miss latency
547system.cpu.icache.ReadReq_avg_miss_latency::total 15259.217641 # average ReadReq miss latency
548system.cpu.icache.demand_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency
549system.cpu.icache.demand_avg_miss_latency::total 15259.217641 # average overall miss latency
550system.cpu.icache.overall_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency
551system.cpu.icache.overall_avg_miss_latency::total 15259.217641 # average overall miss latency
552system.cpu.icache.blocked_cycles::no_mshrs 1109 # number of cycles access was blocked

553system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

554system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked

554system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked

555system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

556system.cpu.icache.avg_blocked_cycles::no_mshrs 34.793103 # average number of cycles each access was blocked

556system.cpu.icache.avg_blocked_cycles::no_mshrs 39.607143 # average number of cycles each access was blocked

557system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
558system.cpu.icache.fast_writes 0 # number of fast writes performed
559system.cpu.icache.cache_copies 0 # number of cache copies performed

560system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2273 # number of ReadReq MSHR hits
561system.cpu.icache.ReadReq_mshr_hits::total 2273 # number of ReadReq MSHR hits
562system.cpu.icache.demand_mshr_hits::cpu.inst 2273 # number of demand (read+write) MSHR hits
563system.cpu.icache.demand_mshr_hits::total 2273 # number of demand (read+write) MSHR hits
564system.cpu.icache.overall_mshr_hits::cpu.inst 2273 # number of overall MSHR hits
565system.cpu.icache.overall_mshr_hits::total 2273 # number of overall MSHR hits
566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses
567system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses
568system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses
569system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses
570system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses
571system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses
572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379116998 # number of ReadReq MSHR miss cycles
573system.cpu.icache.ReadReq_mshr_miss_latency::total 379116998 # number of ReadReq MSHR miss cycles
574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379116998 # number of demand (read+write) MSHR miss cycles
575system.cpu.icache.demand_mshr_miss_latency::total 379116998 # number of demand (read+write) MSHR miss cycles
576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379116998 # number of overall MSHR miss cycles
577system.cpu.icache.overall_mshr_miss_latency::total 379116998 # number of overall MSHR miss cycles

560system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2210 # number of ReadReq MSHR hits
561system.cpu.icache.ReadReq_mshr_hits::total 2210 # number of ReadReq MSHR hits
562system.cpu.icache.demand_mshr_hits::cpu.inst 2210 # number of demand (read+write) MSHR hits
563system.cpu.icache.demand_mshr_hits::total 2210 # number of demand (read+write) MSHR hits
564system.cpu.icache.overall_mshr_hits::cpu.inst 2210 # number of overall MSHR hits
565system.cpu.icache.overall_mshr_hits::total 2210 # number of overall MSHR hits
566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28492 # number of ReadReq MSHR misses
567system.cpu.icache.ReadReq_mshr_misses::total 28492 # number of ReadReq MSHR misses
568system.cpu.icache.demand_mshr_misses::cpu.inst 28492 # number of demand (read+write) MSHR misses
569system.cpu.icache.demand_mshr_misses::total 28492 # number of demand (read+write) MSHR misses
570system.cpu.icache.overall_mshr_misses::cpu.inst 28492 # number of overall MSHR misses
571system.cpu.icache.overall_mshr_misses::total 28492 # number of overall MSHR misses
572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 377164000 # number of ReadReq MSHR miss cycles
573system.cpu.icache.ReadReq_mshr_miss_latency::total 377164000 # number of ReadReq MSHR miss cycles
574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 377164000 # number of demand (read+write) MSHR miss cycles
575system.cpu.icache.demand_mshr_miss_latency::total 377164000 # number of demand (read+write) MSHR miss cycles
576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 377164000 # number of overall MSHR miss cycles
577system.cpu.icache.overall_mshr_miss_latency::total 377164000 # number of overall MSHR miss cycles

578system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
579system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
580system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
581system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
582system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
583system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses

584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.545792 # average ReadReq mshr miss latency
585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.545792 # average ReadReq mshr miss latency
586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
587system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
589system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency

584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13237.540362 # average ReadReq mshr miss latency
585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13237.540362 # average ReadReq mshr miss latency
586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13237.540362 # average overall mshr miss latency
587system.cpu.icache.demand_avg_mshr_miss_latency::total 13237.540362 # average overall mshr miss latency
588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13237.540362 # average overall mshr miss latency
589system.cpu.icache.overall_avg_mshr_miss_latency::total 13237.540362 # average overall mshr miss latency

590system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

591system.cpu.l2cache.replacements 442193 # number of replacements
592system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use
593system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks.

591system.cpu.l2cache.replacements 442192 # number of replacements
592system.cpu.l2cache.tagsinuse 32688.738823 # Cycle average of tags in use
593system.cpu.l2cache.total_refs 1109575 # Total number of references to valid blocks.

594system.cpu.l2cache.sampled_refs 474940 # Sample count of references to valid blocks.

595system.cpu.l2cache.avg_refs 2.336548 # Average number of references to valid blocks.

595system.cpu.l2cache.avg_refs 2.336242 # Average number of references to valid blocks.

596system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

597system.cpu.l2cache.occ_blocks::writebacks 1294.928331 # Average occupied blocks per requestor
598system.cpu.l2cache.occ_blocks::cpu.inst 48.758922 # Average occupied blocks per requestor
599system.cpu.l2cache.occ_blocks::cpu.data 31344.836948 # Average occupied blocks per requestor
600system.cpu.l2cache.occ_percent::writebacks 0.039518 # Average percentage of cache occupancy
601system.cpu.l2cache.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy
602system.cpu.l2cache.occ_percent::cpu.data 0.956569 # Average percentage of cache occupancy
603system.cpu.l2cache.occ_percent::total 0.997575 # Average percentage of cache occupancy
604system.cpu.l2cache.ReadReq_hits::cpu.inst 21799 # number of ReadReq hits
605system.cpu.l2cache.ReadReq_hits::cpu.data 1058077 # number of ReadReq hits
606system.cpu.l2cache.ReadReq_hits::total 1079876 # number of ReadReq hits
607system.cpu.l2cache.Writeback_hits::writebacks 96322 # number of Writeback hits
608system.cpu.l2cache.Writeback_hits::total 96322 # number of Writeback hits

597system.cpu.l2cache.occ_blocks::writebacks 1295.493946 # Average occupied blocks per requestor
598system.cpu.l2cache.occ_blocks::cpu.inst 49.994068 # Average occupied blocks per requestor
599system.cpu.l2cache.occ_blocks::cpu.data 31343.250808 # Average occupied blocks per requestor
600system.cpu.l2cache.occ_percent::writebacks 0.039535 # Average percentage of cache occupancy
601system.cpu.l2cache.occ_percent::cpu.inst 0.001526 # Average percentage of cache occupancy
602system.cpu.l2cache.occ_percent::cpu.data 0.956520 # Average percentage of cache occupancy
603system.cpu.l2cache.occ_percent::total 0.997581 # Average percentage of cache occupancy
604system.cpu.l2cache.ReadReq_hits::cpu.inst 21719 # number of ReadReq hits
605system.cpu.l2cache.ReadReq_hits::cpu.data 1058021 # number of ReadReq hits
606system.cpu.l2cache.ReadReq_hits::total 1079740 # number of ReadReq hits
607system.cpu.l2cache.Writeback_hits::writebacks 96308 # number of Writeback hits
608system.cpu.l2cache.Writeback_hits::total 96308 # number of Writeback hits

609system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
610system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits

611system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits
612system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits
613system.cpu.l2cache.demand_hits::cpu.inst 21799 # number of demand (read+write) hits
614system.cpu.l2cache.demand_hits::cpu.data 1064518 # number of demand (read+write) hits
615system.cpu.l2cache.demand_hits::total 1086317 # number of demand (read+write) hits
616system.cpu.l2cache.overall_hits::cpu.inst 21799 # number of overall hits
617system.cpu.l2cache.overall_hits::cpu.data 1064518 # number of overall hits
618system.cpu.l2cache.overall_hits::total 1086317 # number of overall hits
619system.cpu.l2cache.ReadReq_misses::cpu.inst 2433 # number of ReadReq misses
620system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses
621system.cpu.l2cache.ReadReq_misses::total 408924 # number of ReadReq misses
622system.cpu.l2cache.UpgradeReq_misses::cpu.data 4330 # number of UpgradeReq misses
623system.cpu.l2cache.UpgradeReq_misses::total 4330 # number of UpgradeReq misses
624system.cpu.l2cache.ReadExReq_misses::cpu.data 66074 # number of ReadExReq misses
625system.cpu.l2cache.ReadExReq_misses::total 66074 # number of ReadExReq misses
626system.cpu.l2cache.demand_misses::cpu.inst 2433 # number of demand (read+write) misses
627system.cpu.l2cache.demand_misses::cpu.data 472565 # number of demand (read+write) misses
628system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses
629system.cpu.l2cache.overall_misses::cpu.inst 2433 # number of overall misses
630system.cpu.l2cache.overall_misses::cpu.data 472565 # number of overall misses
631system.cpu.l2cache.overall_misses::total 474998 # number of overall misses
632system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128013500 # number of ReadReq miss cycles
633system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837931500 # number of ReadReq miss cycles
634system.cpu.l2cache.ReadReq_miss_latency::total 25965945000 # number of ReadReq miss cycles
635system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242869000 # number of ReadExReq miss cycles
636system.cpu.l2cache.ReadExReq_miss_latency::total 3242869000 # number of ReadExReq miss cycles
637system.cpu.l2cache.demand_miss_latency::cpu.inst 128013500 # number of demand (read+write) miss cycles
638system.cpu.l2cache.demand_miss_latency::cpu.data 29080800500 # number of demand (read+write) miss cycles
639system.cpu.l2cache.demand_miss_latency::total 29208814000 # number of demand (read+write) miss cycles
640system.cpu.l2cache.overall_miss_latency::cpu.inst 128013500 # number of overall miss cycles
641system.cpu.l2cache.overall_miss_latency::cpu.data 29080800500 # number of overall miss cycles
642system.cpu.l2cache.overall_miss_latency::total 29208814000 # number of overall miss cycles
643system.cpu.l2cache.ReadReq_accesses::cpu.inst 24232 # number of ReadReq accesses(hits+misses)
644system.cpu.l2cache.ReadReq_accesses::cpu.data 1464568 # number of ReadReq accesses(hits+misses)
645system.cpu.l2cache.ReadReq_accesses::total 1488800 # number of ReadReq accesses(hits+misses)
646system.cpu.l2cache.Writeback_accesses::writebacks 96322 # number of Writeback accesses(hits+misses)
647system.cpu.l2cache.Writeback_accesses::total 96322 # number of Writeback accesses(hits+misses)
648system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4333 # number of UpgradeReq accesses(hits+misses)
649system.cpu.l2cache.UpgradeReq_accesses::total 4333 # number of UpgradeReq accesses(hits+misses)
650system.cpu.l2cache.ReadExReq_accesses::cpu.data 72515 # number of ReadExReq accesses(hits+misses)
651system.cpu.l2cache.ReadExReq_accesses::total 72515 # number of ReadExReq accesses(hits+misses)
652system.cpu.l2cache.demand_accesses::cpu.inst 24232 # number of demand (read+write) accesses
653system.cpu.l2cache.demand_accesses::cpu.data 1537083 # number of demand (read+write) accesses
654system.cpu.l2cache.demand_accesses::total 1561315 # number of demand (read+write) accesses
655system.cpu.l2cache.overall_accesses::cpu.inst 24232 # number of overall (read+write) accesses
656system.cpu.l2cache.overall_accesses::cpu.data 1537083 # number of overall (read+write) accesses
657system.cpu.l2cache.overall_accesses::total 1561315 # number of overall (read+write) accesses
658system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100404 # miss rate for ReadReq accesses
659system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277550 # miss rate for ReadReq accesses
660system.cpu.l2cache.ReadReq_miss_rate::total 0.274667 # miss rate for ReadReq accesses
661system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999308 # miss rate for UpgradeReq accesses
662system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999308 # miss rate for UpgradeReq accesses
663system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911177 # miss rate for ReadExReq accesses
664system.cpu.l2cache.ReadExReq_miss_rate::total 0.911177 # miss rate for ReadExReq accesses
665system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100404 # miss rate for demand accesses
666system.cpu.l2cache.demand_miss_rate::cpu.data 0.307443 # miss rate for demand accesses
667system.cpu.l2cache.demand_miss_rate::total 0.304229 # miss rate for demand accesses
668system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100404 # miss rate for overall accesses
669system.cpu.l2cache.overall_miss_rate::cpu.data 0.307443 # miss rate for overall accesses
670system.cpu.l2cache.overall_miss_rate::total 0.304229 # miss rate for overall accesses
671system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.495273 # average ReadReq miss latency
672system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.354416 # average ReadReq miss latency
673system.cpu.l2cache.ReadReq_avg_miss_latency::total 63498.217273 # average ReadReq miss latency
674system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.350425 # average ReadExReq miss latency
675system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.350425 # average ReadExReq miss latency
676system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
677system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency
678system.cpu.l2cache.demand_avg_miss_latency::total 61492.498916 # average overall miss latency
679system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
680system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency
681system.cpu.l2cache.overall_avg_miss_latency::total 61492.498916 # average overall miss latency

611system.cpu.l2cache.ReadExReq_hits::cpu.data 6442 # number of ReadExReq hits
612system.cpu.l2cache.ReadExReq_hits::total 6442 # number of ReadExReq hits
613system.cpu.l2cache.demand_hits::cpu.inst 21719 # number of demand (read+write) hits
614system.cpu.l2cache.demand_hits::cpu.data 1064463 # number of demand (read+write) hits
615system.cpu.l2cache.demand_hits::total 1086182 # number of demand (read+write) hits
616system.cpu.l2cache.overall_hits::cpu.inst 21719 # number of overall hits
617system.cpu.l2cache.overall_hits::cpu.data 1064463 # number of overall hits
618system.cpu.l2cache.overall_hits::total 1086182 # number of overall hits
619system.cpu.l2cache.ReadReq_misses::cpu.inst 2431 # number of ReadReq misses
620system.cpu.l2cache.ReadReq_misses::cpu.data 406497 # number of ReadReq misses
621system.cpu.l2cache.ReadReq_misses::total 408928 # number of ReadReq misses
622system.cpu.l2cache.UpgradeReq_misses::cpu.data 4340 # number of UpgradeReq misses
623system.cpu.l2cache.UpgradeReq_misses::total 4340 # number of UpgradeReq misses
624system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
625system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
626system.cpu.l2cache.demand_misses::cpu.inst 2431 # number of demand (read+write) misses
627system.cpu.l2cache.demand_misses::cpu.data 472572 # number of demand (read+write) misses
628system.cpu.l2cache.demand_misses::total 475003 # number of demand (read+write) misses
629system.cpu.l2cache.overall_misses::cpu.inst 2431 # number of overall misses
630system.cpu.l2cache.overall_misses::cpu.data 472572 # number of overall misses
631system.cpu.l2cache.overall_misses::total 475003 # number of overall misses
632system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 126924500 # number of ReadReq miss cycles
633system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25862108500 # number of ReadReq miss cycles
634system.cpu.l2cache.ReadReq_miss_latency::total 25989033000 # number of ReadReq miss cycles
635system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3246043000 # number of ReadExReq miss cycles
636system.cpu.l2cache.ReadExReq_miss_latency::total 3246043000 # number of ReadExReq miss cycles
637system.cpu.l2cache.demand_miss_latency::cpu.inst 126924500 # number of demand (read+write) miss cycles
638system.cpu.l2cache.demand_miss_latency::cpu.data 29108151500 # number of demand (read+write) miss cycles
639system.cpu.l2cache.demand_miss_latency::total 29235076000 # number of demand (read+write) miss cycles
640system.cpu.l2cache.overall_miss_latency::cpu.inst 126924500 # number of overall miss cycles
641system.cpu.l2cache.overall_miss_latency::cpu.data 29108151500 # number of overall miss cycles
642system.cpu.l2cache.overall_miss_latency::total 29235076000 # number of overall miss cycles
643system.cpu.l2cache.ReadReq_accesses::cpu.inst 24150 # number of ReadReq accesses(hits+misses)
644system.cpu.l2cache.ReadReq_accesses::cpu.data 1464518 # number of ReadReq accesses(hits+misses)
645system.cpu.l2cache.ReadReq_accesses::total 1488668 # number of ReadReq accesses(hits+misses)
646system.cpu.l2cache.Writeback_accesses::writebacks 96308 # number of Writeback accesses(hits+misses)
647system.cpu.l2cache.Writeback_accesses::total 96308 # number of Writeback accesses(hits+misses)
648system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4343 # number of UpgradeReq accesses(hits+misses)
649system.cpu.l2cache.UpgradeReq_accesses::total 4343 # number of UpgradeReq accesses(hits+misses)
650system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses)
651system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses)
652system.cpu.l2cache.demand_accesses::cpu.inst 24150 # number of demand (read+write) accesses
653system.cpu.l2cache.demand_accesses::cpu.data 1537035 # number of demand (read+write) accesses
654system.cpu.l2cache.demand_accesses::total 1561185 # number of demand (read+write) accesses
655system.cpu.l2cache.overall_accesses::cpu.inst 24150 # number of overall (read+write) accesses
656system.cpu.l2cache.overall_accesses::cpu.data 1537035 # number of overall (read+write) accesses
657system.cpu.l2cache.overall_accesses::total 1561185 # number of overall (read+write) accesses
658system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100663 # miss rate for ReadReq accesses
659system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277564 # miss rate for ReadReq accesses
660system.cpu.l2cache.ReadReq_miss_rate::total 0.274694 # miss rate for ReadReq accesses
661system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999309 # miss rate for UpgradeReq accesses
662system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999309 # miss rate for UpgradeReq accesses
663system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911166 # miss rate for ReadExReq accesses
664system.cpu.l2cache.ReadExReq_miss_rate::total 0.911166 # miss rate for ReadExReq accesses
665system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100663 # miss rate for demand accesses
666system.cpu.l2cache.demand_miss_rate::cpu.data 0.307457 # miss rate for demand accesses
667system.cpu.l2cache.demand_miss_rate::total 0.304258 # miss rate for demand accesses
668system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100663 # miss rate for overall accesses
669system.cpu.l2cache.overall_miss_rate::cpu.data 0.307457 # miss rate for overall accesses
670system.cpu.l2cache.overall_miss_rate::total 0.304258 # miss rate for overall accesses
671system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52210.818593 # average ReadReq miss latency
672system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63621.892658 # average ReadReq miss latency
673system.cpu.l2cache.ReadReq_avg_miss_latency::total 63554.055971 # average ReadReq miss latency
674system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49126.643965 # average ReadExReq miss latency
675system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49126.643965 # average ReadExReq miss latency
676system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52210.818593 # average overall miss latency
677system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61595.167509 # average overall miss latency
678system.cpu.l2cache.demand_avg_miss_latency::total 61547.139702 # average overall miss latency
679system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52210.818593 # average overall miss latency
680system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61595.167509 # average overall miss latency
681system.cpu.l2cache.overall_avg_miss_latency::total 61547.139702 # average overall miss latency

682system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
683system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
684system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
685system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
686system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
687system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
688system.cpu.l2cache.fast_writes 0 # number of fast writes performed
689system.cpu.l2cache.cache_copies 0 # number of cache copies performed
690system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
691system.cpu.l2cache.writebacks::total 66098 # number of writebacks
692system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits

693system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
694system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits

693system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits
694system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits

695system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits

696system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
697system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits

696system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
697system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits

698system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits

699system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
700system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits
701system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2431 # number of ReadReq MSHR misses
702system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406469 # number of ReadReq MSHR misses
703system.cpu.l2cache.ReadReq_mshr_misses::total 408900 # number of ReadReq MSHR misses
704system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4330 # number of UpgradeReq MSHR misses
705system.cpu.l2cache.UpgradeReq_mshr_misses::total 4330 # number of UpgradeReq MSHR misses
706system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66074 # number of ReadExReq MSHR misses
707system.cpu.l2cache.ReadExReq_mshr_misses::total 66074 # number of ReadExReq MSHR misses
708system.cpu.l2cache.demand_mshr_misses::cpu.inst 2431 # number of demand (read+write) MSHR misses
709system.cpu.l2cache.demand_mshr_misses::cpu.data 472543 # number of demand (read+write) MSHR misses

699system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
700system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
701system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2429 # number of ReadReq MSHR misses
702system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406470 # number of ReadReq MSHR misses
703system.cpu.l2cache.ReadReq_mshr_misses::total 408899 # number of ReadReq MSHR misses
704system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4340 # number of UpgradeReq MSHR misses
705system.cpu.l2cache.UpgradeReq_mshr_misses::total 4340 # number of UpgradeReq MSHR misses
706system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
707system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
708system.cpu.l2cache.demand_mshr_misses::cpu.inst 2429 # number of demand (read+write) MSHR misses
709system.cpu.l2cache.demand_mshr_misses::cpu.data 472545 # number of demand (read+write) MSHR misses

710system.cpu.l2cache.demand_mshr_misses::total 474974 # number of demand (read+write) MSHR misses

711system.cpu.l2cache.overall_mshr_misses::cpu.inst 2431 # number of overall MSHR misses
712system.cpu.l2cache.overall_mshr_misses::cpu.data 472543 # number of overall MSHR misses

711system.cpu.l2cache.overall_mshr_misses::cpu.inst 2429 # number of overall MSHR misses
712system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses

713system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses

714system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97294812 # number of ReadReq MSHR miss cycles
715system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693797350 # number of ReadReq MSHR miss cycles
716system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791092162 # number of ReadReq MSHR miss cycles
717system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43304330 # number of UpgradeReq MSHR miss cycles
718system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43304330 # number of UpgradeReq MSHR miss cycles
719system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390498504 # number of ReadExReq MSHR miss cycles
720system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390498504 # number of ReadExReq MSHR miss cycles
721system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97294812 # number of demand (read+write) MSHR miss cycles
722system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084295854 # number of demand (read+write) MSHR miss cycles
723system.cpu.l2cache.demand_mshr_miss_latency::total 23181590666 # number of demand (read+write) MSHR miss cycles
724system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97294812 # number of overall MSHR miss cycles
725system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084295854 # number of overall MSHR miss cycles
726system.cpu.l2cache.overall_mshr_miss_latency::total 23181590666 # number of overall MSHR miss cycles
727system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for ReadReq accesses
728system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277535 # mshr miss rate for ReadReq accesses
729system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses
730system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999308 # mshr miss rate for UpgradeReq accesses
731system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999308 # mshr miss rate for UpgradeReq accesses
732system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911177 # mshr miss rate for ReadExReq accesses
733system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911177 # mshr miss rate for ReadExReq accesses
734system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for demand accesses
735system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for demand accesses
736system.cpu.l2cache.demand_mshr_miss_rate::total 0.304214 # mshr miss rate for demand accesses
737system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for overall accesses
738system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for overall accesses
739system.cpu.l2cache.overall_mshr_miss_rate::total 0.304214 # mshr miss rate for overall accesses
740system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.547100 # average ReadReq mshr miss latency
741system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.133075 # average ReadReq mshr miss latency
742system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.398048 # average ReadReq mshr miss latency

714system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96251295 # number of ReadReq MSHR miss cycles
715system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20717048717 # number of ReadReq MSHR miss cycles
716system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20813300012 # number of ReadReq MSHR miss cycles
717system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43404340 # number of UpgradeReq MSHR miss cycles
718system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43404340 # number of UpgradeReq MSHR miss cycles
719system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2393684509 # number of ReadExReq MSHR miss cycles
720system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2393684509 # number of ReadExReq MSHR miss cycles
721system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96251295 # number of demand (read+write) MSHR miss cycles
722system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23110733226 # number of demand (read+write) MSHR miss cycles
723system.cpu.l2cache.demand_mshr_miss_latency::total 23206984521 # number of demand (read+write) MSHR miss cycles
724system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96251295 # number of overall MSHR miss cycles
725system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23110733226 # number of overall MSHR miss cycles
726system.cpu.l2cache.overall_mshr_miss_latency::total 23206984521 # number of overall MSHR miss cycles
727system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for ReadReq accesses
728system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277545 # mshr miss rate for ReadReq accesses
729system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274674 # mshr miss rate for ReadReq accesses
730system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999309 # mshr miss rate for UpgradeReq accesses
731system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999309 # mshr miss rate for UpgradeReq accesses
732system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses
733system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses
734system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for demand accesses
735system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for demand accesses
736system.cpu.l2cache.demand_mshr_miss_rate::total 0.304239 # mshr miss rate for demand accesses
737system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for overall accesses
738system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for overall accesses
739system.cpu.l2cache.overall_mshr_miss_rate::total 0.304239 # mshr miss rate for overall accesses
740system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39625.893372 # average ReadReq mshr miss latency
741system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50968.210980 # average ReadReq mshr miss latency
742system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50900.833732 # average ReadReq mshr miss latency

743system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
744system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency

745system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.109847 # average ReadExReq mshr miss latency
746system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.109847 # average ReadExReq mshr miss latency
747system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency
748system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
749system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
750system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency
751system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
752system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency

745system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36226.780310 # average ReadExReq mshr miss latency
746system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36226.780310 # average ReadExReq mshr miss latency
747system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency
748system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency
749system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency
750system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency
751system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency
752system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency

753system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

754system.cpu.dcache.replacements 1532987 # number of replacements
755system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
756system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
757system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
758system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
759system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
760system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
761system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
762system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
763system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
764system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
765system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
766system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
767system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
768system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
769system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
770system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
771system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
772system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
773system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
774system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
775system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
776system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
777system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
778system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses

754system.cpu.dcache.replacements 1532939 # number of replacements
755system.cpu.dcache.tagsinuse 4094.623683 # Cycle average of tags in use
756system.cpu.dcache.total_refs 970042937 # Total number of references to valid blocks.
757system.cpu.dcache.sampled_refs 1537035 # Sample count of references to valid blocks.
758system.cpu.dcache.avg_refs 631.113109 # Average number of references to valid blocks.
759system.cpu.dcache.warmup_cycle 332181000 # Cycle when the warmup percentage was hit.
760system.cpu.dcache.occ_blocks::cpu.data 4094.623683 # Average occupied blocks per requestor
761system.cpu.dcache.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy
762system.cpu.dcache.occ_percent::total 0.999664 # Average percentage of cache occupancy
763system.cpu.dcache.ReadReq_hits::cpu.data 693909081 # number of ReadReq hits
764system.cpu.dcache.ReadReq_hits::total 693909081 # number of ReadReq hits
765system.cpu.dcache.WriteReq_hits::cpu.data 276100966 # number of WriteReq hits
766system.cpu.dcache.WriteReq_hits::total 276100966 # number of WriteReq hits
767system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits
768system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits
769system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
770system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
771system.cpu.dcache.demand_hits::cpu.data 970010047 # number of demand (read+write) hits
772system.cpu.dcache.demand_hits::total 970010047 # number of demand (read+write) hits
773system.cpu.dcache.overall_hits::cpu.data 970010047 # number of overall hits
774system.cpu.dcache.overall_hits::total 970010047 # number of overall hits
775system.cpu.dcache.ReadReq_misses::cpu.data 1953320 # number of ReadReq misses
776system.cpu.dcache.ReadReq_misses::total 1953320 # number of ReadReq misses
777system.cpu.dcache.WriteReq_misses::cpu.data 834712 # number of WriteReq misses
778system.cpu.dcache.WriteReq_misses::total 834712 # number of WriteReq misses

779system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
780system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses

781system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
782system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
783system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
784system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
785system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369162000 # number of ReadReq miss cycles
786system.cpu.dcache.ReadReq_miss_latency::total 67369162000 # number of ReadReq miss cycles
787system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954940470 # number of WriteReq miss cycles
788system.cpu.dcache.WriteReq_miss_latency::total 39954940470 # number of WriteReq miss cycles
789system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
790system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
791system.cpu.dcache.demand_miss_latency::cpu.data 107324102470 # number of demand (read+write) miss cycles
792system.cpu.dcache.demand_miss_latency::total 107324102470 # number of demand (read+write) miss cycles
793system.cpu.dcache.overall_miss_latency::cpu.data 107324102470 # number of overall miss cycles
794system.cpu.dcache.overall_miss_latency::total 107324102470 # number of overall miss cycles
795system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
796system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)

781system.cpu.dcache.demand_misses::cpu.data 2788032 # number of demand (read+write) misses
782system.cpu.dcache.demand_misses::total 2788032 # number of demand (read+write) misses
783system.cpu.dcache.overall_misses::cpu.data 2788032 # number of overall misses
784system.cpu.dcache.overall_misses::total 2788032 # number of overall misses
785system.cpu.dcache.ReadReq_miss_latency::cpu.data 67394089000 # number of ReadReq miss cycles
786system.cpu.dcache.ReadReq_miss_latency::total 67394089000 # number of ReadReq miss cycles
787system.cpu.dcache.WriteReq_miss_latency::cpu.data 39986185470 # number of WriteReq miss cycles
788system.cpu.dcache.WriteReq_miss_latency::total 39986185470 # number of WriteReq miss cycles
789system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171500 # number of LoadLockedReq miss cycles
790system.cpu.dcache.LoadLockedReq_miss_latency::total 171500 # number of LoadLockedReq miss cycles
791system.cpu.dcache.demand_miss_latency::cpu.data 107380274470 # number of demand (read+write) miss cycles
792system.cpu.dcache.demand_miss_latency::total 107380274470 # number of demand (read+write) miss cycles
793system.cpu.dcache.overall_miss_latency::cpu.data 107380274470 # number of overall miss cycles
794system.cpu.dcache.overall_miss_latency::total 107380274470 # number of overall miss cycles
795system.cpu.dcache.ReadReq_accesses::cpu.data 695862401 # number of ReadReq accesses(hits+misses)
796system.cpu.dcache.ReadReq_accesses::total 695862401 # number of ReadReq accesses(hits+misses)

797system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
798system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)

799system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
800system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
801system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
802system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
803system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
804system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
805system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
806system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses

799system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses)
800system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses)
801system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
802system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
803system.cpu.dcache.demand_accesses::cpu.data 972798079 # number of demand (read+write) accesses
804system.cpu.dcache.demand_accesses::total 972798079 # number of demand (read+write) accesses
805system.cpu.dcache.overall_accesses::cpu.data 972798079 # number of overall (read+write) accesses
806system.cpu.dcache.overall_accesses::total 972798079 # number of overall (read+write) accesses

807system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
808system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
809system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
810system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses

811system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
812system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses

811system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
812system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses

813system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
814system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
815system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
816system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses

817system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency
818system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.508124 # average ReadReq miss latency
819system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.989278 # average WriteReq miss latency
820system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.989278 # average WriteReq miss latency
821system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
822system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
823system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
824system.cpu.dcache.demand_avg_miss_latency::total 38495.249960 # average overall miss latency
825system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
826system.cpu.dcache.overall_avg_miss_latency::total 38495.249960 # average overall miss latency
827system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
828system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
829system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
830system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
831system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
832system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked

817system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34502.328855 # average ReadReq miss latency
818system.cpu.dcache.ReadReq_avg_miss_latency::total 34502.328855 # average ReadReq miss latency
819system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47904.169905 # average WriteReq miss latency
820system.cpu.dcache.WriteReq_avg_miss_latency::total 47904.169905 # average WriteReq miss latency
821system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57166.666667 # average LoadLockedReq miss latency
822system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57166.666667 # average LoadLockedReq miss latency
823system.cpu.dcache.demand_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency
824system.cpu.dcache.demand_avg_miss_latency::total 38514.720947 # average overall miss latency
825system.cpu.dcache.overall_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency
826system.cpu.dcache.overall_avg_miss_latency::total 38514.720947 # average overall miss latency
827system.cpu.dcache.blocked_cycles::no_mshrs 2182 # number of cycles access was blocked
828system.cpu.dcache.blocked_cycles::no_targets 795 # number of cycles access was blocked
829system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked
830system.cpu.dcache.blocked::no_targets 88 # number of cycles access was blocked
831system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.964286 # average number of cycles each access was blocked
832system.cpu.dcache.avg_blocked_cycles::no_targets 9.034091 # average number of cycles each access was blocked

833system.cpu.dcache.fast_writes 0 # number of fast writes performed
834system.cpu.dcache.cache_copies 0 # number of cache copies performed

835system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
836system.cpu.dcache.writebacks::total 96322 # number of writebacks
837system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
838system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
839system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
840system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits

835system.cpu.dcache.writebacks::writebacks 96308 # number of writebacks
836system.cpu.dcache.writebacks::total 96308 # number of writebacks
837system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488800 # number of ReadReq MSHR hits
838system.cpu.dcache.ReadReq_mshr_hits::total 488800 # number of ReadReq MSHR hits
839system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757854 # number of WriteReq MSHR hits
840system.cpu.dcache.WriteReq_mshr_hits::total 757854 # number of WriteReq MSHR hits

841system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
842system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits

843system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
844system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
845system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
846system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
847system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
848system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
849system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
850system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
851system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
852system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
853system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
854system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
855system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884240500 # number of ReadReq MSHR miss cycles
856system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884240500 # number of ReadReq MSHR miss cycles
857system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478487500 # number of WriteReq MSHR miss cycles
858system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478487500 # number of WriteReq MSHR miss cycles
859system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
860system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
861system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
862system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles

843system.cpu.dcache.demand_mshr_hits::cpu.data 1246654 # number of demand (read+write) MSHR hits
844system.cpu.dcache.demand_mshr_hits::total 1246654 # number of demand (read+write) MSHR hits
845system.cpu.dcache.overall_mshr_hits::cpu.data 1246654 # number of overall MSHR hits
846system.cpu.dcache.overall_mshr_hits::total 1246654 # number of overall MSHR hits
847system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464520 # number of ReadReq MSHR misses
848system.cpu.dcache.ReadReq_mshr_misses::total 1464520 # number of ReadReq MSHR misses
849system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76858 # number of WriteReq MSHR misses
850system.cpu.dcache.WriteReq_mshr_misses::total 76858 # number of WriteReq MSHR misses
851system.cpu.dcache.demand_mshr_misses::cpu.data 1541378 # number of demand (read+write) MSHR misses
852system.cpu.dcache.demand_mshr_misses::total 1541378 # number of demand (read+write) MSHR misses
853system.cpu.dcache.overall_mshr_misses::cpu.data 1541378 # number of overall MSHR misses
854system.cpu.dcache.overall_mshr_misses::total 1541378 # number of overall MSHR misses
855system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37907812500 # number of ReadReq MSHR miss cycles
856system.cpu.dcache.ReadReq_mshr_miss_latency::total 37907812500 # number of ReadReq MSHR miss cycles
857system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3481886500 # number of WriteReq MSHR miss cycles
858system.cpu.dcache.WriteReq_mshr_miss_latency::total 3481886500 # number of WriteReq MSHR miss cycles
859system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41389699000 # number of demand (read+write) MSHR miss cycles
860system.cpu.dcache.demand_mshr_miss_latency::total 41389699000 # number of demand (read+write) MSHR miss cycles
861system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41389699000 # number of overall MSHR miss cycles
862system.cpu.dcache.overall_mshr_miss_latency::total 41389699000 # number of overall MSHR miss cycles

863system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
864system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses

865system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
866system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
867system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
868system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
869system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
870system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
871system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency
872system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency
873system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency
874system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency
875system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
876system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
877system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
878system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency

865system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
866system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
867system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses
868system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses
869system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses
870system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses
871system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25884.120736 # average ReadReq mshr miss latency
872system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25884.120736 # average ReadReq mshr miss latency
873system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45302.850712 # average WriteReq mshr miss latency
874system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45302.850712 # average WriteReq mshr miss latency
875system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency
876system.cpu.dcache.demand_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency
877system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency
878system.cpu.dcache.overall_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency