| stats.txt (9378:36ed6d4654bb) | stats.txt (9449:56610ab73040) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.624868 # Number of seconds simulated 4sim_ticks 624867585500 # Number of ticks simulated 5final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.624868 # Number of seconds simulated 4sim_ticks 624867585500 # Number of ticks simulated 5final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 118271 # Simulator instruction rate (inst/s) 8host_op_rate 161069 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53384157 # Simulator tick rate (ticks/s) 10host_mem_usage 298364 # Number of bytes of host memory used 11host_seconds 11705.11 # Real time elapsed on the host | 7host_inst_rate 53257 # Simulator instruction rate (inst/s) 8host_op_rate 72528 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24038469 # Simulator tick rate (ticks/s) 10host_mem_usage 255596 # Number of bytes of host memory used 11host_seconds 25994.48 # Real time elapsed on the host |
| 12sim_insts 1384379060 # Number of instructions simulated 13sim_ops 1885333812 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 30242752 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 155584 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 155584 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory --- 52 unchanged lines hidden (view full) --- 72system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 12sim_insts 1384379060 # Number of instructions simulated 13sim_ops 1885333812 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 30242752 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 155584 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 155584 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory --- 52 unchanged lines hidden (view full) --- 72system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 80system.physmem.totGap 624867513500 # Total gap between requests | 80system.physmem.totGap 624867514500 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 474974 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 474974 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 174system.physmem.totQLat 3316258619 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 18090208619 # Sum of mem lat for all requests | 174system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests |
| 176system.physmem.totBusLat 1899312000 # Total cycles spent in databus access 177system.physmem.totBankLat 12874638000 # Total cycles spent in bank access 178system.physmem.avgQLat 6984.13 # Average queueing delay per request 179system.physmem.avgBankLat 27114.32 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request | 176system.physmem.totBusLat 1899312000 # Total cycles spent in databus access 177system.physmem.totBankLat 12874638000 # Total cycles spent in bank access 178system.physmem.avgQLat 6984.13 # Average queueing delay per request 179system.physmem.avgBankLat 27114.32 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 181system.physmem.avgMemAccLat 38098.45 # Average memory access latency | 181system.physmem.avgMemAccLat 38098.44 # Average memory access latency |
| 182system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.35 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.03 # Average read queue length over time 189system.physmem.avgWrQLen 17.43 # Average write queue length over time --- 51 unchanged lines hidden (view full) --- 241system.cpu.BPredUnit.lookups 439117025 # Number of BP lookups 242system.cpu.BPredUnit.condPredicted 350578524 # Number of conditional branches predicted 243system.cpu.BPredUnit.condIncorrect 30630316 # Number of conditional branches incorrect 244system.cpu.BPredUnit.BTBLookups 248764319 # Number of BTB lookups 245system.cpu.BPredUnit.BTBHits 227490785 # Number of BTB hits 246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 247system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target. 248system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions. | 182system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.35 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.03 # Average read queue length over time 189system.physmem.avgWrQLen 17.43 # Average write queue length over time --- 51 unchanged lines hidden (view full) --- 241system.cpu.BPredUnit.lookups 439117025 # Number of BP lookups 242system.cpu.BPredUnit.condPredicted 350578524 # Number of conditional branches predicted 243system.cpu.BPredUnit.condIncorrect 30630316 # Number of conditional branches incorrect 244system.cpu.BPredUnit.BTBLookups 248764319 # Number of BTB lookups 245system.cpu.BPredUnit.BTBHits 227490785 # Number of BTB hits 246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 247system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target. 248system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions. |
| 249system.cpu.fetch.icacheStallCycles 354123352 # Number of cycles fetch is stalled on an Icache miss | 249system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss |
| 250system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed 251system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered 252system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken 253system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked 254system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing | 250system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed 251system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered 252system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken 253system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked 254system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing |
| 255system.cpu.fetch.BlockedCycles 133000859 # Number of cycles fetch has spent blocked 256system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 255system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked 256system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 257system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps 258system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR | 257system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps 258system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR |
| 259system.cpu.fetch.CacheLines 333825475 # Number of cache lines fetched 260system.cpu.fetch.IcacheSquashes 10767149 # Number of outstanding Icache misses that were squashed 261system.cpu.fetch.rateDist::samples 1215073364 # Number of instructions fetched each cycle (Total) | 259system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched 260system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed 261system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total) |
| 262system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 262system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 265system.cpu.fetch.rateDist::0 614410423 50.57% 50.57% # Number of instructions fetched each cycle (Total) | 265system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total) |
| 266system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::4 72457573 5.96% 72.48% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::5 42599927 3.51% 75.99% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::6 31039765 2.55% 78.54% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::7 31697654 2.61% 81.15% # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 266system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::4 72457573 5.96% 72.48% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::5 42599927 3.51% 75.99% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::6 31039765 2.55% 78.54% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::7 31697654 2.61% 81.15% # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 277system.cpu.fetch.rateDist::total 1215073364 # Number of instructions fetched each cycle (Total) | 277system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total) |
| 278system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle 279system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle 280system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle | 278system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle 279system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle 280system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle |
| 281system.cpu.decode.BlockedCycles 105461627 # Number of cycles decode is blocked | 281system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked |
| 282system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running 283system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking 284system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing 285system.cpu.decode.BranchResolved 44615078 # Number of times decode resolved a branch 286system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction 287system.cpu.decode.DecodedInsts 3041090435 # Number of instructions handled by decode 288system.cpu.decode.SquashedInsts 27022 # Number of squashed instructions handled by decode 289system.cpu.rename.SquashCycles 127217578 # Number of cycles rename is squashing 290system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle 291system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking 292system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst | 282system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running 283system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking 284system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing 285system.cpu.decode.BranchResolved 44615078 # Number of times decode resolved a branch 286system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction 287system.cpu.decode.DecodedInsts 3041090435 # Number of instructions handled by decode 288system.cpu.decode.SquashedInsts 27022 # Number of squashed instructions handled by decode 289system.cpu.rename.SquashCycles 127217578 # Number of cycles rename is squashing 290system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle 291system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking 292system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst |
| 293system.cpu.rename.RunCycles 540789818 # Number of cycles rename is running 294system.cpu.rename.UnblockCycles 71593101 # Number of cycles rename is unblocking 295system.cpu.rename.RenamedInsts 2966286071 # Number of instructions processed by rename | 293system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running 294system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking 295system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename |
| 296system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full 297system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full 298system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full | 296system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full 297system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full 298system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full |
| 299system.cpu.rename.RenamedOperands 2940514356 # Number of destination operands rename has renamed 300system.cpu.rename.RenameLookups 14121260893 # Number of register rename lookups that rename has made 301system.cpu.rename.int_rename_lookups 13550785312 # Number of integer rename lookups | 299system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed 300system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made 301system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups |
| 302system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups 303system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed | 302system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups 303system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed |
| 304system.cpu.rename.UndoneMaps 947360714 # Number of HB maps that are undone due to squashing | 304system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing |
| 305system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed 306system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed 307system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer 308system.cpu.memDep0.insertedLoads 972715984 # Number of loads inserted to the mem dependence unit. 309system.cpu.memDep0.insertedStores 490205592 # Number of stores inserted to the mem dependence unit. 310system.cpu.memDep0.conflictingLoads 36288460 # Number of conflicting loads. 311system.cpu.memDep0.conflictingStores 40771047 # Number of conflicting stores. 312system.cpu.iq.iqInstsAdded 2804297042 # Number of instructions added to the IQ (excludes non-spec) 313system.cpu.iq.iqNonSpecInstsAdded 31006 # Number of non-speculative instructions added to the IQ 314system.cpu.iq.iqInstsIssued 2436370950 # Number of instructions issued 315system.cpu.iq.iqSquashedInstsIssued 13311855 # Number of squashed instructions issued 316system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling 317system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph 318system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed | 305system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed 306system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed 307system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer 308system.cpu.memDep0.insertedLoads 972715984 # Number of loads inserted to the mem dependence unit. 309system.cpu.memDep0.insertedStores 490205592 # Number of stores inserted to the mem dependence unit. 310system.cpu.memDep0.conflictingLoads 36288460 # Number of conflicting loads. 311system.cpu.memDep0.conflictingStores 40771047 # Number of conflicting stores. 312system.cpu.iq.iqInstsAdded 2804297042 # Number of instructions added to the IQ (excludes non-spec) 313system.cpu.iq.iqNonSpecInstsAdded 31006 # Number of non-speculative instructions added to the IQ 314system.cpu.iq.iqInstsIssued 2436370950 # Number of instructions issued 315system.cpu.iq.iqSquashedInstsIssued 13311855 # Number of squashed instructions issued 316system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling 317system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph 318system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed |
| 319system.cpu.iq.issued_per_cycle::samples 1215073364 # Number of insts issued each cycle | 319system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle |
| 320system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 320system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 323system.cpu.iq.issued_per_cycle::0 379121475 31.20% 31.20% # Number of insts issued each cycle | 323system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle |
| 324system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::4 132635579 10.92% 87.90% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::5 93723777 7.71% 95.61% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::6 37883178 3.12% 98.73% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::7 12361449 1.02% 99.75% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 324system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::4 132635579 10.92% 87.90% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::5 93723777 7.71% 95.61% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::6 37883178 3.12% 98.73% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::7 12361449 1.02% 99.75% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 335system.cpu.iq.issued_per_cycle::total 1215073364 # Number of insts issued each cycle | 335system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle |
| 336system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 337system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 400system.cpu.iq.FU_type_0::MemRead 838357967 34.41% 81.84% # Type of FU issued 401system.cpu.iq.FU_type_0::MemWrite 442336083 18.16% 100.00% # Type of FU issued 402system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 403system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 404system.cpu.iq.FU_type_0::total 2436370950 # Type of FU issued 405system.cpu.iq.rate 1.949510 # Inst issue rate 406system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested 407system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst) | 336system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 337system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 400system.cpu.iq.FU_type_0::MemRead 838357967 34.41% 81.84% # Type of FU issued 401system.cpu.iq.FU_type_0::MemWrite 442336083 18.16% 100.00% # Type of FU issued 402system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 403system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 404system.cpu.iq.FU_type_0::total 2436370950 # Type of FU issued 405system.cpu.iq.rate 1.949510 # Inst issue rate 406system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested 407system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst) |
| 408system.cpu.iq.int_inst_queue_reads 6066277406 # Number of integer instruction queue reads | 408system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads |
| 409system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes 410system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses 411system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads 412system.cpu.iq.fp_inst_queue_writes 82717236 # Number of floating instruction queue writes 413system.cpu.iq.fp_inst_queue_wakeup_accesses 56437909 # Number of floating instruction queue wakeup accesses 414system.cpu.iq.int_alu_accesses 2460715459 # Number of integer alu accesses 415system.cpu.iq.fp_alu_accesses 63320089 # Number of floating point alu accesses 416system.cpu.iew.lsq.thread0.forwLoads 84361835 # Number of loads that had data forwarded from stores --- 6 unchanged lines hidden (view full) --- 423system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 424system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled 425system.cpu.iew.lsq.thread0.cacheBlocked 221 # Number of times an access to memory failed due to the cache being blocked 426system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 427system.cpu.iew.iewSquashCycles 127217578 # Number of cycles IEW is squashing 428system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking 429system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking 430system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ | 409system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes 410system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses 411system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads 412system.cpu.iq.fp_inst_queue_writes 82717236 # Number of floating instruction queue writes 413system.cpu.iq.fp_inst_queue_wakeup_accesses 56437909 # Number of floating instruction queue wakeup accesses 414system.cpu.iq.int_alu_accesses 2460715459 # Number of integer alu accesses 415system.cpu.iq.fp_alu_accesses 63320089 # Number of floating point alu accesses 416system.cpu.iew.lsq.thread0.forwLoads 84361835 # Number of loads that had data forwarded from stores --- 6 unchanged lines hidden (view full) --- 423system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 424system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled 425system.cpu.iew.lsq.thread0.cacheBlocked 221 # Number of times an access to memory failed due to the cache being blocked 426system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 427system.cpu.iew.iewSquashCycles 127217578 # Number of cycles IEW is squashing 428system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking 429system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking 430system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ |
| 431system.cpu.iew.iewDispSquashedInsts 1409393 # Number of squashed instructions skipped by dispatch | 431system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch |
| 432system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions 433system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions 434system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions 435system.cpu.iew.iewIQFullEvents 1558593 # Number of times the IQ has become full, causing a stall 436system.cpu.iew.iewLSQFullEvents 2526 # Number of times the LSQ has become full, causing a stall 437system.cpu.iew.memOrderViolationEvents 1428808 # Number of memory order violations 438system.cpu.iew.predictedTakenIncorrect 32521161 # Number of branches that were predicted taken incorrectly 439system.cpu.iew.predictedNotTakenIncorrect 1512713 # Number of branches that were predicted not taken incorrectly --- 45 unchanged lines hidden (view full) --- 485system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. 486system.cpu.commit.int_insts 1653705643 # Number of committed integer instructions. 487system.cpu.commit.function_calls 41577833 # Number of function calls committed. 488system.cpu.commit.bw_lim_events 90883098 # number cycles where commit BW limit reached 489system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 490system.cpu.rob.rob_reads 3801294955 # The number of ROB reads 491system.cpu.rob.rob_writes 5735909866 # The number of ROB writes 492system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself | 432system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions 433system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions 434system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions 435system.cpu.iew.iewIQFullEvents 1558593 # Number of times the IQ has become full, causing a stall 436system.cpu.iew.iewLSQFullEvents 2526 # Number of times the LSQ has become full, causing a stall 437system.cpu.iew.memOrderViolationEvents 1428808 # Number of memory order violations 438system.cpu.iew.predictedTakenIncorrect 32521161 # Number of branches that were predicted taken incorrectly 439system.cpu.iew.predictedNotTakenIncorrect 1512713 # Number of branches that were predicted not taken incorrectly --- 45 unchanged lines hidden (view full) --- 485system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. 486system.cpu.commit.int_insts 1653705643 # Number of committed integer instructions. 487system.cpu.commit.function_calls 41577833 # Number of function calls committed. 488system.cpu.commit.bw_lim_events 90883098 # number cycles where commit BW limit reached 489system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 490system.cpu.rob.rob_reads 3801294955 # The number of ROB reads 491system.cpu.rob.rob_writes 5735909866 # The number of ROB writes 492system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 493system.cpu.idleCycles 34661808 # Total number of cycles that the CPU has spent unscheduled due to idling | 493system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 494system.cpu.committedInsts 1384379060 # Number of Instructions Simulated 495system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated 496system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated 497system.cpu.cpi 0.902741 # CPI: Cycles Per Instruction 498system.cpu.cpi_total 0.902741 # CPI: Total CPI of All Threads 499system.cpu.ipc 1.107738 # IPC: Instructions Per Cycle 500system.cpu.ipc_total 1.107738 # IPC: Total IPC of All Threads 501system.cpu.int_regfile_reads 11770471325 # number of integer regfile reads --- 12 unchanged lines hidden (view full) --- 514system.cpu.icache.occ_percent::cpu.inst 0.802023 # Average percentage of cache occupancy 515system.cpu.icache.occ_percent::total 0.802023 # Average percentage of cache occupancy 516system.cpu.icache.ReadReq_hits::cpu.inst 333794637 # number of ReadReq hits 517system.cpu.icache.ReadReq_hits::total 333794637 # number of ReadReq hits 518system.cpu.icache.demand_hits::cpu.inst 333794637 # number of demand (read+write) hits 519system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits 520system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits 521system.cpu.icache.overall_hits::total 333794637 # number of overall hits | 494system.cpu.committedInsts 1384379060 # Number of Instructions Simulated 495system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated 496system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated 497system.cpu.cpi 0.902741 # CPI: Cycles Per Instruction 498system.cpu.cpi_total 0.902741 # CPI: Total CPI of All Threads 499system.cpu.ipc 1.107738 # IPC: Instructions Per Cycle 500system.cpu.ipc_total 1.107738 # IPC: Total IPC of All Threads 501system.cpu.int_regfile_reads 11770471325 # number of integer regfile reads --- 12 unchanged lines hidden (view full) --- 514system.cpu.icache.occ_percent::cpu.inst 0.802023 # Average percentage of cache occupancy 515system.cpu.icache.occ_percent::total 0.802023 # Average percentage of cache occupancy 516system.cpu.icache.ReadReq_hits::cpu.inst 333794637 # number of ReadReq hits 517system.cpu.icache.ReadReq_hits::total 333794637 # number of ReadReq hits 518system.cpu.icache.demand_hits::cpu.inst 333794637 # number of demand (read+write) hits 519system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits 520system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits 521system.cpu.icache.overall_hits::total 333794637 # number of overall hits |
| 522system.cpu.icache.ReadReq_misses::cpu.inst 30836 # number of ReadReq misses 523system.cpu.icache.ReadReq_misses::total 30836 # number of ReadReq misses 524system.cpu.icache.demand_misses::cpu.inst 30836 # number of demand (read+write) misses 525system.cpu.icache.demand_misses::total 30836 # number of demand (read+write) misses 526system.cpu.icache.overall_misses::cpu.inst 30836 # number of overall misses 527system.cpu.icache.overall_misses::total 30836 # number of overall misses 528system.cpu.icache.ReadReq_miss_latency::cpu.inst 469688998 # number of ReadReq miss cycles 529system.cpu.icache.ReadReq_miss_latency::total 469688998 # number of ReadReq miss cycles 530system.cpu.icache.demand_miss_latency::cpu.inst 469688998 # number of demand (read+write) miss cycles 531system.cpu.icache.demand_miss_latency::total 469688998 # number of demand (read+write) miss cycles 532system.cpu.icache.overall_miss_latency::cpu.inst 469688998 # number of overall miss cycles 533system.cpu.icache.overall_miss_latency::total 469688998 # number of overall miss cycles 534system.cpu.icache.ReadReq_accesses::cpu.inst 333825473 # number of ReadReq accesses(hits+misses) 535system.cpu.icache.ReadReq_accesses::total 333825473 # number of ReadReq accesses(hits+misses) 536system.cpu.icache.demand_accesses::cpu.inst 333825473 # number of demand (read+write) accesses 537system.cpu.icache.demand_accesses::total 333825473 # number of demand (read+write) accesses 538system.cpu.icache.overall_accesses::cpu.inst 333825473 # number of overall (read+write) accesses 539system.cpu.icache.overall_accesses::total 333825473 # number of overall (read+write) accesses | 522system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses 523system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses 524system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses 525system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses 526system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses 527system.cpu.icache.overall_misses::total 30837 # number of overall misses 528system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles 529system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles 530system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles 531system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles 532system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles 533system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles 534system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses) 535system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses) 536system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses 537system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses 538system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses 539system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses |
| 540system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses 541system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses 542system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses 543system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses 544system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses 545system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses | 540system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses 541system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses 542system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses 543system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses 544system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses 545system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses |
| 546system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15231.839344 # average ReadReq miss latency 547system.cpu.icache.ReadReq_avg_miss_latency::total 15231.839344 # average ReadReq miss latency 548system.cpu.icache.demand_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency 549system.cpu.icache.demand_avg_miss_latency::total 15231.839344 # average overall miss latency 550system.cpu.icache.overall_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency 551system.cpu.icache.overall_avg_miss_latency::total 15231.839344 # average overall miss latency | 546system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15233.615397 # average ReadReq miss latency 547system.cpu.icache.ReadReq_avg_miss_latency::total 15233.615397 # average ReadReq miss latency 548system.cpu.icache.demand_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency 549system.cpu.icache.demand_avg_miss_latency::total 15233.615397 # average overall miss latency 550system.cpu.icache.overall_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency 551system.cpu.icache.overall_avg_miss_latency::total 15233.615397 # average overall miss latency |
| 552system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked 553system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked 555system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.icache.avg_blocked_cycles::no_mshrs 34.793103 # average number of cycles each access was blocked 557system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu.icache.fast_writes 0 # number of fast writes performed 559system.cpu.icache.cache_copies 0 # number of cache copies performed | 552system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked 553system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked 555system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.icache.avg_blocked_cycles::no_mshrs 34.793103 # average number of cycles each access was blocked 557system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu.icache.fast_writes 0 # number of fast writes performed 559system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 560system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2272 # number of ReadReq MSHR hits 561system.cpu.icache.ReadReq_mshr_hits::total 2272 # number of ReadReq MSHR hits 562system.cpu.icache.demand_mshr_hits::cpu.inst 2272 # number of demand (read+write) MSHR hits 563system.cpu.icache.demand_mshr_hits::total 2272 # number of demand (read+write) MSHR hits 564system.cpu.icache.overall_mshr_hits::cpu.inst 2272 # number of overall MSHR hits 565system.cpu.icache.overall_mshr_hits::total 2272 # number of overall MSHR hits | 560system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2273 # number of ReadReq MSHR hits 561system.cpu.icache.ReadReq_mshr_hits::total 2273 # number of ReadReq MSHR hits 562system.cpu.icache.demand_mshr_hits::cpu.inst 2273 # number of demand (read+write) MSHR hits 563system.cpu.icache.demand_mshr_hits::total 2273 # number of demand (read+write) MSHR hits 564system.cpu.icache.overall_mshr_hits::cpu.inst 2273 # number of overall MSHR hits 565system.cpu.icache.overall_mshr_hits::total 2273 # number of overall MSHR hits |
| 566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses 567system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses 568system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses 569system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses 570system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses 571system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses | 566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses 567system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses 568system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses 569system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses 570system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses 571system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses |
| 572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379117998 # number of ReadReq MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_latency::total 379117998 # number of ReadReq MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379117998 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::total 379117998 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379117998 # number of overall MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::total 379117998 # number of overall MSHR miss cycles | 572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379116998 # number of ReadReq MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_latency::total 379116998 # number of ReadReq MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379116998 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::total 379116998 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379116998 # number of overall MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::total 379116998 # number of overall MSHR miss cycles |
| 578system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses 579system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses 580system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses 581system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses 582system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses 583system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses | 578system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses 579system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses 580system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses 581system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses 582system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses 583system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses |
| 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.580801 # average ReadReq mshr miss latency 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.580801 # average ReadReq mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency | 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.545792 # average ReadReq mshr miss latency 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.545792 # average ReadReq mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency |
| 590system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 590system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 591system.cpu.dcache.replacements 1532987 # number of replacements 592system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use 593system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks. 594system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks. 595system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks. 596system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit. 597system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor 598system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy 599system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy 600system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits 601system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits 602system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits 603system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits 604system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits 605system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits 606system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits 607system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits 608system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits 609system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits 610system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits 611system.cpu.dcache.overall_hits::total 969986101 # number of overall hits 612system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses 613system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses 614system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses 615system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses 616system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 617system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 618system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses 619system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses 620system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses 621system.cpu.dcache.overall_misses::total 2787983 # number of overall misses 622system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles 623system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles 626system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles 627system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles 628system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles 629system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles 630system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles 631system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles 632system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses) 633system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses) 634system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 635system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 636system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses) 637system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses) 638system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses) 639system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses) 640system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses 641system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses 642system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses 643system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses 644system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses 645system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses 646system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses 647system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses 648system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses 649system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses 650system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses 651system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses 652system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses 653system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses 654system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency 655system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency 656system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency 657system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency 658system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency 659system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency 660system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency 661system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency 664system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked 665system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked 666system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked 667system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked 668system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked 670system.cpu.dcache.fast_writes 0 # number of fast writes performed 671system.cpu.dcache.cache_copies 0 # number of cache copies performed 672system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks 673system.cpu.dcache.writebacks::total 96322 # number of writebacks 674system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits 675system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits 678system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 679system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 680system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits 681system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits 682system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits 683system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits 684system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses 685system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses 687system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses 688system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses 689system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses 690system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses 691system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses 692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses 704system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses 705system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses 706system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses 707system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550 # average ReadReq mshr miss latency 709system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency 711system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency 713system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency 715system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency 716system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 717system.cpu.l2cache.replacements 442193 # number of replacements 718system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use 719system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks. 720system.cpu.l2cache.sampled_refs 474940 # Sample count of references to valid blocks. 721system.cpu.l2cache.avg_refs 2.336548 # Average number of references to valid blocks. 722system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 723system.cpu.l2cache.occ_blocks::writebacks 1294.928331 # Average occupied blocks per requestor 724system.cpu.l2cache.occ_blocks::cpu.inst 48.758922 # Average occupied blocks per requestor --- 25 unchanged lines hidden (view full) --- 750system.cpu.l2cache.ReadExReq_misses::cpu.data 66074 # number of ReadExReq misses 751system.cpu.l2cache.ReadExReq_misses::total 66074 # number of ReadExReq misses 752system.cpu.l2cache.demand_misses::cpu.inst 2433 # number of demand (read+write) misses 753system.cpu.l2cache.demand_misses::cpu.data 472565 # number of demand (read+write) misses 754system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses 755system.cpu.l2cache.overall_misses::cpu.inst 2433 # number of overall misses 756system.cpu.l2cache.overall_misses::cpu.data 472565 # number of overall misses 757system.cpu.l2cache.overall_misses::total 474998 # number of overall misses | 591system.cpu.l2cache.replacements 442193 # number of replacements 592system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use 593system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks. 594system.cpu.l2cache.sampled_refs 474940 # Sample count of references to valid blocks. 595system.cpu.l2cache.avg_refs 2.336548 # Average number of references to valid blocks. 596system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 597system.cpu.l2cache.occ_blocks::writebacks 1294.928331 # Average occupied blocks per requestor 598system.cpu.l2cache.occ_blocks::cpu.inst 48.758922 # Average occupied blocks per requestor --- 25 unchanged lines hidden (view full) --- 624system.cpu.l2cache.ReadExReq_misses::cpu.data 66074 # number of ReadExReq misses 625system.cpu.l2cache.ReadExReq_misses::total 66074 # number of ReadExReq misses 626system.cpu.l2cache.demand_misses::cpu.inst 2433 # number of demand (read+write) misses 627system.cpu.l2cache.demand_misses::cpu.data 472565 # number of demand (read+write) misses 628system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses 629system.cpu.l2cache.overall_misses::cpu.inst 2433 # number of overall misses 630system.cpu.l2cache.overall_misses::cpu.data 472565 # number of overall misses 631system.cpu.l2cache.overall_misses::total 474998 # number of overall misses |
| 758system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128014500 # number of ReadReq miss cycles 759system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837930500 # number of ReadReq miss cycles | 632system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128013500 # number of ReadReq miss cycles 633system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837931500 # number of ReadReq miss cycles |
| 760system.cpu.l2cache.ReadReq_miss_latency::total 25965945000 # number of ReadReq miss cycles | 634system.cpu.l2cache.ReadReq_miss_latency::total 25965945000 # number of ReadReq miss cycles |
| 761system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242870000 # number of ReadExReq miss cycles 762system.cpu.l2cache.ReadExReq_miss_latency::total 3242870000 # number of ReadExReq miss cycles 763system.cpu.l2cache.demand_miss_latency::cpu.inst 128014500 # number of demand (read+write) miss cycles | 635system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242869000 # number of ReadExReq miss cycles 636system.cpu.l2cache.ReadExReq_miss_latency::total 3242869000 # number of ReadExReq miss cycles 637system.cpu.l2cache.demand_miss_latency::cpu.inst 128013500 # number of demand (read+write) miss cycles |
| 764system.cpu.l2cache.demand_miss_latency::cpu.data 29080800500 # number of demand (read+write) miss cycles | 638system.cpu.l2cache.demand_miss_latency::cpu.data 29080800500 # number of demand (read+write) miss cycles |
| 765system.cpu.l2cache.demand_miss_latency::total 29208815000 # number of demand (read+write) miss cycles 766system.cpu.l2cache.overall_miss_latency::cpu.inst 128014500 # number of overall miss cycles | 639system.cpu.l2cache.demand_miss_latency::total 29208814000 # number of demand (read+write) miss cycles 640system.cpu.l2cache.overall_miss_latency::cpu.inst 128013500 # number of overall miss cycles |
| 767system.cpu.l2cache.overall_miss_latency::cpu.data 29080800500 # number of overall miss cycles | 641system.cpu.l2cache.overall_miss_latency::cpu.data 29080800500 # number of overall miss cycles |
| 768system.cpu.l2cache.overall_miss_latency::total 29208815000 # number of overall miss cycles | 642system.cpu.l2cache.overall_miss_latency::total 29208814000 # number of overall miss cycles |
| 769system.cpu.l2cache.ReadReq_accesses::cpu.inst 24232 # number of ReadReq accesses(hits+misses) 770system.cpu.l2cache.ReadReq_accesses::cpu.data 1464568 # number of ReadReq accesses(hits+misses) 771system.cpu.l2cache.ReadReq_accesses::total 1488800 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.Writeback_accesses::writebacks 96322 # number of Writeback accesses(hits+misses) 773system.cpu.l2cache.Writeback_accesses::total 96322 # number of Writeback accesses(hits+misses) 774system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4333 # number of UpgradeReq accesses(hits+misses) 775system.cpu.l2cache.UpgradeReq_accesses::total 4333 # number of UpgradeReq accesses(hits+misses) 776system.cpu.l2cache.ReadExReq_accesses::cpu.data 72515 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 789system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911177 # miss rate for ReadExReq accesses 790system.cpu.l2cache.ReadExReq_miss_rate::total 0.911177 # miss rate for ReadExReq accesses 791system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100404 # miss rate for demand accesses 792system.cpu.l2cache.demand_miss_rate::cpu.data 0.307443 # miss rate for demand accesses 793system.cpu.l2cache.demand_miss_rate::total 0.304229 # miss rate for demand accesses 794system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100404 # miss rate for overall accesses 795system.cpu.l2cache.overall_miss_rate::cpu.data 0.307443 # miss rate for overall accesses 796system.cpu.l2cache.overall_miss_rate::total 0.304229 # miss rate for overall accesses | 643system.cpu.l2cache.ReadReq_accesses::cpu.inst 24232 # number of ReadReq accesses(hits+misses) 644system.cpu.l2cache.ReadReq_accesses::cpu.data 1464568 # number of ReadReq accesses(hits+misses) 645system.cpu.l2cache.ReadReq_accesses::total 1488800 # number of ReadReq accesses(hits+misses) 646system.cpu.l2cache.Writeback_accesses::writebacks 96322 # number of Writeback accesses(hits+misses) 647system.cpu.l2cache.Writeback_accesses::total 96322 # number of Writeback accesses(hits+misses) 648system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4333 # number of UpgradeReq accesses(hits+misses) 649system.cpu.l2cache.UpgradeReq_accesses::total 4333 # number of UpgradeReq accesses(hits+misses) 650system.cpu.l2cache.ReadExReq_accesses::cpu.data 72515 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 663system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911177 # miss rate for ReadExReq accesses 664system.cpu.l2cache.ReadExReq_miss_rate::total 0.911177 # miss rate for ReadExReq accesses 665system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100404 # miss rate for demand accesses 666system.cpu.l2cache.demand_miss_rate::cpu.data 0.307443 # miss rate for demand accesses 667system.cpu.l2cache.demand_miss_rate::total 0.304229 # miss rate for demand accesses 668system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100404 # miss rate for overall accesses 669system.cpu.l2cache.overall_miss_rate::cpu.data 0.307443 # miss rate for overall accesses 670system.cpu.l2cache.overall_miss_rate::total 0.304229 # miss rate for overall accesses |
| 797system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.906289 # average ReadReq miss latency 798system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.351956 # average ReadReq miss latency | 671system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.495273 # average ReadReq miss latency 672system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.354416 # average ReadReq miss latency |
| 799system.cpu.l2cache.ReadReq_avg_miss_latency::total 63498.217273 # average ReadReq miss latency | 673system.cpu.l2cache.ReadReq_avg_miss_latency::total 63498.217273 # average ReadReq miss latency |
| 800system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.365560 # average ReadExReq miss latency 801system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.365560 # average ReadExReq miss latency 802system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency | 674system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.350425 # average ReadExReq miss latency 675system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.350425 # average ReadExReq miss latency 676system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency |
| 803system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency | 677system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency |
| 804system.cpu.l2cache.demand_avg_miss_latency::total 61492.501021 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency | 678system.cpu.l2cache.demand_avg_miss_latency::total 61492.498916 # average overall miss latency 679system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency |
| 806system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency | 680system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency |
| 807system.cpu.l2cache.overall_avg_miss_latency::total 61492.501021 # average overall miss latency | 681system.cpu.l2cache.overall_avg_miss_latency::total 61492.498916 # average overall miss latency |
| 808system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 811system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 812system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 813system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 814system.cpu.l2cache.fast_writes 0 # number of fast writes performed 815system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 833system.cpu.l2cache.ReadExReq_mshr_misses::total 66074 # number of ReadExReq MSHR misses 834system.cpu.l2cache.demand_mshr_misses::cpu.inst 2431 # number of demand (read+write) MSHR misses 835system.cpu.l2cache.demand_mshr_misses::cpu.data 472543 # number of demand (read+write) MSHR misses 836system.cpu.l2cache.demand_mshr_misses::total 474974 # number of demand (read+write) MSHR misses 837system.cpu.l2cache.overall_mshr_misses::cpu.inst 2431 # number of overall MSHR misses 838system.cpu.l2cache.overall_mshr_misses::cpu.data 472543 # number of overall MSHR misses 839system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses 840system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97294812 # number of ReadReq MSHR miss cycles | 682system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 683system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 684system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 685system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 686system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 687system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 688system.cpu.l2cache.fast_writes 0 # number of fast writes performed 689system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 707system.cpu.l2cache.ReadExReq_mshr_misses::total 66074 # number of ReadExReq MSHR misses 708system.cpu.l2cache.demand_mshr_misses::cpu.inst 2431 # number of demand (read+write) MSHR misses 709system.cpu.l2cache.demand_mshr_misses::cpu.data 472543 # number of demand (read+write) MSHR misses 710system.cpu.l2cache.demand_mshr_misses::total 474974 # number of demand (read+write) MSHR misses 711system.cpu.l2cache.overall_mshr_misses::cpu.inst 2431 # number of overall MSHR misses 712system.cpu.l2cache.overall_mshr_misses::cpu.data 472543 # number of overall MSHR misses 713system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses 714system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97294812 # number of ReadReq MSHR miss cycles |
| 841system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693796850 # number of ReadReq MSHR miss cycles 842system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791091662 # number of ReadReq MSHR miss cycles | 715system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693797350 # number of ReadReq MSHR miss cycles 716system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791092162 # number of ReadReq MSHR miss cycles |
| 843system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43304330 # number of UpgradeReq MSHR miss cycles 844system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43304330 # number of UpgradeReq MSHR miss cycles | 717system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43304330 # number of UpgradeReq MSHR miss cycles 718system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43304330 # number of UpgradeReq MSHR miss cycles |
| 845system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390499504 # number of ReadExReq MSHR miss cycles 846system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390499504 # number of ReadExReq MSHR miss cycles | 719system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390498504 # number of ReadExReq MSHR miss cycles 720system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390498504 # number of ReadExReq MSHR miss cycles |
| 847system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97294812 # number of demand (read+write) MSHR miss cycles | 721system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97294812 # number of demand (read+write) MSHR miss cycles |
| 848system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084296354 # number of demand (read+write) MSHR miss cycles 849system.cpu.l2cache.demand_mshr_miss_latency::total 23181591166 # number of demand (read+write) MSHR miss cycles | 722system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084295854 # number of demand (read+write) MSHR miss cycles 723system.cpu.l2cache.demand_mshr_miss_latency::total 23181590666 # number of demand (read+write) MSHR miss cycles |
| 850system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97294812 # number of overall MSHR miss cycles | 724system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97294812 # number of overall MSHR miss cycles |
| 851system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084296354 # number of overall MSHR miss cycles 852system.cpu.l2cache.overall_mshr_miss_latency::total 23181591166 # number of overall MSHR miss cycles | 725system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084295854 # number of overall MSHR miss cycles 726system.cpu.l2cache.overall_mshr_miss_latency::total 23181590666 # number of overall MSHR miss cycles |
| 853system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for ReadReq accesses 854system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277535 # mshr miss rate for ReadReq accesses 855system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999308 # mshr miss rate for UpgradeReq accesses 857system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999308 # mshr miss rate for UpgradeReq accesses 858system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911177 # mshr miss rate for ReadExReq accesses 859system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911177 # mshr miss rate for ReadExReq accesses 860system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for demand accesses 861system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for demand accesses 862system.cpu.l2cache.demand_mshr_miss_rate::total 0.304214 # mshr miss rate for demand accesses 863system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for overall accesses 864system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for overall accesses 865system.cpu.l2cache.overall_mshr_miss_rate::total 0.304214 # mshr miss rate for overall accesses 866system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.547100 # average ReadReq mshr miss latency | 727system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for ReadReq accesses 728system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277535 # mshr miss rate for ReadReq accesses 729system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses 730system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999308 # mshr miss rate for UpgradeReq accesses 731system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999308 # mshr miss rate for UpgradeReq accesses 732system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911177 # mshr miss rate for ReadExReq accesses 733system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911177 # mshr miss rate for ReadExReq accesses 734system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for demand accesses 735system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for demand accesses 736system.cpu.l2cache.demand_mshr_miss_rate::total 0.304214 # mshr miss rate for demand accesses 737system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for overall accesses 738system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for overall accesses 739system.cpu.l2cache.overall_mshr_miss_rate::total 0.304214 # mshr miss rate for overall accesses 740system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.547100 # average ReadReq mshr miss latency |
| 867system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.131845 # average ReadReq mshr miss latency 868system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.396826 # average ReadReq mshr miss latency | 741system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.133075 # average ReadReq mshr miss latency 742system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.398048 # average ReadReq mshr miss latency |
| 869system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 870system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 743system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 744system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| 871system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.124981 # average ReadExReq mshr miss latency 872system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.124981 # average ReadExReq mshr miss latency | 745system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.109847 # average ReadExReq mshr miss latency 746system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.109847 # average ReadExReq mshr miss latency |
| 873system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency | 747system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency |
| 874system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency 875system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency | 748system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency 749system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency |
| 876system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency | 750system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency |
| 877system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency 878system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency | 751system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency 752system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency |
| 879system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 753system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 754system.cpu.dcache.replacements 1532987 # number of replacements 755system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use 756system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks. 757system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks. 758system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks. 759system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit. 760system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor 761system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy 762system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy 763system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits 764system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits 765system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits 766system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits 767system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits 768system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits 769system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits 770system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits 771system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits 772system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits 773system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits 774system.cpu.dcache.overall_hits::total 969986101 # number of overall hits 775system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses 776system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses 777system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses 778system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses 779system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 780system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 781system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses 782system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses 783system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses 784system.cpu.dcache.overall_misses::total 2787983 # number of overall misses 785system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369162000 # number of ReadReq miss cycles 786system.cpu.dcache.ReadReq_miss_latency::total 67369162000 # number of ReadReq miss cycles 787system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954940470 # number of WriteReq miss cycles 788system.cpu.dcache.WriteReq_miss_latency::total 39954940470 # number of WriteReq miss cycles 789system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles 790system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles 791system.cpu.dcache.demand_miss_latency::cpu.data 107324102470 # number of demand (read+write) miss cycles 792system.cpu.dcache.demand_miss_latency::total 107324102470 # number of demand (read+write) miss cycles 793system.cpu.dcache.overall_miss_latency::cpu.data 107324102470 # number of overall miss cycles 794system.cpu.dcache.overall_miss_latency::total 107324102470 # number of overall miss cycles 795system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses) 796system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses) 797system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 798system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 799system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses) 800system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses) 801system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses) 802system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses) 803system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses 804system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses 805system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses 806system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses 807system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses 808system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses 809system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses 810system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses 811system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses 812system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses 813system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses 814system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses 815system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses 816system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses 817system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency 818system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.508124 # average ReadReq miss latency 819system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.989278 # average WriteReq miss latency 820system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.989278 # average WriteReq miss latency 821system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency 822system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency 823system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency 824system.cpu.dcache.demand_avg_miss_latency::total 38495.249960 # average overall miss latency 825system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency 826system.cpu.dcache.overall_avg_miss_latency::total 38495.249960 # average overall miss latency 827system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked 828system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked 829system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked 830system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked 831system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked 832system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked 833system.cpu.dcache.fast_writes 0 # number of fast writes performed 834system.cpu.dcache.cache_copies 0 # number of cache copies performed 835system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks 836system.cpu.dcache.writebacks::total 96322 # number of writebacks 837system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits 838system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits 839system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits 840system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits 841system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 842system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 843system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits 844system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits 845system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits 846system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits 847system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses 848system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses 849system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses 850system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses 851system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses 852system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses 853system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses 854system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses 855system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884240500 # number of ReadReq MSHR miss cycles 856system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884240500 # number of ReadReq MSHR miss cycles 857system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478487500 # number of WriteReq MSHR miss cycles 858system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478487500 # number of WriteReq MSHR miss cycles 859system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles 860system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles 861system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles 862system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles 863system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses 864system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses 865system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses 866system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses 867system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses 868system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses 869system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses 870system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses 871system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency 872system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency 873system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency 874system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency 875system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency 876system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency 877system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency 878system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency 879system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
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| 880 881---------- End Simulation Statistics ---------- | 880 881---------- End Simulation Statistics ---------- |