| stats.txt (9223:be1c1059438b) | stats.txt (9229:65f927bda74d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.735463 # Number of seconds simulated 4sim_ticks 735462942500 # Number of ticks simulated 5final_tick 735462942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.737495 # Number of seconds simulated 4sim_ticks 737494828500 # Number of ticks simulated 5final_tick 737494828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 115593 # Simulator instruction rate (inst/s) 8host_op_rate 157422 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 61409842 # Simulator tick rate (ticks/s) 10host_mem_usage 243732 # Number of bytes of host memory used 11host_seconds 11976.30 # Real time elapsed on the host 12sim_insts 1384378705 # Number of instructions simulated 13sim_ops 1885333457 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 209152 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 94513152 # Number of bytes read from this memory 16system.physmem.bytes_read::total 94722304 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 209152 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 209152 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 20system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3268 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1476768 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 1480036 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 284381 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 128508381 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 128792762 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 284381 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 284381 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 5751849 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 5751849 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 5751849 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 284381 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 128508381 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 134544612 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 117861 # Simulator instruction rate (inst/s) 8host_op_rate 160511 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 62787760 # Simulator tick rate (ticks/s) 10host_mem_usage 243784 # Number of bytes of host memory used 11host_seconds 11745.84 # Real time elapsed on the host 12sim_insts 1384378545 # Number of instructions simulated 13sim_ops 1885333297 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 209536 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 94516480 # Number of bytes read from this memory 16system.physmem.bytes_read::total 94726016 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 209536 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 209536 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory 20system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3274 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1476820 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 1480094 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 284119 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 128158838 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 128442956 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 284119 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 284119 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 5736089 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 5736089 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 5736089 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 284119 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 128158838 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 134179045 # Total bandwidth to/from this memory (bytes/s) |
| 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 1411 # Number of system calls | 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 1411 # Number of system calls |
| 80system.cpu.numCycles 1470925886 # number of cpu cycles simulated | 80system.cpu.numCycles 1474989658 # number of cpu cycles simulated |
| 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 83system.cpu.BPredUnit.lookups 526944807 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 400998639 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 36103831 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 389912593 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 290078755 # Number of BTB hits | 83system.cpu.BPredUnit.lookups 524417855 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 399374260 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 35885746 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 373085909 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 286974367 # Number of BTB hits |
| 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 89system.cpu.BPredUnit.usedRAS 59371448 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 2810327 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 451184041 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 2630280787 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 526944807 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 349450203 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 714901139 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 225817309 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 101657894 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 2270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 20337 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 420935290 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 11687737 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 1451892883 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.541647 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.159630 # Number of instructions fetched each cycle (Total) | 89system.cpu.BPredUnit.usedRAS 58521049 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 2814397 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 448543327 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 2629766387 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 524417855 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 345495416 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 712413372 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 224871613 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 101150257 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 2305 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 27764 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 417868916 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 11061583 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 1445533834 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.549178 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.166303 # Number of instructions fetched each cycle (Total) |
| 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 106system.cpu.fetch.rateDist::0 737052267 50.76% 50.76% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 55648987 3.83% 54.60% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 113021811 7.78% 62.38% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 71058557 4.89% 67.28% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 83474414 5.75% 73.03% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 55105836 3.80% 76.82% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 35245314 2.43% 79.25% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 35853884 2.47% 81.72% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 265431813 18.28% 100.00% # Number of instructions fetched each cycle (Total) | 106system.cpu.fetch.rateDist::0 733184926 50.72% 50.72% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 55708468 3.85% 54.57% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 112020823 7.75% 62.32% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 70937824 4.91% 67.23% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 82697525 5.72% 72.95% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 53946539 3.73% 76.68% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 34097920 2.36% 79.04% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 36269848 2.51% 81.55% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 266669961 18.45% 100.00% # Number of instructions fetched each cycle (Total) |
| 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 118system.cpu.fetch.rateDist::total 1451892883 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.358240 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.788180 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 498609504 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 80967892 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 677644967 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 10558484 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 184112036 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 82169847 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 15539 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 3562988403 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 34450 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 184112036 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 537763866 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 32181538 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 530906 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 647549947 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 49754590 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 3439334544 # Number of instructions processed by rename | 118system.cpu.fetch.rateDist::total 1445533834 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.355540 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.782905 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 495848393 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 80424598 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 675057973 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 10827570 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 183375300 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 81502199 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 23236 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 3555990026 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 53741 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 183375300 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 535002639 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 31838463 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 561864 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 645033334 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 49722234 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 3433849661 # Number of instructions processed by rename |
| 137system.cpu.rename.ROBFullEvents 240 # Number of times rename has blocked due to ROB full | 137system.cpu.rename.ROBFullEvents 240 # Number of times rename has blocked due to ROB full |
| 138system.cpu.rename.IQFullEvents 4507727 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 40704108 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 1637 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 3357877059 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 16273276362 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 15612337004 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 660939358 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 1993153074 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 1364723985 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 50374 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 45755 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 138448530 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 1057693537 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 579697033 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 32301976 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 40224751 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 3204253855 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 55204 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 2728539607 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 26296633 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 1318520975 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 3049786617 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 32197 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 1451892883 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 1.879298 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.913242 # Number of insts issued each cycle | 138system.cpu.rename.IQFullEvents 4442600 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 40377333 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 1619 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 3343633011 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 16242490520 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 15601606149 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 640884371 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 1993152818 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 1350480193 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 55128 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 50419 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 136573484 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 1056851261 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 578467186 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 33770671 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 40675012 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 3200649154 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 58384 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 2726502260 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 25388775 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 1314914344 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 3030342592 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 35409 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 1445533834 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 1.886156 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.918040 # Number of insts issued each cycle |
| 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 165system.cpu.iq.issued_per_cycle::0 529391229 36.46% 36.46% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 201881649 13.90% 50.37% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 217086646 14.95% 65.32% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 180698536 12.45% 77.76% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 155303824 10.70% 88.46% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 101627119 7.00% 95.46% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 47687061 3.28% 98.75% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 10818751 0.75% 99.49% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 7398068 0.51% 100.00% # Number of insts issued each cycle | 165system.cpu.iq.issued_per_cycle::0 525278081 36.34% 36.34% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 201262430 13.92% 50.26% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 215918123 14.94% 65.20% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 180162301 12.46% 77.66% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 154926049 10.72% 88.38% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 101550700 7.03% 95.40% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 47554041 3.29% 98.69% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 10922133 0.76% 99.45% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 7959976 0.55% 100.00% # Number of insts issued each cycle |
| 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 177system.cpu.iq.issued_per_cycle::total 1451892883 # Number of insts issued each cycle | 177system.cpu.iq.issued_per_cycle::total 1445533834 # Number of insts issued each cycle |
| 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 179system.cpu.iq.fu_full::IntAlu 1769730 1.85% 1.85% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 23897 0.03% 1.88% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 57017691 59.74% 61.62% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 36624161 38.38% 100.00% # attempts to use FU when none available | 179system.cpu.iq.fu_full::IntAlu 1492509 1.56% 1.56% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 23896 0.02% 1.59% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 1.59% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.59% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.59% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.59% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 1.59% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.59% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.59% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.59% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.59% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.59% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.59% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.59% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.59% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 1.59% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.59% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 1.59% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.59% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.59% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.59% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.59% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.59% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.59% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.59% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.59% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.59% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.59% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.59% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 56884483 59.48% 61.06% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 37239793 38.94% 100.00% # attempts to use FU when none available |
| 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 213system.cpu.iq.FU_type_0::IntAlu 1267852875 46.47% 46.47% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 11249841 0.41% 46.88% # Type of FU issued 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 6876502 0.25% 47.18% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 5509242 0.20% 47.38% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 10 0.00% 47.38% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 23422716 0.86% 48.24% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.24% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.24% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.24% # Type of FU issued 242system.cpu.iq.FU_type_0::MemRead 900241539 32.99% 81.23% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 512011592 18.77% 100.00% # Type of FU issued | 213system.cpu.iq.FU_type_0::IntAlu 1265251443 46.41% 46.41% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 11240550 0.41% 46.82% # Type of FU issued 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.82% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.82% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.82% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.82% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.82% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.82% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.82% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.82% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.82% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.82% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.82% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.82% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.82% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.82% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.82% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.82% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.82% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.82% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.87% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.87% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 6876520 0.25% 47.12% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 5507594 0.20% 47.32% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 50 0.00% 47.32% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 23397304 0.86% 48.18% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued 242system.cpu.iq.FU_type_0::MemRead 900321510 33.02% 81.20% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 512531999 18.80% 100.00% # Type of FU issued |
| 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 246system.cpu.iq.FU_type_0::total 2728539607 # Type of FU issued 247system.cpu.iq.rate 1.854981 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 95435479 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.034977 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 6896111029 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 4417455828 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 2500265065 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 134593180 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 105438972 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 60061785 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 2754719800 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 69255286 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 70868561 # Number of loads that had data forwarded from stores | 246system.cpu.iq.FU_type_0::total 2726502260 # Type of FU issued 247system.cpu.iq.rate 1.848489 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 95640681 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.035078 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 6886689526 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 4415187143 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 2498660773 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 132878284 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 100500200 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 59720745 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 2753616267 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 68526674 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 71560936 # Number of loads that had data forwarded from stores |
| 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 260system.cpu.iew.lsq.thread0.squashedLoads 426304733 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 264948 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 1116073 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 302700113 # Number of stores squashed | 260system.cpu.iew.lsq.thread0.squashedLoads 425462489 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 295662 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 1252623 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 301470298 # Number of stores squashed |
| 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 266system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled | 266system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled |
| 267system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 267system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 269system.cpu.iew.iewSquashCycles 184112036 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 17217570 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 2222077 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 3204383976 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 3801477 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 1057693537 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 579697033 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 44065 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 2220604 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 1116073 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 37419443 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 9018722 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 46438165 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 2627591050 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 846492275 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 100948557 # Number of squashed instructions skipped in execute | 269system.cpu.iew.iewSquashCycles 183375300 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 17460814 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 1976242 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 3200787719 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 6982578 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 1056851261 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 578467186 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 47271 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 1974574 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 647 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 1252623 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 36804150 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 9241017 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 46045167 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 2625801566 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 846122172 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 100700694 # Number of squashed instructions skipped in execute |
| 286system.cpu.iew.exec_swp 0 # number of swp insts executed | 286system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 287system.cpu.iew.exec_nop 74917 # number of nop insts executed 288system.cpu.iew.exec_refs 1329282286 # number of memory reference insts executed 289system.cpu.iew.exec_branches 361424797 # Number of branches executed 290system.cpu.iew.exec_stores 482790011 # Number of stores executed 291system.cpu.iew.exec_rate 1.786352 # Inst execution rate 292system.cpu.iew.wb_sent 2588656133 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 2560326850 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 1477151291 # num instructions producing a value 295system.cpu.iew.wb_consumers 2761912490 # num instructions consuming a value | 287system.cpu.iew.exec_nop 80181 # number of nop insts executed 288system.cpu.iew.exec_refs 1330053445 # number of memory reference insts executed 289system.cpu.iew.exec_branches 359055744 # Number of branches executed 290system.cpu.iew.exec_stores 483931273 # Number of stores executed 291system.cpu.iew.exec_rate 1.780217 # Inst execution rate 292system.cpu.iew.wb_sent 2586917302 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 2558381518 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 1475385900 # num instructions producing a value 295system.cpu.iew.wb_consumers 2766219416 # num instructions consuming a value |
| 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 297system.cpu.iew.wb_rate 1.740623 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.534829 # average fanout of values written-back | 297system.cpu.iew.wb_rate 1.734508 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.533358 # average fanout of values written-back |
| 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 300system.cpu.commit.commitSquashedInsts 1319039983 # The number of squashed insts skipped by commit 301system.cpu.commit.commitNonSpecStalls 23007 # The number of times commit has been forced to stall to communicate backwards 302system.cpu.commit.branchMispredicts 41626374 # The number of times a branch was mispredicted 303system.cpu.commit.committed_per_cycle::samples 1267780849 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::mean 1.487122 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::stdev 2.205349 # Number of insts commited each cycle | 300system.cpu.commit.commitSquashedInsts 1315443833 # The number of squashed insts skipped by commit 301system.cpu.commit.commitNonSpecStalls 22975 # The number of times commit has been forced to stall to communicate backwards 302system.cpu.commit.branchMispredicts 41404056 # The number of times a branch was mispredicted 303system.cpu.commit.committed_per_cycle::samples 1262158536 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::mean 1.493746 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::stdev 2.206193 # Number of insts commited each cycle |
| 306system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 306system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 307system.cpu.commit.committed_per_cycle::0 586908423 46.29% 46.29% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::1 318188211 25.10% 71.39% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::2 101915381 8.04% 79.43% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::3 79184752 6.25% 85.68% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::4 52930899 4.18% 89.85% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::5 24002778 1.89% 91.75% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::6 17056118 1.35% 93.09% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::7 9057246 0.71% 93.81% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::8 78537041 6.19% 100.00% # Number of insts commited each cycle | 307system.cpu.commit.committed_per_cycle::0 581725846 46.09% 46.09% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::1 316852279 25.10% 71.19% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::2 102044776 8.08% 79.28% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::3 79824424 6.32% 85.60% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::4 53115957 4.21% 89.81% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::5 24396464 1.93% 91.74% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::6 17091653 1.35% 93.10% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::7 8923952 0.71% 93.81% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::8 78183185 6.19% 100.00% # Number of insts commited each cycle |
| 316system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 316system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 319system.cpu.commit.committed_per_cycle::total 1267780849 # Number of insts commited each cycle 320system.cpu.commit.committedInsts 1384389721 # Number of instructions committed 321system.cpu.commit.committedOps 1885344473 # Number of ops (including micro ops) committed | 319system.cpu.commit.committed_per_cycle::total 1262158536 # Number of insts commited each cycle 320system.cpu.commit.committedInsts 1384389561 # Number of instructions committed 321system.cpu.commit.committedOps 1885344313 # Number of ops (including micro ops) committed |
| 322system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 322system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 323system.cpu.commit.refs 908385724 # Number of memory references committed 324system.cpu.commit.loads 631388804 # Number of loads committed | 323system.cpu.commit.refs 908385660 # Number of memory references committed 324system.cpu.commit.loads 631388772 # Number of loads committed |
| 325system.cpu.commit.membars 9986 # Number of memory barriers committed | 325system.cpu.commit.membars 9986 # Number of memory barriers committed |
| 326system.cpu.commit.branches 291350167 # Number of branches committed | 326system.cpu.commit.branches 291350135 # Number of branches committed |
| 327system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. | 327system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. |
| 328system.cpu.commit.int_insts 1653705359 # Number of committed integer instructions. | 328system.cpu.commit.int_insts 1653705231 # Number of committed integer instructions. |
| 329system.cpu.commit.function_calls 41577833 # Number of function calls committed. | 329system.cpu.commit.function_calls 41577833 # Number of function calls committed. |
| 330system.cpu.commit.bw_lim_events 78537041 # number cycles where commit BW limit reached | 330system.cpu.commit.bw_lim_events 78183185 # number cycles where commit BW limit reached |
| 331system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 331system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 332system.cpu.rob.rob_reads 4393609919 # The number of ROB reads 333system.cpu.rob.rob_writes 6592898385 # The number of ROB writes 334system.cpu.timesIdled 1319009 # Number of times that the entire CPU went into an idle state and unscheduled itself 335system.cpu.idleCycles 19033003 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu.committedInsts 1384378705 # Number of Instructions Simulated 337system.cpu.committedOps 1885333457 # Number of Ops (including micro ops) Simulated 338system.cpu.committedInsts_total 1384378705 # Number of Instructions Simulated 339system.cpu.cpi 1.062517 # CPI: Cycles Per Instruction 340system.cpu.cpi_total 1.062517 # CPI: Total CPI of All Threads 341system.cpu.ipc 0.941161 # IPC: Instructions Per Cycle 342system.cpu.ipc_total 0.941161 # IPC: Total IPC of All Threads 343system.cpu.int_regfile_reads 12954963873 # number of integer regfile reads 344system.cpu.int_regfile_writes 2433899431 # number of integer regfile writes 345system.cpu.fp_regfile_reads 71453474 # number of floating regfile reads 346system.cpu.fp_regfile_writes 51512029 # number of floating regfile writes 347system.cpu.misc_regfile_reads 4110345957 # number of misc regfile reads 348system.cpu.misc_regfile_writes 13776148 # number of misc regfile writes 349system.cpu.icache.replacements 27727 # number of replacements 350system.cpu.icache.tagsinuse 1657.357291 # Cycle average of tags in use 351system.cpu.icache.total_refs 420895339 # Total number of references to valid blocks. 352system.cpu.icache.sampled_refs 29422 # Sample count of references to valid blocks. 353system.cpu.icache.avg_refs 14305.463225 # Average number of references to valid blocks. | 332system.cpu.rob.rob_reads 4384745152 # The number of ROB reads 333system.cpu.rob.rob_writes 6584968170 # The number of ROB writes 334system.cpu.timesIdled 1343543 # Number of times that the entire CPU went into an idle state and unscheduled itself 335system.cpu.idleCycles 29455824 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu.committedInsts 1384378545 # Number of Instructions Simulated 337system.cpu.committedOps 1885333297 # Number of Ops (including micro ops) Simulated 338system.cpu.committedInsts_total 1384378545 # Number of Instructions Simulated 339system.cpu.cpi 1.065453 # CPI: Cycles Per Instruction 340system.cpu.cpi_total 1.065453 # CPI: Total CPI of All Threads 341system.cpu.ipc 0.938568 # IPC: Instructions Per Cycle 342system.cpu.ipc_total 0.938568 # IPC: Total IPC of All Threads 343system.cpu.int_regfile_reads 12950426831 # number of integer regfile reads 344system.cpu.int_regfile_writes 2427369394 # number of integer regfile writes 345system.cpu.fp_regfile_reads 71525918 # number of floating regfile reads 346system.cpu.fp_regfile_writes 50683175 # number of floating regfile writes 347system.cpu.misc_regfile_reads 4109052133 # number of misc regfile reads 348system.cpu.misc_regfile_writes 13776084 # number of misc regfile writes 349system.cpu.icache.replacements 27555 # number of replacements 350system.cpu.icache.tagsinuse 1659.051734 # Cycle average of tags in use 351system.cpu.icache.total_refs 417829104 # Total number of references to valid blocks. 352system.cpu.icache.sampled_refs 29252 # Sample count of references to valid blocks. 353system.cpu.icache.avg_refs 14283.779024 # Average number of references to valid blocks. |
| 354system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 354system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 355system.cpu.icache.occ_blocks::cpu.inst 1657.357291 # Average occupied blocks per requestor 356system.cpu.icache.occ_percent::cpu.inst 0.809256 # Average percentage of cache occupancy 357system.cpu.icache.occ_percent::total 0.809256 # Average percentage of cache occupancy 358system.cpu.icache.ReadReq_hits::cpu.inst 420900012 # number of ReadReq hits 359system.cpu.icache.ReadReq_hits::total 420900012 # number of ReadReq hits 360system.cpu.icache.demand_hits::cpu.inst 420900012 # number of demand (read+write) hits 361system.cpu.icache.demand_hits::total 420900012 # number of demand (read+write) hits 362system.cpu.icache.overall_hits::cpu.inst 420900012 # number of overall hits 363system.cpu.icache.overall_hits::total 420900012 # number of overall hits 364system.cpu.icache.ReadReq_misses::cpu.inst 35278 # number of ReadReq misses 365system.cpu.icache.ReadReq_misses::total 35278 # number of ReadReq misses 366system.cpu.icache.demand_misses::cpu.inst 35278 # number of demand (read+write) misses 367system.cpu.icache.demand_misses::total 35278 # number of demand (read+write) misses 368system.cpu.icache.overall_misses::cpu.inst 35278 # number of overall misses 369system.cpu.icache.overall_misses::total 35278 # number of overall misses 370system.cpu.icache.ReadReq_miss_latency::cpu.inst 347510000 # number of ReadReq miss cycles 371system.cpu.icache.ReadReq_miss_latency::total 347510000 # number of ReadReq miss cycles 372system.cpu.icache.demand_miss_latency::cpu.inst 347510000 # number of demand (read+write) miss cycles 373system.cpu.icache.demand_miss_latency::total 347510000 # number of demand (read+write) miss cycles 374system.cpu.icache.overall_miss_latency::cpu.inst 347510000 # number of overall miss cycles 375system.cpu.icache.overall_miss_latency::total 347510000 # number of overall miss cycles 376system.cpu.icache.ReadReq_accesses::cpu.inst 420935290 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.ReadReq_accesses::total 420935290 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.demand_accesses::cpu.inst 420935290 # number of demand (read+write) accesses 379system.cpu.icache.demand_accesses::total 420935290 # number of demand (read+write) accesses 380system.cpu.icache.overall_accesses::cpu.inst 420935290 # number of overall (read+write) accesses 381system.cpu.icache.overall_accesses::total 420935290 # number of overall (read+write) accesses | 355system.cpu.icache.occ_blocks::cpu.inst 1659.051734 # Average occupied blocks per requestor 356system.cpu.icache.occ_percent::cpu.inst 0.810084 # Average percentage of cache occupancy 357system.cpu.icache.occ_percent::total 0.810084 # Average percentage of cache occupancy 358system.cpu.icache.ReadReq_hits::cpu.inst 417833790 # number of ReadReq hits 359system.cpu.icache.ReadReq_hits::total 417833790 # number of ReadReq hits 360system.cpu.icache.demand_hits::cpu.inst 417833790 # number of demand (read+write) hits 361system.cpu.icache.demand_hits::total 417833790 # number of demand (read+write) hits 362system.cpu.icache.overall_hits::cpu.inst 417833790 # number of overall hits 363system.cpu.icache.overall_hits::total 417833790 # number of overall hits 364system.cpu.icache.ReadReq_misses::cpu.inst 35126 # number of ReadReq misses 365system.cpu.icache.ReadReq_misses::total 35126 # number of ReadReq misses 366system.cpu.icache.demand_misses::cpu.inst 35126 # number of demand (read+write) misses 367system.cpu.icache.demand_misses::total 35126 # number of demand (read+write) misses 368system.cpu.icache.overall_misses::cpu.inst 35126 # number of overall misses 369system.cpu.icache.overall_misses::total 35126 # number of overall misses 370system.cpu.icache.ReadReq_miss_latency::cpu.inst 348458500 # number of ReadReq miss cycles 371system.cpu.icache.ReadReq_miss_latency::total 348458500 # number of ReadReq miss cycles 372system.cpu.icache.demand_miss_latency::cpu.inst 348458500 # number of demand (read+write) miss cycles 373system.cpu.icache.demand_miss_latency::total 348458500 # number of demand (read+write) miss cycles 374system.cpu.icache.overall_miss_latency::cpu.inst 348458500 # number of overall miss cycles 375system.cpu.icache.overall_miss_latency::total 348458500 # number of overall miss cycles 376system.cpu.icache.ReadReq_accesses::cpu.inst 417868916 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.ReadReq_accesses::total 417868916 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.demand_accesses::cpu.inst 417868916 # number of demand (read+write) accesses 379system.cpu.icache.demand_accesses::total 417868916 # number of demand (read+write) accesses 380system.cpu.icache.overall_accesses::cpu.inst 417868916 # number of overall (read+write) accesses 381system.cpu.icache.overall_accesses::total 417868916 # number of overall (read+write) accesses |
| 382system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses 383system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses 384system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses 385system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses 386system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses 387system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses | 382system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses 383system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses 384system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses 385system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses 386system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses 387system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses |
| 388system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9850.615114 # average ReadReq miss latency 389system.cpu.icache.ReadReq_avg_miss_latency::total 9850.615114 # average ReadReq miss latency 390system.cpu.icache.demand_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency 391system.cpu.icache.demand_avg_miss_latency::total 9850.615114 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::total 9850.615114 # average overall miss latency | 388system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9920.244264 # average ReadReq miss latency 389system.cpu.icache.ReadReq_avg_miss_latency::total 9920.244264 # average ReadReq miss latency 390system.cpu.icache.demand_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency 391system.cpu.icache.demand_avg_miss_latency::total 9920.244264 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::total 9920.244264 # average overall miss latency |
| 394system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 399system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 400system.cpu.icache.fast_writes 0 # number of fast writes performed 401system.cpu.icache.cache_copies 0 # number of cache copies performed | 394system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 399system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 400system.cpu.icache.fast_writes 0 # number of fast writes performed 401system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 402system.cpu.icache.ReadReq_mshr_hits::cpu.inst 933 # number of ReadReq MSHR hits 403system.cpu.icache.ReadReq_mshr_hits::total 933 # number of ReadReq MSHR hits 404system.cpu.icache.demand_mshr_hits::cpu.inst 933 # number of demand (read+write) MSHR hits 405system.cpu.icache.demand_mshr_hits::total 933 # number of demand (read+write) MSHR hits 406system.cpu.icache.overall_mshr_hits::cpu.inst 933 # number of overall MSHR hits 407system.cpu.icache.overall_mshr_hits::total 933 # number of overall MSHR hits 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34345 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 34345 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 34345 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 34345 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 34345 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 34345 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 217293500 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 217293500 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 217293500 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 217293500 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 217293500 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 217293500 # number of overall MSHR miss cycles | 402system.cpu.icache.ReadReq_mshr_hits::cpu.inst 940 # number of ReadReq MSHR hits 403system.cpu.icache.ReadReq_mshr_hits::total 940 # number of ReadReq MSHR hits 404system.cpu.icache.demand_mshr_hits::cpu.inst 940 # number of demand (read+write) MSHR hits 405system.cpu.icache.demand_mshr_hits::total 940 # number of demand (read+write) MSHR hits 406system.cpu.icache.overall_mshr_hits::cpu.inst 940 # number of overall MSHR hits 407system.cpu.icache.overall_mshr_hits::total 940 # number of overall MSHR hits 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34186 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 34186 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 34186 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 34186 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 34186 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 34186 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218551000 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 218551000 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218551000 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 218551000 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218551000 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 218551000 # number of overall MSHR miss cycles |
| 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses | 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses |
| 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6326.787014 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6326.787014 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency | 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6392.997133 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6392.997133 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency |
| 432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 433system.cpu.dcache.replacements 1532802 # number of replacements 434system.cpu.dcache.tagsinuse 4094.906416 # Cycle average of tags in use 435system.cpu.dcache.total_refs 1033702432 # Total number of references to valid blocks. 436system.cpu.dcache.sampled_refs 1536898 # Sample count of references to valid blocks. 437system.cpu.dcache.avg_refs 672.590134 # Average number of references to valid blocks. | 433system.cpu.dcache.replacements 1533020 # number of replacements 434system.cpu.dcache.tagsinuse 4094.909429 # Cycle average of tags in use 435system.cpu.dcache.total_refs 1033013851 # Total number of references to valid blocks. 436system.cpu.dcache.sampled_refs 1537116 # Sample count of references to valid blocks. 437system.cpu.dcache.avg_refs 672.046775 # Average number of references to valid blocks. |
| 438system.cpu.dcache.warmup_cycle 306710000 # Cycle when the warmup percentage was hit. | 438system.cpu.dcache.warmup_cycle 306710000 # Cycle when the warmup percentage was hit. |
| 439system.cpu.dcache.occ_blocks::cpu.data 4094.906416 # Average occupied blocks per requestor 440system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy 441system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy 442system.cpu.dcache.ReadReq_hits::cpu.data 757546654 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 757546654 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.data 276115180 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 276115180 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.data 11970 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 11970 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.data 11608 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 11608 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.data 1033661834 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 1033661834 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.data 1033661834 # number of overall hits 453system.cpu.dcache.overall_hits::total 1033661834 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.data 2867388 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 2867388 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.data 820498 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 820498 # number of WriteReq misses 458system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses 459system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses 460system.cpu.dcache.demand_misses::cpu.data 3687886 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 3687886 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 3687886 # number of overall misses 463system.cpu.dcache.overall_misses::total 3687886 # number of overall misses 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 99520769500 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 99520769500 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963338500 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 33963338500 # number of WriteReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216500 # number of LoadLockedReq miss cycles 469system.cpu.dcache.LoadLockedReq_miss_latency::total 216500 # number of LoadLockedReq miss cycles 470system.cpu.dcache.demand_miss_latency::cpu.data 133484108000 # number of demand (read+write) miss cycles 471system.cpu.dcache.demand_miss_latency::total 133484108000 # number of demand (read+write) miss cycles 472system.cpu.dcache.overall_miss_latency::cpu.data 133484108000 # number of overall miss cycles 473system.cpu.dcache.overall_miss_latency::total 133484108000 # number of overall miss cycles 474system.cpu.dcache.ReadReq_accesses::cpu.data 760414042 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.ReadReq_accesses::total 760414042 # number of ReadReq accesses(hits+misses) | 439system.cpu.dcache.occ_blocks::cpu.data 4094.909429 # Average occupied blocks per requestor 440system.cpu.dcache.occ_percent::cpu.data 0.999734 # Average percentage of cache occupancy 441system.cpu.dcache.occ_percent::total 0.999734 # Average percentage of cache occupancy 442system.cpu.dcache.ReadReq_hits::cpu.data 756858216 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 756858216 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.data 276115103 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 276115103 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.data 11921 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 11921 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.data 11576 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 11576 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.data 1032973319 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 1032973319 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.data 1032973319 # number of overall hits 453system.cpu.dcache.overall_hits::total 1032973319 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.data 2483728 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 2483728 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.data 820575 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 820575 # number of WriteReq misses 458system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 459system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses 460system.cpu.dcache.demand_misses::cpu.data 3304303 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 3304303 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 3304303 # number of overall misses 463system.cpu.dcache.overall_misses::total 3304303 # number of overall misses 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 90046240500 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 90046240500 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963890000 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 33963890000 # number of WriteReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles 469system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles 470system.cpu.dcache.demand_miss_latency::cpu.data 124010130500 # number of demand (read+write) miss cycles 471system.cpu.dcache.demand_miss_latency::total 124010130500 # number of demand (read+write) miss cycles 472system.cpu.dcache.overall_miss_latency::cpu.data 124010130500 # number of overall miss cycles 473system.cpu.dcache.overall_miss_latency::total 124010130500 # number of overall miss cycles 474system.cpu.dcache.ReadReq_accesses::cpu.data 759341944 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.ReadReq_accesses::total 759341944 # number of ReadReq accesses(hits+misses) |
| 476system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) | 476system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) |
| 478system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11976 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.LoadLockedReq_accesses::total 11976 # number of LoadLockedReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::cpu.data 11608 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.StoreCondReq_accesses::total 11608 # number of StoreCondReq accesses(hits+misses) 482system.cpu.dcache.demand_accesses::cpu.data 1037349720 # number of demand (read+write) accesses 483system.cpu.dcache.demand_accesses::total 1037349720 # number of demand (read+write) accesses 484system.cpu.dcache.overall_accesses::cpu.data 1037349720 # number of overall (read+write) accesses 485system.cpu.dcache.overall_accesses::total 1037349720 # number of overall (read+write) accesses 486system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003771 # miss rate for ReadReq accesses 487system.cpu.dcache.ReadReq_miss_rate::total 0.003771 # miss rate for ReadReq accesses | 478system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11925 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.LoadLockedReq_accesses::total 11925 # number of LoadLockedReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::cpu.data 11576 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.StoreCondReq_accesses::total 11576 # number of StoreCondReq accesses(hits+misses) 482system.cpu.dcache.demand_accesses::cpu.data 1036277622 # number of demand (read+write) accesses 483system.cpu.dcache.demand_accesses::total 1036277622 # number of demand (read+write) accesses 484system.cpu.dcache.overall_accesses::cpu.data 1036277622 # number of overall (read+write) accesses 485system.cpu.dcache.overall_accesses::total 1036277622 # number of overall (read+write) accesses 486system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003271 # miss rate for ReadReq accesses 487system.cpu.dcache.ReadReq_miss_rate::total 0.003271 # miss rate for ReadReq accesses |
| 488system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002963 # miss rate for WriteReq accesses 489system.cpu.dcache.WriteReq_miss_rate::total 0.002963 # miss rate for WriteReq accesses | 488system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002963 # miss rate for WriteReq accesses 489system.cpu.dcache.WriteReq_miss_rate::total 0.002963 # miss rate for WriteReq accesses |
| 490system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000501 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000501 # miss rate for LoadLockedReq accesses 492system.cpu.dcache.demand_miss_rate::cpu.data 0.003555 # miss rate for demand accesses 493system.cpu.dcache.demand_miss_rate::total 0.003555 # miss rate for demand accesses 494system.cpu.dcache.overall_miss_rate::cpu.data 0.003555 # miss rate for overall accesses 495system.cpu.dcache.overall_miss_rate::total 0.003555 # miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34707.814045 # average ReadReq miss latency 497system.cpu.dcache.ReadReq_avg_miss_latency::total 34707.814045 # average ReadReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41393.566468 # average WriteReq miss latency 499system.cpu.dcache.WriteReq_avg_miss_latency::total 41393.566468 # average WriteReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36083.333333 # average LoadLockedReq miss latency 501system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 36083.333333 # average LoadLockedReq miss latency 502system.cpu.dcache.demand_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency 503system.cpu.dcache.demand_avg_miss_latency::total 36195.291286 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::total 36195.291286 # average overall miss latency | 490system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000335 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000335 # miss rate for LoadLockedReq accesses 492system.cpu.dcache.demand_miss_rate::cpu.data 0.003189 # miss rate for demand accesses 493system.cpu.dcache.demand_miss_rate::total 0.003189 # miss rate for demand accesses 494system.cpu.dcache.overall_miss_rate::cpu.data 0.003189 # miss rate for overall accesses 495system.cpu.dcache.overall_miss_rate::total 0.003189 # miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36254.469290 # average ReadReq miss latency 497system.cpu.dcache.ReadReq_avg_miss_latency::total 36254.469290 # average ReadReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41390.354325 # average WriteReq miss latency 499system.cpu.dcache.WriteReq_avg_miss_latency::total 41390.354325 # average WriteReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35000 # average LoadLockedReq miss latency 501system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35000 # average LoadLockedReq miss latency 502system.cpu.dcache.demand_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency 503system.cpu.dcache.demand_avg_miss_latency::total 37529.890721 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::total 37529.890721 # average overall miss latency |
| 506system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 507system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 509system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 511system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked 512system.cpu.dcache.fast_writes 0 # number of fast writes performed 513system.cpu.dcache.cache_copies 0 # number of cache copies performed | 506system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 507system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 509system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 511system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked 512system.cpu.dcache.fast_writes 0 # number of fast writes performed 513system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 514system.cpu.dcache.writebacks::writebacks 108638 # number of writebacks 515system.cpu.dcache.writebacks::total 108638 # number of writebacks 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1403027 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 1403027 # number of ReadReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743038 # number of WriteReq MSHR hits 519system.cpu.dcache.WriteReq_mshr_hits::total 743038 # number of WriteReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits 522system.cpu.dcache.demand_mshr_hits::cpu.data 2146065 # number of demand (read+write) MSHR hits 523system.cpu.dcache.demand_mshr_hits::total 2146065 # number of demand (read+write) MSHR hits 524system.cpu.dcache.overall_mshr_hits::cpu.data 2146065 # number of overall MSHR hits 525system.cpu.dcache.overall_mshr_hits::total 2146065 # number of overall MSHR hits 526system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464361 # number of ReadReq MSHR misses 527system.cpu.dcache.ReadReq_mshr_misses::total 1464361 # number of ReadReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77460 # number of WriteReq MSHR misses 529system.cpu.dcache.WriteReq_mshr_misses::total 77460 # number of WriteReq MSHR misses 530system.cpu.dcache.demand_mshr_misses::cpu.data 1541821 # number of demand (read+write) MSHR misses 531system.cpu.dcache.demand_mshr_misses::total 1541821 # number of demand (read+write) MSHR misses 532system.cpu.dcache.overall_mshr_misses::cpu.data 1541821 # number of overall MSHR misses 533system.cpu.dcache.overall_mshr_misses::total 1541821 # number of overall MSHR misses 534system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50337065001 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.ReadReq_mshr_miss_latency::total 50337065001 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525124500 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525124500 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52862189501 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::total 52862189501 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52862189501 # number of overall MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::total 52862189501 # number of overall MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001926 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001926 # mshr miss rate for ReadReq accesses | 514system.cpu.dcache.writebacks::writebacks 108316 # number of writebacks 515system.cpu.dcache.writebacks::total 108316 # number of writebacks 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1019154 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 1019154 # number of ReadReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743098 # number of WriteReq MSHR hits 519system.cpu.dcache.WriteReq_mshr_hits::total 743098 # number of WriteReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 522system.cpu.dcache.demand_mshr_hits::cpu.data 1762252 # number of demand (read+write) MSHR hits 523system.cpu.dcache.demand_mshr_hits::total 1762252 # number of demand (read+write) MSHR hits 524system.cpu.dcache.overall_mshr_hits::cpu.data 1762252 # number of overall MSHR hits 525system.cpu.dcache.overall_mshr_hits::total 1762252 # number of overall MSHR hits 526system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464574 # number of ReadReq MSHR misses 527system.cpu.dcache.ReadReq_mshr_misses::total 1464574 # number of ReadReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77477 # number of WriteReq MSHR misses 529system.cpu.dcache.WriteReq_mshr_misses::total 77477 # number of WriteReq MSHR misses 530system.cpu.dcache.demand_mshr_misses::cpu.data 1542051 # number of demand (read+write) MSHR misses 531system.cpu.dcache.demand_mshr_misses::total 1542051 # number of demand (read+write) MSHR misses 532system.cpu.dcache.overall_mshr_misses::cpu.data 1542051 # number of overall MSHR misses 533system.cpu.dcache.overall_mshr_misses::total 1542051 # number of overall MSHR misses 534system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50338229502 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.ReadReq_mshr_miss_latency::total 50338229502 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525857500 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525857500 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52864087002 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::total 52864087002 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52864087002 # number of overall MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::total 52864087002 # number of overall MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001929 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001929 # mshr miss rate for ReadReq accesses |
| 544system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses | 544system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses |
| 546system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001486 # mshr miss rate for demand accesses 547system.cpu.dcache.demand_mshr_miss_rate::total 0.001486 # mshr miss rate for demand accesses 548system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001486 # mshr miss rate for overall accesses 549system.cpu.dcache.overall_mshr_miss_rate::total 0.001486 # mshr miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34374.764830 # average ReadReq mshr miss latency 551system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34374.764830 # average ReadReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32599.076943 # average WriteReq mshr miss latency 553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32599.076943 # average WriteReq mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34285.555522 # average overall mshr miss latency 555system.cpu.dcache.demand_avg_mshr_miss_latency::total 34285.555522 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34285.555522 # average overall mshr miss latency 557system.cpu.dcache.overall_avg_mshr_miss_latency::total 34285.555522 # average overall mshr miss latency | 546system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses 547system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses 548system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses 549system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34370.560656 # average ReadReq mshr miss latency 551system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34370.560656 # average ReadReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32601.384927 # average WriteReq mshr miss latency 553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32601.384927 # average WriteReq mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency 555system.cpu.dcache.demand_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency 557system.cpu.dcache.overall_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency |
| 558system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 558system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 559system.cpu.l2cache.replacements 1480261 # number of replacements 560system.cpu.l2cache.tagsinuse 32698.232813 # Cycle average of tags in use 561system.cpu.l2cache.total_refs 88469 # Total number of references to valid blocks. 562system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks. 563system.cpu.l2cache.avg_refs 0.058472 # Average number of references to valid blocks. | 559system.cpu.l2cache.replacements 1480259 # number of replacements 560system.cpu.l2cache.tagsinuse 32698.440647 # Cycle average of tags in use 561system.cpu.l2cache.total_refs 88180 # Total number of references to valid blocks. 562system.cpu.l2cache.sampled_refs 1513003 # Sample count of references to valid blocks. 563system.cpu.l2cache.avg_refs 0.058281 # Average number of references to valid blocks. |
| 564system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 564system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 565system.cpu.l2cache.occ_blocks::writebacks 3127.449947 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.inst 61.048059 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_blocks::cpu.data 29509.734807 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_percent::writebacks 0.095442 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.inst 0.001863 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::cpu.data 0.900566 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::total 0.997871 # Average percentage of cache occupancy 572system.cpu.l2cache.ReadReq_hits::cpu.inst 26144 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::cpu.data 53654 # number of ReadReq hits 574system.cpu.l2cache.ReadReq_hits::total 79798 # number of ReadReq hits 575system.cpu.l2cache.Writeback_hits::writebacks 108638 # number of Writeback hits 576system.cpu.l2cache.Writeback_hits::total 108638 # number of Writeback hits | 565system.cpu.l2cache.occ_blocks::writebacks 3112.320696 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.inst 61.394609 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_blocks::cpu.data 29524.725342 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_percent::writebacks 0.094980 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.inst 0.001874 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::cpu.data 0.901023 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::total 0.997877 # Average percentage of cache occupancy 572system.cpu.l2cache.ReadReq_hits::cpu.inst 25967 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::cpu.data 53813 # number of ReadReq hits 574system.cpu.l2cache.ReadReq_hits::total 79780 # number of ReadReq hits 575system.cpu.l2cache.Writeback_hits::writebacks 108316 # number of Writeback hits 576system.cpu.l2cache.Writeback_hits::total 108316 # number of Writeback hits |
| 577system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 578system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits | 577system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 578system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits |
| 579system.cpu.l2cache.ReadExReq_hits::cpu.data 6457 # number of ReadExReq hits 580system.cpu.l2cache.ReadExReq_hits::total 6457 # number of ReadExReq hits 581system.cpu.l2cache.demand_hits::cpu.inst 26144 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::cpu.data 60111 # number of demand (read+write) hits 583system.cpu.l2cache.demand_hits::total 86255 # number of demand (read+write) hits 584system.cpu.l2cache.overall_hits::cpu.inst 26144 # number of overall hits 585system.cpu.l2cache.overall_hits::cpu.data 60111 # number of overall hits 586system.cpu.l2cache.overall_hits::total 86255 # number of overall hits 587system.cpu.l2cache.ReadReq_misses::cpu.inst 3279 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::cpu.data 1410706 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 1413985 # number of ReadReq misses 590system.cpu.l2cache.UpgradeReq_misses::cpu.data 4920 # number of UpgradeReq misses 591system.cpu.l2cache.UpgradeReq_misses::total 4920 # number of UpgradeReq misses | 579system.cpu.l2cache.ReadExReq_hits::cpu.data 6462 # number of ReadExReq hits 580system.cpu.l2cache.ReadExReq_hits::total 6462 # number of ReadExReq hits 581system.cpu.l2cache.demand_hits::cpu.inst 25967 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::cpu.data 60275 # number of demand (read+write) hits 583system.cpu.l2cache.demand_hits::total 86242 # number of demand (read+write) hits 584system.cpu.l2cache.overall_hits::cpu.inst 25967 # number of overall hits 585system.cpu.l2cache.overall_hits::cpu.data 60275 # number of overall hits 586system.cpu.l2cache.overall_hits::total 86242 # number of overall hits 587system.cpu.l2cache.ReadReq_misses::cpu.inst 3285 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::cpu.data 1410760 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 1414045 # number of ReadReq misses 590system.cpu.l2cache.UpgradeReq_misses::cpu.data 4932 # number of UpgradeReq misses 591system.cpu.l2cache.UpgradeReq_misses::total 4932 # number of UpgradeReq misses |
| 592system.cpu.l2cache.ReadExReq_misses::cpu.data 66081 # number of ReadExReq misses 593system.cpu.l2cache.ReadExReq_misses::total 66081 # number of ReadExReq misses | 592system.cpu.l2cache.ReadExReq_misses::cpu.data 66081 # number of ReadExReq misses 593system.cpu.l2cache.ReadExReq_misses::total 66081 # number of ReadExReq misses |
| 594system.cpu.l2cache.demand_misses::cpu.inst 3279 # number of demand (read+write) misses 595system.cpu.l2cache.demand_misses::cpu.data 1476787 # number of demand (read+write) misses 596system.cpu.l2cache.demand_misses::total 1480066 # number of demand (read+write) misses 597system.cpu.l2cache.overall_misses::cpu.inst 3279 # number of overall misses 598system.cpu.l2cache.overall_misses::cpu.data 1476787 # number of overall misses 599system.cpu.l2cache.overall_misses::total 1480066 # number of overall misses 600system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 116051500 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48793887000 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadReq_miss_latency::total 48909938500 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2274851500 # number of ReadExReq miss cycles 604system.cpu.l2cache.ReadExReq_miss_latency::total 2274851500 # number of ReadExReq miss cycles 605system.cpu.l2cache.demand_miss_latency::cpu.inst 116051500 # number of demand (read+write) miss cycles 606system.cpu.l2cache.demand_miss_latency::cpu.data 51068738500 # number of demand (read+write) miss cycles 607system.cpu.l2cache.demand_miss_latency::total 51184790000 # number of demand (read+write) miss cycles 608system.cpu.l2cache.overall_miss_latency::cpu.inst 116051500 # number of overall miss cycles 609system.cpu.l2cache.overall_miss_latency::cpu.data 51068738500 # number of overall miss cycles 610system.cpu.l2cache.overall_miss_latency::total 51184790000 # number of overall miss cycles 611system.cpu.l2cache.ReadReq_accesses::cpu.inst 29423 # number of ReadReq accesses(hits+misses) 612system.cpu.l2cache.ReadReq_accesses::cpu.data 1464360 # number of ReadReq accesses(hits+misses) 613system.cpu.l2cache.ReadReq_accesses::total 1493783 # number of ReadReq accesses(hits+misses) 614system.cpu.l2cache.Writeback_accesses::writebacks 108638 # number of Writeback accesses(hits+misses) 615system.cpu.l2cache.Writeback_accesses::total 108638 # number of Writeback accesses(hits+misses) 616system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4923 # number of UpgradeReq accesses(hits+misses) 617system.cpu.l2cache.UpgradeReq_accesses::total 4923 # number of UpgradeReq accesses(hits+misses) 618system.cpu.l2cache.ReadExReq_accesses::cpu.data 72538 # number of ReadExReq accesses(hits+misses) 619system.cpu.l2cache.ReadExReq_accesses::total 72538 # number of ReadExReq accesses(hits+misses) 620system.cpu.l2cache.demand_accesses::cpu.inst 29423 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_accesses::cpu.data 1536898 # number of demand (read+write) accesses 622system.cpu.l2cache.demand_accesses::total 1566321 # number of demand (read+write) accesses 623system.cpu.l2cache.overall_accesses::cpu.inst 29423 # number of overall (read+write) accesses 624system.cpu.l2cache.overall_accesses::cpu.data 1536898 # number of overall (read+write) accesses 625system.cpu.l2cache.overall_accesses::total 1566321 # number of overall (read+write) accesses 626system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111443 # miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.963360 # miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_miss_rate::total 0.946580 # miss rate for ReadReq accesses 629system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999391 # miss rate for UpgradeReq accesses 630system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999391 # miss rate for UpgradeReq accesses 631system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910985 # miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_miss_rate::total 0.910985 # miss rate for ReadExReq accesses 633system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111443 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::cpu.data 0.960888 # miss rate for demand accesses 635system.cpu.l2cache.demand_miss_rate::total 0.944931 # miss rate for demand accesses 636system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111443 # miss rate for overall accesses 637system.cpu.l2cache.overall_miss_rate::cpu.data 0.960888 # miss rate for overall accesses 638system.cpu.l2cache.overall_miss_rate::total 0.944931 # miss rate for overall accesses 639system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35392.345227 # average ReadReq miss latency 640system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34588.274949 # average ReadReq miss latency 641system.cpu.l2cache.ReadReq_avg_miss_latency::total 34590.139570 # average ReadReq miss latency 642system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34425.197863 # average ReadExReq miss latency 643system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34425.197863 # average ReadExReq miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35392.345227 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34580.977826 # average overall miss latency 646system.cpu.l2cache.demand_avg_miss_latency::total 34582.775363 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35392.345227 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34580.977826 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::total 34582.775363 # average overall miss latency | 594system.cpu.l2cache.demand_misses::cpu.inst 3285 # number of demand (read+write) misses 595system.cpu.l2cache.demand_misses::cpu.data 1476841 # number of demand (read+write) misses 596system.cpu.l2cache.demand_misses::total 1480126 # number of demand (read+write) misses 597system.cpu.l2cache.overall_misses::cpu.inst 3285 # number of overall misses 598system.cpu.l2cache.overall_misses::cpu.data 1476841 # number of overall misses 599system.cpu.l2cache.overall_misses::total 1480126 # number of overall misses 600system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 116334500 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48797101500 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadReq_miss_latency::total 48913436000 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2274840000 # number of ReadExReq miss cycles 604system.cpu.l2cache.ReadExReq_miss_latency::total 2274840000 # number of ReadExReq miss cycles 605system.cpu.l2cache.demand_miss_latency::cpu.inst 116334500 # number of demand (read+write) miss cycles 606system.cpu.l2cache.demand_miss_latency::cpu.data 51071941500 # number of demand (read+write) miss cycles 607system.cpu.l2cache.demand_miss_latency::total 51188276000 # number of demand (read+write) miss cycles 608system.cpu.l2cache.overall_miss_latency::cpu.inst 116334500 # number of overall miss cycles 609system.cpu.l2cache.overall_miss_latency::cpu.data 51071941500 # number of overall miss cycles 610system.cpu.l2cache.overall_miss_latency::total 51188276000 # number of overall miss cycles 611system.cpu.l2cache.ReadReq_accesses::cpu.inst 29252 # number of ReadReq accesses(hits+misses) 612system.cpu.l2cache.ReadReq_accesses::cpu.data 1464573 # number of ReadReq accesses(hits+misses) 613system.cpu.l2cache.ReadReq_accesses::total 1493825 # number of ReadReq accesses(hits+misses) 614system.cpu.l2cache.Writeback_accesses::writebacks 108316 # number of Writeback accesses(hits+misses) 615system.cpu.l2cache.Writeback_accesses::total 108316 # number of Writeback accesses(hits+misses) 616system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4935 # number of UpgradeReq accesses(hits+misses) 617system.cpu.l2cache.UpgradeReq_accesses::total 4935 # number of UpgradeReq accesses(hits+misses) 618system.cpu.l2cache.ReadExReq_accesses::cpu.data 72543 # number of ReadExReq accesses(hits+misses) 619system.cpu.l2cache.ReadExReq_accesses::total 72543 # number of ReadExReq accesses(hits+misses) 620system.cpu.l2cache.demand_accesses::cpu.inst 29252 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_accesses::cpu.data 1537116 # number of demand (read+write) accesses 622system.cpu.l2cache.demand_accesses::total 1566368 # number of demand (read+write) accesses 623system.cpu.l2cache.overall_accesses::cpu.inst 29252 # number of overall (read+write) accesses 624system.cpu.l2cache.overall_accesses::cpu.data 1537116 # number of overall (read+write) accesses 625system.cpu.l2cache.overall_accesses::total 1566368 # number of overall (read+write) accesses 626system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.112300 # miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.963257 # miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_miss_rate::total 0.946593 # miss rate for ReadReq accesses 629system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999392 # miss rate for UpgradeReq accesses 630system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999392 # miss rate for UpgradeReq accesses 631system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910922 # miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_miss_rate::total 0.910922 # miss rate for ReadExReq accesses 633system.cpu.l2cache.demand_miss_rate::cpu.inst 0.112300 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::cpu.data 0.960787 # miss rate for demand accesses 635system.cpu.l2cache.demand_miss_rate::total 0.944941 # miss rate for demand accesses 636system.cpu.l2cache.overall_miss_rate::cpu.inst 0.112300 # miss rate for overall accesses 637system.cpu.l2cache.overall_miss_rate::cpu.data 0.960787 # miss rate for overall accesses 638system.cpu.l2cache.overall_miss_rate::total 0.944941 # miss rate for overall accesses 639system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35413.850837 # average ReadReq miss latency 640system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34589.229564 # average ReadReq miss latency 641system.cpu.l2cache.ReadReq_avg_miss_latency::total 34591.145261 # average ReadReq miss latency 642system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34425.023834 # average ReadExReq miss latency 643system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34425.023834 # average ReadExReq miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35413.850837 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34581.882207 # average overall miss latency 646system.cpu.l2cache.demand_avg_miss_latency::total 34583.728683 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35413.850837 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34581.882207 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::total 34583.728683 # average overall miss latency |
| 650system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.l2cache.fast_writes 0 # number of fast writes performed 657system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 650system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.l2cache.fast_writes 0 # number of fast writes performed 657system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 658system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 659system.cpu.l2cache.writebacks::total 66098 # number of writebacks | 658system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks 659system.cpu.l2cache.writebacks::total 66099 # number of writebacks |
| 660system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits | 660system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits |
| 661system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits 662system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits | 661system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 662system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits |
| 663system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits | 663system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits |
| 664system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits 665system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits | 664system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 665system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits |
| 666system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits | 666system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits |
| 667system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits 668system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits 669system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3268 # number of ReadReq MSHR misses 670system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410687 # number of ReadReq MSHR misses 671system.cpu.l2cache.ReadReq_mshr_misses::total 1413955 # number of ReadReq MSHR misses 672system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4920 # number of UpgradeReq MSHR misses 673system.cpu.l2cache.UpgradeReq_mshr_misses::total 4920 # number of UpgradeReq MSHR misses | 667system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 668system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits 669system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3274 # number of ReadReq MSHR misses 670system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410739 # number of ReadReq MSHR misses 671system.cpu.l2cache.ReadReq_mshr_misses::total 1414013 # number of ReadReq MSHR misses 672system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4932 # number of UpgradeReq MSHR misses 673system.cpu.l2cache.UpgradeReq_mshr_misses::total 4932 # number of UpgradeReq MSHR misses |
| 674system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66081 # number of ReadExReq MSHR misses 675system.cpu.l2cache.ReadExReq_mshr_misses::total 66081 # number of ReadExReq MSHR misses | 674system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66081 # number of ReadExReq MSHR misses 675system.cpu.l2cache.ReadExReq_mshr_misses::total 66081 # number of ReadExReq MSHR misses |
| 676system.cpu.l2cache.demand_mshr_misses::cpu.inst 3268 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.demand_mshr_misses::cpu.data 1476768 # number of demand (read+write) MSHR misses 678system.cpu.l2cache.demand_mshr_misses::total 1480036 # number of demand (read+write) MSHR misses 679system.cpu.l2cache.overall_mshr_misses::cpu.inst 3268 # number of overall MSHR misses 680system.cpu.l2cache.overall_mshr_misses::cpu.data 1476768 # number of overall MSHR misses 681system.cpu.l2cache.overall_mshr_misses::total 1480036 # number of overall MSHR misses 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105473000 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44226810500 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44332283500 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152520000 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152520000 # number of UpgradeReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049208000 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049208000 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105473000 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46276018500 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 46381491500 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105473000 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46276018500 # number of overall MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::total 46381491500 # number of overall MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111070 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963347 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.946560 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999391 # mshr miss rate for UpgradeReq accesses 699system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999391 # mshr miss rate for UpgradeReq accesses 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910985 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910985 # mshr miss rate for ReadExReq accesses 702system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111070 # mshr miss rate for demand accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960876 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::total 0.944912 # mshr miss rate for demand accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111070 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960876 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::total 0.944912 # mshr miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32274.479804 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.256870 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.390667 # average ReadReq mshr miss latency | 676system.cpu.l2cache.demand_mshr_misses::cpu.inst 3274 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.demand_mshr_misses::cpu.data 1476820 # number of demand (read+write) MSHR misses 678system.cpu.l2cache.demand_mshr_misses::total 1480094 # number of demand (read+write) MSHR misses 679system.cpu.l2cache.overall_mshr_misses::cpu.inst 3274 # number of overall MSHR misses 680system.cpu.l2cache.overall_mshr_misses::cpu.data 1476820 # number of overall MSHR misses 681system.cpu.l2cache.overall_mshr_misses::total 1480094 # number of overall MSHR misses 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105728000 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44228314000 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44334042000 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152892000 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152892000 # number of UpgradeReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049197000 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049197000 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105728000 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46277511000 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 46383239000 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105728000 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46277511000 # number of overall MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::total 46383239000 # number of overall MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963243 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.946572 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999392 # mshr miss rate for UpgradeReq accesses 699system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999392 # mshr miss rate for UpgradeReq accesses 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910922 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910922 # mshr miss rate for ReadExReq accesses 702system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for demand accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::total 0.944921 # mshr miss rate for demand accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::total 0.944921 # mshr miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32293.219304 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.167012 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.348237 # average ReadReq mshr miss latency |
| 711system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 712system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency | 711system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 712system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency |
| 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.547661 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.547661 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency | 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.381199 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.381199 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency |
| 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722 723---------- End Simulation Statistics ---------- | 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722 723---------- End Simulation Statistics ---------- |