| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.735495 # Number of seconds simulated 4sim_ticks 735495062500 # Number of ticks simulated 5final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.735495 # Number of seconds simulated 4sim_ticks 735495062500 # Number of ticks simulated 5final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 126424 # Simulator instruction rate (inst/s) 8host_op_rate 172171 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 67166483 # Simulator tick rate (ticks/s) 10host_mem_usage 230552 # Number of bytes of host memory used 11host_seconds 10950.33 # Real time elapsed on the host | 7host_inst_rate 70506 # Simulator instruction rate (inst/s) 8host_op_rate 96019 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37458496 # Simulator tick rate (ticks/s) 10host_mem_usage 237496 # Number of bytes of host memory used 11host_seconds 19634.93 # Real time elapsed on the host |
| 12sim_insts 1384379503 # Number of instructions simulated 13sim_ops 1885334256 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 94839680 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 4230336 # Number of bytes written to this memory 17system.physmem.num_reads 1481870 # Number of read requests responded to by this memory 18system.physmem.num_writes 66099 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 353 unchanged lines hidden (view full) --- 373system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses 374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency 375system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency 376system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 1384379503 # Number of instructions simulated 13sim_ops 1885334256 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 94839680 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 4230336 # Number of bytes written to this memory 17system.physmem.num_reads 1481870 # Number of read requests responded to by this memory 18system.physmem.num_writes 66099 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 353 unchanged lines hidden (view full) --- 373system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses 374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency 375system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency 376system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 381system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 382system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 381system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 382system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 383system.cpu.icache.fast_writes 0 # number of fast writes performed 384system.cpu.icache.cache_copies 0 # number of cache copies performed 385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 853 # number of ReadReq MSHR hits 386system.cpu.icache.ReadReq_mshr_hits::total 853 # number of ReadReq MSHR hits 387system.cpu.icache.demand_mshr_hits::cpu.inst 853 # number of demand (read+write) MSHR hits 388system.cpu.icache.demand_mshr_hits::total 853 # number of demand (read+write) MSHR hits 389system.cpu.icache.overall_mshr_hits::cpu.inst 853 # number of overall MSHR hits 390system.cpu.icache.overall_mshr_hits::total 853 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 469system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency 470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency 471system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked | 383system.cpu.icache.fast_writes 0 # number of fast writes performed 384system.cpu.icache.cache_copies 0 # number of cache copies performed 385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 853 # number of ReadReq MSHR hits 386system.cpu.icache.ReadReq_mshr_hits::total 853 # number of ReadReq MSHR hits 387system.cpu.icache.demand_mshr_hits::cpu.inst 853 # number of demand (read+write) MSHR hits 388system.cpu.icache.demand_mshr_hits::total 853 # number of demand (read+write) MSHR hits 389system.cpu.icache.overall_mshr_hits::cpu.inst 853 # number of overall MSHR hits 390system.cpu.icache.overall_mshr_hits::total 853 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 469system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency 470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency 471system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked |
| 477system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked | 477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 478system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 106560 # number of writebacks 482system.cpu.dcache.writebacks::total 106560 # number of writebacks 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904767 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 904767 # number of ReadReq MSHR hits 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743443 # number of WriteReq MSHR hits --- 110 unchanged lines hidden (view full) --- 596system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency 597system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency 598system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency 599system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency 600system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 601system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 602system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 603system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 478system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 106560 # number of writebacks 482system.cpu.dcache.writebacks::total 106560 # number of writebacks 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904767 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 904767 # number of ReadReq MSHR hits 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743443 # number of WriteReq MSHR hits --- 110 unchanged lines hidden (view full) --- 596system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency 597system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency 598system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency 599system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency 600system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 601system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 602system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 603system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 604system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 605system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 604system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 605system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 606system.cpu.l2cache.fast_writes 0 # number of fast writes performed 607system.cpu.l2cache.cache_copies 0 # number of cache copies performed 608system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks 609system.cpu.l2cache.writebacks::total 66099 # number of writebacks 610system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 611system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits 612system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits 613system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits --- 50 unchanged lines hidden --- | 606system.cpu.l2cache.fast_writes 0 # number of fast writes performed 607system.cpu.l2cache.cache_copies 0 # number of cache copies performed 608system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks 609system.cpu.l2cache.writebacks::total 66099 # number of writebacks 610system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 611system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits 612system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits 613system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits --- 50 unchanged lines hidden --- |