| stats.txt (11687:b3d5f0e9e258) | stats.txt (11754:c209cb86278a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.339013 # Number of seconds simulated 4sim_ticks 339012932000 # Number of ticks simulated 5final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.338999 # Number of seconds simulated 4sim_ticks 338998876000 # Number of ticks simulated 5final_tick 338998876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 218277 # Simulator instruction rate (inst/s) 8host_op_rate 268728 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 115505586 # Simulator tick rate (ticks/s) 10host_mem_usage 277356 # Number of bytes of host memory used 11host_seconds 2935.04 # Real time elapsed on the host | 7host_inst_rate 210128 # Simulator instruction rate (inst/s) 8host_op_rate 258696 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 111189218 # Simulator tick rate (ticks/s) 10host_mem_usage 277020 # Number of bytes of host memory used 11host_seconds 3048.85 # Real time elapsed on the host |
| 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 269632 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 48043328 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 12965504 # Number of bytes read from this memory 20system.physmem.bytes_read::total 61278464 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 269632 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 269632 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 4245696 # Number of bytes written to this memory 24system.physmem.bytes_written::total 4245696 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 4213 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 750677 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 202586 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 957476 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 66339 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 66339 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 795344 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 141715325 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 38244866 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 180755535 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 795344 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 795344 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 12523699 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 12523699 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 12523699 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 795344 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 141715325 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 38244866 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 193279235 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 957477 # Number of read requests accepted 45system.physmem.writeReqs 66339 # Number of write requests accepted 46system.physmem.readBursts 957477 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 66339 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 61258752 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 19776 # Total number of bytes read from write queue 50system.physmem.bytesWritten 4240576 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 61278528 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 4245696 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 309 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 54 # Number of DRAM write bursts merged with an existing one | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 268928 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 48012032 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 12961152 # Number of bytes read from this memory 20system.physmem.bytes_read::total 61242112 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 268928 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 268928 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 4244288 # Number of bytes written to this memory 24system.physmem.bytes_written::total 4244288 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 4202 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 750188 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 202518 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 956908 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 66317 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 66317 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 793301 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 141628883 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 38233613 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 180655797 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 793301 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 793301 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 12520065 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 12520065 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 12520065 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 793301 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 141628883 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 38233613 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 193175862 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 956909 # Number of read requests accepted 45system.physmem.writeReqs 66317 # Number of write requests accepted 46system.physmem.readBursts 956909 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 66317 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 61223936 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue 50system.physmem.bytesWritten 4238080 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 61242176 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 4244288 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 65 # Number of DRAM write bursts merged with an existing one |
| 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 19910 # Per bank write bursts 57system.physmem.perBankRdBursts::1 19533 # Per bank write bursts 58system.physmem.perBankRdBursts::2 657271 # Per bank write bursts 59system.physmem.perBankRdBursts::3 20982 # Per bank write bursts 60system.physmem.perBankRdBursts::4 19710 # Per bank write bursts 61system.physmem.perBankRdBursts::5 21143 # Per bank write bursts 62system.physmem.perBankRdBursts::6 19634 # Per bank write bursts 63system.physmem.perBankRdBursts::7 20055 # Per bank write bursts 64system.physmem.perBankRdBursts::8 19495 # Per bank write bursts 65system.physmem.perBankRdBursts::9 20079 # Per bank write bursts 66system.physmem.perBankRdBursts::10 19428 # Per bank write bursts 67system.physmem.perBankRdBursts::11 19728 # Per bank write bursts 68system.physmem.perBankRdBursts::12 19649 # Per bank write bursts 69system.physmem.perBankRdBursts::13 21208 # Per bank write bursts 70system.physmem.perBankRdBursts::14 19490 # Per bank write bursts 71system.physmem.perBankRdBursts::15 19853 # Per bank write bursts 72system.physmem.perBankWrBursts::0 4286 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 19928 # Per bank write bursts 57system.physmem.perBankRdBursts::1 19580 # Per bank write bursts 58system.physmem.perBankRdBursts::2 657267 # Per bank write bursts 59system.physmem.perBankRdBursts::3 20958 # Per bank write bursts 60system.physmem.perBankRdBursts::4 19729 # Per bank write bursts 61system.physmem.perBankRdBursts::5 20737 # Per bank write bursts 62system.physmem.perBankRdBursts::6 19560 # Per bank write bursts 63system.physmem.perBankRdBursts::7 19988 # Per bank write bursts 64system.physmem.perBankRdBursts::8 19522 # Per bank write bursts 65system.physmem.perBankRdBursts::9 20089 # Per bank write bursts 66system.physmem.perBankRdBursts::10 19525 # Per bank write bursts 67system.physmem.perBankRdBursts::11 19708 # Per bank write bursts 68system.physmem.perBankRdBursts::12 19661 # Per bank write bursts 69system.physmem.perBankRdBursts::13 21032 # Per bank write bursts 70system.physmem.perBankRdBursts::14 19553 # Per bank write bursts 71system.physmem.perBankRdBursts::15 19787 # Per bank write bursts 72system.physmem.perBankWrBursts::0 4255 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::1 4105 # Per bank write bursts | 73system.physmem.perBankWrBursts::1 4105 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::2 4145 # Per bank write bursts 75system.physmem.perBankWrBursts::3 4153 # Per bank write bursts 76system.physmem.perBankWrBursts::4 4249 # Per bank write bursts 77system.physmem.perBankWrBursts::5 4230 # Per bank write bursts 78system.physmem.perBankWrBursts::6 4173 # Per bank write bursts | 74system.physmem.perBankWrBursts::2 4143 # Per bank write bursts 75system.physmem.perBankWrBursts::3 4152 # Per bank write bursts 76system.physmem.perBankWrBursts::4 4244 # Per bank write bursts 77system.physmem.perBankWrBursts::5 4226 # Per bank write bursts 78system.physmem.perBankWrBursts::6 4174 # Per bank write bursts |
| 79system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::9 4096 # Per bank write bursts | 79system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::9 4096 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::10 4094 # Per bank write bursts | 82system.physmem.perBankWrBursts::10 4096 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::11 4097 # Per bank write bursts | 83system.physmem.perBankWrBursts::11 4097 # Per bank write bursts |
| 84system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 85system.physmem.perBankWrBursts::13 4096 # Per bank write bursts | 84system.physmem.perBankWrBursts::12 4097 # Per bank write bursts 85system.physmem.perBankWrBursts::13 4095 # Per bank write bursts |
| 86system.physmem.perBankWrBursts::14 4096 # Per bank write bursts | 86system.physmem.perBankWrBursts::14 4096 # Per bank write bursts |
| 87system.physmem.perBankWrBursts::15 4149 # Per bank write bursts | 87system.physmem.perBankWrBursts::15 4152 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 90system.physmem.totGap 339012921500 # Total gap between requests | 90system.physmem.totGap 338998865500 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 957477 # Read request sizes (log2) | 97system.physmem.readPktSize::6 956909 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 66339 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 764538 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 120546 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 15621 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 6697 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 6433 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 7720 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 9109 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 10145 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 6841 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 3643 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 2525 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 1571 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1107 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 66317 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 764114 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 120431 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 15489 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 6466 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 7783 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 9162 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 10166 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 6863 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 3709 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 2433 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 1574 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1088 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 644 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see |
| 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 537 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 883 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 1456 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 2089 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 2622 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 3068 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 3545 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 4065 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 4483 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 4939 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 5348 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 5856 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6147 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 4797 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 4234 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 4114 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 131 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 91 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 74 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 66 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 67 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 62 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 52 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 41 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 43 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 28 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 16 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 13 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 7 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 553 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 600 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 931 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 1459 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 2107 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 2610 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 3064 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 3520 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 4015 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 4546 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 4994 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 5464 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 5885 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6183 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 5988 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 4751 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 4208 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 4080 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 139 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 103 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 88 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 64 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 54 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 51 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 36 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 23 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see |
| 193system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see | 193system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see |
| 194system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see | 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see |
| 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 201system.physmem.bytesPerActivate::samples 195212 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 335.517735 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 192.597798 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 355.506182 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 64341 32.96% 32.96% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 60661 31.07% 64.03% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 15753 8.07% 72.10% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3211 1.64% 73.75% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 3578 1.83% 75.58% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2458 1.26% 76.84% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 2478 1.27% 78.11% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 34211 17.53% 95.64% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 8521 4.36% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 195212 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 3994 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 204.692539 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::gmean 35.349556 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::stdev 2360.542955 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::0-4095 3971 99.42% 99.42% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::4096-8191 10 0.25% 99.67% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::8192-12287 5 0.13% 99.80% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::12288-16383 1 0.03% 99.82% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.85% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.87% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::28672-32767 1 0.03% 99.90% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.92% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.95% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::69632-73727 1 0.03% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::98304-102399 1 0.03% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 3994 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 3994 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 16.589634 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 16.506417 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 1.926291 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16 3368 84.33% 84.33% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::17 17 0.43% 84.75% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::18 396 9.91% 94.67% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::19 46 1.15% 95.82% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20 24 0.60% 96.42% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::21 17 0.43% 96.85% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::22 21 0.53% 97.37% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::23 18 0.45% 97.82% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::24 15 0.38% 98.20% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::25 17 0.43% 98.62% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::26 13 0.33% 98.95% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::27 10 0.25% 99.20% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::28 7 0.18% 99.37% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::29 8 0.20% 99.57% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::30 8 0.20% 99.77% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::32 4 0.10% 99.87% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::33 1 0.03% 99.90% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::34 1 0.03% 99.92% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::35 1 0.03% 99.95% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::37 1 0.03% 99.97% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::39 1 0.03% 100.00% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::total 3994 # Writes before turning the bus around for reads 257system.physmem.totQLat 27473404757 # Total ticks spent queuing 258system.physmem.totMemAccLat 45420304757 # Total ticks spent from burst creation until serviced by the DRAM 259system.physmem.totBusLat 4785840000 # Total ticks spent in databus transfers 260system.physmem.avgQLat 28702.80 # Average queueing delay per DRAM burst | 201system.physmem.bytesPerActivate::samples 195260 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 335.246789 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 192.210032 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 355.737014 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 64653 33.11% 33.11% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 60691 31.08% 64.19% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 15519 7.95% 72.14% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3195 1.64% 73.78% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 3493 1.79% 75.57% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2388 1.22% 76.79% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 2513 1.29% 78.08% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 34304 17.57% 95.64% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 8504 4.36% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 195260 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 3991 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 173.742922 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::gmean 35.179059 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::stdev 1709.732000 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::0-4095 3971 99.50% 99.50% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.72% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::8192-12287 3 0.08% 99.80% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::12288-16383 3 0.08% 99.87% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.90% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.92% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.95% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.97% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::73728-77823 1 0.03% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::total 3991 # Reads before turning the bus around for writes 229system.physmem.wrPerTurnAround::samples 3991 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::mean 16.592333 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::gmean 16.512127 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::stdev 1.873555 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::16 3350 83.94% 83.94% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::17 21 0.53% 84.47% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::18 395 9.90% 94.36% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::19 55 1.38% 95.74% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20 24 0.60% 96.34% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::21 19 0.48% 96.82% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::22 17 0.43% 97.24% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::23 26 0.65% 97.90% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::24 20 0.50% 98.40% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::25 16 0.40% 98.80% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::26 9 0.23% 99.02% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::27 11 0.28% 99.30% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::28 7 0.18% 99.47% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::29 5 0.13% 99.60% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::30 4 0.10% 99.70% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::31 6 0.15% 99.85% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::32 1 0.03% 99.87% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::33 3 0.08% 99.95% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::34 2 0.05% 100.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::total 3991 # Writes before turning the bus around for reads 253system.physmem.totQLat 27417238749 # Total ticks spent queuing 254system.physmem.totMemAccLat 45353938749 # Total ticks spent from burst creation until serviced by the DRAM 255system.physmem.totBusLat 4783120000 # Total ticks spent in databus transfers 256system.physmem.avgQLat 28660.41 # Average queueing delay per DRAM burst |
| 261system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 257system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 262system.physmem.avgMemAccLat 47452.80 # Average memory access latency per DRAM burst 263system.physmem.avgRdBW 180.70 # Average DRAM read bandwidth in MiByte/s 264system.physmem.avgWrBW 12.51 # Average achieved write bandwidth in MiByte/s 265system.physmem.avgRdBWSys 180.76 # Average system read bandwidth in MiByte/s | 258system.physmem.avgMemAccLat 47410.41 # Average memory access latency per DRAM burst 259system.physmem.avgRdBW 180.60 # Average DRAM read bandwidth in MiByte/s 260system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s 261system.physmem.avgRdBWSys 180.66 # Average system read bandwidth in MiByte/s |
| 266system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s 267system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 268system.physmem.busUtil 1.51 # Data bus utilization in percentage 269system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads 270system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes 271system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing | 262system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s 263system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 264system.physmem.busUtil 1.51 # Data bus utilization in percentage 265system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads 266system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes 267system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing |
| 272system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing 273system.physmem.readRowHits 805066 # Number of row buffer hits during reads 274system.physmem.writeRowHits 23137 # Number of row buffer hits during writes 275system.physmem.readRowHitRate 84.11 # Row buffer hit rate for reads 276system.physmem.writeRowHitRate 34.91 # Row buffer hit rate for writes 277system.physmem.avgGap 331126.81 # Average gap between requests 278system.physmem.pageHitRate 80.92 # Row buffer hit rate, read and write combined 279system.physmem_0.actEnergy 894020820 # Energy for activate commands per rank (pJ) 280system.physmem_0.preEnergy 475164360 # Energy for precharge commands per rank (pJ) 281system.physmem_0.readEnergy 5699412180 # Energy for read commands per rank (pJ) 282system.physmem_0.writeEnergy 174541140 # Energy for write commands per rank (pJ) 283system.physmem_0.refreshEnergy 27331811520.000008 # Energy for refresh commands per rank (pJ) 284system.physmem_0.actBackEnergy 14462317590 # Energy for active background per rank (pJ) 285system.physmem_0.preBackEnergy 674820000 # Energy for precharge background per rank (pJ) 286system.physmem_0.actPowerDownEnergy 138340924320 # Energy for active power-down per rank (pJ) 287system.physmem_0.prePowerDownEnergy 704060640 # Energy for precharge power-down per rank (pJ) 288system.physmem_0.selfRefreshEnergy 673701120.000000 # Energy for self refresh per rank (pJ) 289system.physmem_0.totalEnergy 189477322380 # Total energy per rank (pJ) 290system.physmem_0.averagePower 558.908824 # Core power per rank (mW) 291system.physmem_0.totalIdleTime 305437641889 # Total Idle time Per DRAM Rank 292system.physmem_0.memoryStateTime::IDLE 528629764 # Time in different power states 293system.physmem_0.memoryStateTime::REF 11569144000 # Time in different power states 294system.physmem_0.memoryStateTime::SREF 223118500 # Time in different power states 295system.physmem_0.memoryStateTime::PRE_PDN 1833570381 # Time in different power states 296system.physmem_0.memoryStateTime::ACT 21477516347 # Time in different power states 297system.physmem_0.memoryStateTime::ACT_PDN 303380953008 # Time in different power states 298system.physmem_1.actEnergy 499878540 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 265665180 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 1134760200 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 171330840 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 25420895760.000004 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 7011060990 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 1362065280 # Energy for precharge background per rank (pJ) 305system.physmem_1.actPowerDownEnergy 70491607590 # Energy for active power-down per rank (pJ) 306system.physmem_1.prePowerDownEnergy 31027049280 # Energy for precharge power-down per rank (pJ) 307system.physmem_1.selfRefreshEnergy 25487678070 # Energy for self refresh per rank (pJ) 308system.physmem_1.totalEnergy 162872491950 # Total energy per rank (pJ) 309system.physmem_1.averagePower 480.431501 # Core power per rank (mW) 310system.physmem_1.totalIdleTime 320089357075 # Total Idle time Per DRAM Rank 311system.physmem_1.memoryStateTime::IDLE 2604072271 # Time in different power states 312system.physmem_1.memoryStateTime::REF 10809446000 # Time in different power states 313system.physmem_1.memoryStateTime::SREF 84703185250 # Time in different power states 314system.physmem_1.memoryStateTime::PRE_PDN 80799625521 # Time in different power states 315system.physmem_1.memoryStateTime::ACT 5510033904 # Time in different power states 316system.physmem_1.memoryStateTime::ACT_PDN 154586569054 # Time in different power states 317system.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 318system.cpu.branchPred.lookups 174656775 # Number of BP lookups 319system.cpu.branchPred.condPredicted 119110803 # Number of conditional branches predicted 320system.cpu.branchPred.condIncorrect 4015685 # Number of conditional branches incorrect 321system.cpu.branchPred.BTBLookups 96721345 # Number of BTB lookups 322system.cpu.branchPred.BTBHits 67754534 # Number of BTB hits | 268system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing 269system.physmem.readRowHits 804753 # Number of row buffer hits during reads 270system.physmem.writeRowHits 22823 # Number of row buffer hits during writes 271system.physmem.readRowHitRate 84.12 # Row buffer hit rate for reads 272system.physmem.writeRowHitRate 34.45 # Row buffer hit rate for writes 273system.physmem.avgGap 331304.00 # Average gap between requests 274system.physmem.pageHitRate 80.91 # Row buffer hit rate, read and write combined 275system.physmem_0.actEnergy 893206860 # Energy for activate commands per rank (pJ) 276system.physmem_0.preEnergy 474750705 # Energy for precharge commands per rank (pJ) 277system.physmem_0.readEnergy 5695906440 # Energy for read commands per rank (pJ) 278system.physmem_0.writeEnergy 174321900 # Energy for write commands per rank (pJ) 279system.physmem_0.refreshEnergy 27330582240.000008 # Energy for refresh commands per rank (pJ) 280system.physmem_0.actBackEnergy 14459296590 # Energy for active background per rank (pJ) 281system.physmem_0.preBackEnergy 677245920 # Energy for precharge background per rank (pJ) 282system.physmem_0.actPowerDownEnergy 138340780680 # Energy for active power-down per rank (pJ) 283system.physmem_0.prePowerDownEnergy 698740320 # Energy for precharge power-down per rank (pJ) 284system.physmem_0.selfRefreshEnergy 673162065.000000 # Energy for self refresh per rank (pJ) 285system.physmem_0.totalEnergy 189465949500 # Total energy per rank (pJ) 286system.physmem_0.averagePower 558.898453 # Core power per rank (mW) 287system.physmem_0.totalIdleTime 305423895331 # Total Idle time Per DRAM Rank 288system.physmem_0.memoryStateTime::IDLE 532417778 # Time in different power states 289system.physmem_0.memoryStateTime::REF 11568510000 # Time in different power states 290system.physmem_0.memoryStateTime::SREF 220427000 # Time in different power states 291system.physmem_0.memoryStateTime::PRE_PDN 1819753036 # Time in different power states 292system.physmem_0.memoryStateTime::ACT 21474052891 # Time in different power states 293system.physmem_0.memoryStateTime::ACT_PDN 303383715295 # Time in different power states 294system.physmem_1.actEnergy 500999520 # Energy for activate commands per rank (pJ) 295system.physmem_1.preEnergy 266260995 # Energy for precharge commands per rank (pJ) 296system.physmem_1.readEnergy 1134381780 # Energy for read commands per rank (pJ) 297system.physmem_1.writeEnergy 171346500 # Energy for write commands per rank (pJ) 298system.physmem_1.refreshEnergy 25447939920.000004 # Energy for refresh commands per rank (pJ) 299system.physmem_1.actBackEnergy 7069016310 # Energy for active background per rank (pJ) 300system.physmem_1.preBackEnergy 1362680640 # Energy for precharge background per rank (pJ) 301system.physmem_1.actPowerDownEnergy 70550856240 # Energy for active power-down per rank (pJ) 302system.physmem_1.prePowerDownEnergy 31070458080 # Energy for precharge power-down per rank (pJ) 303system.physmem_1.selfRefreshEnergy 25392894210 # Energy for self refresh per rank (pJ) 304system.physmem_1.totalEnergy 162967325295 # Total energy per rank (pJ) 305system.physmem_1.averagePower 480.731167 # Core power per rank (mW) 306system.physmem_1.totalIdleTime 319946801176 # Total Idle time Per DRAM Rank 307system.physmem_1.memoryStateTime::IDLE 2603762514 # Time in different power states 308system.physmem_1.memoryStateTime::REF 10820898000 # Time in different power states 309system.physmem_1.memoryStateTime::SREF 84317463250 # Time in different power states 310system.physmem_1.memoryStateTime::PRE_PDN 80912710040 # Time in different power states 311system.physmem_1.memoryStateTime::ACT 5627391560 # Time in different power states 312system.physmem_1.memoryStateTime::ACT_PDN 154716650636 # Time in different power states 313system.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 314system.cpu.branchPred.lookups 174659469 # Number of BP lookups 315system.cpu.branchPred.condPredicted 119114964 # Number of conditional branches predicted 316system.cpu.branchPred.condIncorrect 4015677 # Number of conditional branches incorrect 317system.cpu.branchPred.BTBLookups 96720579 # Number of BTB lookups 318system.cpu.branchPred.BTBHits 67753891 # Number of BTB hits |
| 323system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 319system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 324system.cpu.branchPred.BTBHitPct 70.051274 # BTB Hit Percentage 325system.cpu.branchPred.usedRAS 18785121 # Number of times the RAS was used to get a target. 326system.cpu.branchPred.RASInCorrect 1299599 # Number of incorrect RAS predictions. 327system.cpu.branchPred.indirectLookups 16716580 # Number of indirect predictor lookups. 328system.cpu.branchPred.indirectHits 16702336 # Number of indirect target hits. 329system.cpu.branchPred.indirectMisses 14244 # Number of indirect misses. 330system.cpu.branchPredindirectMispredicted 1279516 # Number of mispredicted indirect branches. | 320system.cpu.branchPred.BTBHitPct 70.051164 # BTB Hit Percentage 321system.cpu.branchPred.usedRAS 18782444 # Number of times the RAS was used to get a target. 322system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. 323system.cpu.branchPred.indirectLookups 16716760 # Number of indirect predictor lookups. 324system.cpu.branchPred.indirectHits 16702354 # Number of indirect target hits. 325system.cpu.branchPred.indirectMisses 14406 # Number of indirect misses. 326system.cpu.branchPredindirectMispredicted 1279517 # Number of mispredicted indirect branches. |
| 331system.cpu_clk_domain.clock 500 # Clock period in ticks | 327system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 332system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states | 328system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states |
| 333system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 334system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 337system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 354system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 355system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 356system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 357system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 358system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 359system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 360system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 361system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 329system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 330system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 350system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 351system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 352system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 353system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 354system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 355system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 356system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 357system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 362system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states | 358system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states |
| 363system.cpu.dtb.walker.walks 0 # Table walker walks requested 364system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 367system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 368system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 370system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 384system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 385system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 386system.cpu.dtb.read_accesses 0 # DTB read accesses 387system.cpu.dtb.write_accesses 0 # DTB write accesses 388system.cpu.dtb.inst_accesses 0 # ITB inst accesses 389system.cpu.dtb.hits 0 # DTB hits 390system.cpu.dtb.misses 0 # DTB misses 391system.cpu.dtb.accesses 0 # DTB accesses | 359system.cpu.dtb.walker.walks 0 # Table walker walks requested 360system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 363system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 366system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 380system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 381system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 382system.cpu.dtb.read_accesses 0 # DTB read accesses 383system.cpu.dtb.write_accesses 0 # DTB write accesses 384system.cpu.dtb.inst_accesses 0 # ITB inst accesses 385system.cpu.dtb.hits 0 # DTB hits 386system.cpu.dtb.misses 0 # DTB misses 387system.cpu.dtb.accesses 0 # DTB accesses |
| 392system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states | 388system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states |
| 393system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 394system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 395system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 397system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 398system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 400system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 414system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 415system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 416system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 417system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 418system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 419system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 420system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 421system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 389system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 390system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 391system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 392system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 393system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 394system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 396system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 410system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 411system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 412system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 413system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 414system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 415system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 416system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 417system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 422system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states | 418system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states |
| 423system.cpu.itb.walker.walks 0 # Table walker walks requested 424system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 425system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 426system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 427system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 428system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 429system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 430system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 445system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 446system.cpu.itb.read_accesses 0 # DTB read accesses 447system.cpu.itb.write_accesses 0 # DTB write accesses 448system.cpu.itb.inst_accesses 0 # ITB inst accesses 449system.cpu.itb.hits 0 # DTB hits 450system.cpu.itb.misses 0 # DTB misses 451system.cpu.itb.accesses 0 # DTB accesses 452system.cpu.workload.num_syscalls 673 # Number of system calls | 419system.cpu.itb.walker.walks 0 # Table walker walks requested 420system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 421system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 423system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 424system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 425system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 426system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 441system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 442system.cpu.itb.read_accesses 0 # DTB read accesses 443system.cpu.itb.write_accesses 0 # DTB write accesses 444system.cpu.itb.inst_accesses 0 # ITB inst accesses 445system.cpu.itb.hits 0 # DTB hits 446system.cpu.itb.misses 0 # DTB misses 447system.cpu.itb.accesses 0 # DTB accesses 448system.cpu.workload.num_syscalls 673 # Number of system calls |
| 453system.cpu.pwrStateResidencyTicks::ON 339012932000 # Cumulative time (in ticks) in various power states 454system.cpu.numCycles 678025865 # number of cpu cycles simulated | 449system.cpu.pwrStateResidencyTicks::ON 338998876000 # Cumulative time (in ticks) in various power states 450system.cpu.numCycles 677997753 # number of cpu cycles simulated |
| 455system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 456system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 451system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 452system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 457system.cpu.fetch.icacheStallCycles 34354212 # Number of cycles fetch is stalled on an Icache miss 458system.cpu.fetch.Insts 824273790 # Number of instructions fetch has processed 459system.cpu.fetch.Branches 174656775 # Number of branches that fetch encountered 460system.cpu.fetch.predictedBranches 103241991 # Number of branches that fetch has predicted taken 461system.cpu.fetch.Cycles 639159762 # Number of cycles fetch has run and was not squashing or blocked 462system.cpu.fetch.SquashCycles 8068079 # Number of cycles fetch has spent squashing 463system.cpu.fetch.MiscStallCycles 2457 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 453system.cpu.fetch.icacheStallCycles 35007390 # Number of cycles fetch is stalled on an Icache miss 454system.cpu.fetch.Insts 824275552 # Number of instructions fetch has processed 455system.cpu.fetch.Branches 174659469 # Number of branches that fetch encountered 456system.cpu.fetch.predictedBranches 103238689 # Number of branches that fetch has predicted taken 457system.cpu.fetch.Cycles 638483488 # Number of cycles fetch has run and was not squashing or blocked 458system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing 459system.cpu.fetch.MiscStallCycles 3174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 464system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps | 460system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps |
| 465system.cpu.fetch.IcacheWaitRetryStallCycles 3206 # Number of stall cycles due to full MSHR 466system.cpu.fetch.CacheLines 247740942 # Number of cache lines fetched 467system.cpu.fetch.IcacheSquashes 12520 # Number of outstanding Icache misses that were squashed 468system.cpu.fetch.rateDist::samples 677553693 # Number of instructions fetched each cycle (Total) 469system.cpu.fetch.rateDist::mean 1.500365 # Number of instructions fetched each cycle (Total) 470system.cpu.fetch.rateDist::stdev 1.263651 # Number of instructions fetched each cycle (Total) | 461system.cpu.fetch.IcacheWaitRetryStallCycles 3169 # Number of stall cycles due to full MSHR 462system.cpu.fetch.CacheLines 247736654 # Number of cache lines fetched 463system.cpu.fetch.IcacheSquashes 13165 # Number of outstanding Icache misses that were squashed 464system.cpu.fetch.rateDist::samples 677531262 # Number of instructions fetched each cycle (Total) 465system.cpu.fetch.rateDist::mean 1.500399 # Number of instructions fetched each cycle (Total) 466system.cpu.fetch.rateDist::stdev 1.263726 # Number of instructions fetched each cycle (Total) |
| 471system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 467system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 472system.cpu.fetch.rateDist::0 215486043 31.80% 31.80% # Number of instructions fetched each cycle (Total) 473system.cpu.fetch.rateDist::1 148340760 21.89% 53.70% # Number of instructions fetched each cycle (Total) 474system.cpu.fetch.rateDist::2 72943473 10.77% 64.46% # Number of instructions fetched each cycle (Total) 475system.cpu.fetch.rateDist::3 240783417 35.54% 100.00% # Number of instructions fetched each cycle (Total) | 468system.cpu.fetch.rateDist::0 215511441 31.81% 31.81% # Number of instructions fetched each cycle (Total) 469system.cpu.fetch.rateDist::1 148279019 21.89% 53.69% # Number of instructions fetched each cycle (Total) 470system.cpu.fetch.rateDist::2 72933920 10.76% 64.46% # Number of instructions fetched each cycle (Total) 471system.cpu.fetch.rateDist::3 240806882 35.54% 100.00% # Number of instructions fetched each cycle (Total) |
| 476system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 477system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 478system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 472system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 473system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 474system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 479system.cpu.fetch.rateDist::total 677553693 # Number of instructions fetched each cycle (Total) 480system.cpu.fetch.branchRate 0.257596 # Number of branch fetches per cycle 481system.cpu.fetch.rate 1.215697 # Number of inst fetches per cycle 482system.cpu.decode.IdleCycles 75112537 # Number of cycles decode is idle 483system.cpu.decode.BlockedCycles 258679606 # Number of cycles decode is blocked 484system.cpu.decode.RunCycles 277758053 # Number of cycles decode is running 485system.cpu.decode.UnblockCycles 61982472 # Number of cycles decode is unblocking 486system.cpu.decode.SquashCycles 4021025 # Number of cycles decode is squashing 487system.cpu.decode.BranchResolved 20810112 # Number of times decode resolved a branch 488system.cpu.decode.BranchMispred 13117 # Number of times decode detected a branch misprediction 489system.cpu.decode.DecodedInsts 924576668 # Number of instructions handled by decode 490system.cpu.decode.SquashedInsts 11804380 # Number of squashed instructions handled by decode 491system.cpu.rename.SquashCycles 4021025 # Number of cycles rename is squashing 492system.cpu.rename.IdleCycles 118056358 # Number of cycles rename is idle 493system.cpu.rename.BlockCycles 157938220 # Number of cycles rename is blocking 494system.cpu.rename.serializeStallCycles 213059 # count of cycles rename stalled for serializing inst 495system.cpu.rename.RunCycles 294555904 # Number of cycles rename is running 496system.cpu.rename.UnblockCycles 102769127 # Number of cycles rename is unblocking 497system.cpu.rename.RenamedInsts 906541450 # Number of instructions processed by rename 498system.cpu.rename.SquashedInsts 6890856 # Number of squashed instructions processed by rename 499system.cpu.rename.ROBFullEvents 27990855 # Number of times rename has blocked due to ROB full 500system.cpu.rename.IQFullEvents 2220094 # Number of times rename has blocked due to IQ full 501system.cpu.rename.LQFullEvents 49338949 # Number of times rename has blocked due to LQ full 502system.cpu.rename.SQFullEvents 500517 # Number of times rename has blocked due to SQ full 503system.cpu.rename.RenamedOperands 980921468 # Number of destination operands rename has renamed 504system.cpu.rename.RenameLookups 4318014727 # Number of register rename lookups that rename has made 505system.cpu.rename.int_rename_lookups 1001837715 # Number of integer rename lookups | 475system.cpu.fetch.rateDist::total 677531262 # Number of instructions fetched each cycle (Total) 476system.cpu.fetch.branchRate 0.257611 # Number of branch fetches per cycle 477system.cpu.fetch.rate 1.215750 # Number of inst fetches per cycle 478system.cpu.decode.IdleCycles 75755548 # Number of cycles decode is idle 479system.cpu.decode.BlockedCycles 258011846 # Number of cycles decode is blocked 480system.cpu.decode.RunCycles 277771746 # Number of cycles decode is running 481system.cpu.decode.UnblockCycles 61971111 # Number of cycles decode is unblocking 482system.cpu.decode.SquashCycles 4021011 # Number of cycles decode is squashing 483system.cpu.decode.BranchResolved 20808683 # Number of times decode resolved a branch 484system.cpu.decode.BranchMispred 13107 # Number of times decode detected a branch misprediction 485system.cpu.decode.DecodedInsts 924572936 # Number of instructions handled by decode 486system.cpu.decode.SquashedInsts 11806711 # Number of squashed instructions handled by decode 487system.cpu.rename.SquashCycles 4021011 # Number of cycles rename is squashing 488system.cpu.rename.IdleCycles 118697379 # Number of cycles rename is idle 489system.cpu.rename.BlockCycles 157348847 # Number of cycles rename is blocking 490system.cpu.rename.serializeStallCycles 212785 # count of cycles rename stalled for serializing inst 491system.cpu.rename.RunCycles 295131252 # Number of cycles rename is running 492system.cpu.rename.UnblockCycles 102119988 # Number of cycles rename is unblocking 493system.cpu.rename.RenamedInsts 906539563 # Number of instructions processed by rename 494system.cpu.rename.SquashedInsts 6891328 # Number of squashed instructions processed by rename 495system.cpu.rename.ROBFullEvents 27972681 # Number of times rename has blocked due to ROB full 496system.cpu.rename.IQFullEvents 2218640 # Number of times rename has blocked due to IQ full 497system.cpu.rename.LQFullEvents 49279009 # Number of times rename has blocked due to LQ full 498system.cpu.rename.SQFullEvents 483149 # Number of times rename has blocked due to SQ full 499system.cpu.rename.RenamedOperands 980928941 # Number of destination operands rename has renamed 500system.cpu.rename.RenameLookups 4318000809 # Number of register rename lookups that rename has made 501system.cpu.rename.int_rename_lookups 1001835244 # Number of integer rename lookups |
| 506system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups 507system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed | 502system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups 503system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed |
| 508system.cpu.rename.UndoneMaps 106143238 # Number of HB maps that are undone due to squashing 509system.cpu.rename.serializingInsts 6855 # count of serializing insts renamed 510system.cpu.rename.tempSerializingInsts 6838 # count of temporary serializing insts renamed 511system.cpu.rename.skidInsts 138815476 # count of insts added to the skid buffer 512system.cpu.memDep0.insertedLoads 271882151 # Number of loads inserted to the mem dependence unit. 513system.cpu.memDep0.insertedStores 160587217 # Number of stores inserted to the mem dependence unit. 514system.cpu.memDep0.conflictingLoads 6164479 # Number of conflicting loads. 515system.cpu.memDep0.conflictingStores 12153288 # Number of conflicting stores. 516system.cpu.iq.iqInstsAdded 899827421 # Number of instructions added to the IQ (excludes non-spec) 517system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ 518system.cpu.iq.iqInstsIssued 860030622 # Number of instructions issued 519system.cpu.iq.iqSquashedInstsIssued 9216880 # Number of squashed instructions issued 520system.cpu.iq.iqSquashedInstsExamined 111115045 # Number of squashed instructions iterated over during squash; mainly for profiling 521system.cpu.iq.iqSquashedOperandsExamined 244388609 # Number of squashed operands that are examined and possibly removed from graph 522system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed 523system.cpu.iq.issued_per_cycle::samples 677553693 # Number of insts issued each cycle 524system.cpu.iq.issued_per_cycle::mean 1.269317 # Number of insts issued each cycle 525system.cpu.iq.issued_per_cycle::stdev 1.101593 # Number of insts issued each cycle | 504system.cpu.rename.UndoneMaps 106150711 # Number of HB maps that are undone due to squashing 505system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed 506system.cpu.rename.tempSerializingInsts 6840 # count of temporary serializing insts renamed 507system.cpu.rename.skidInsts 138234074 # count of insts added to the skid buffer 508system.cpu.memDep0.insertedLoads 271880895 # Number of loads inserted to the mem dependence unit. 509system.cpu.memDep0.insertedStores 160585540 # Number of stores inserted to the mem dependence unit. 510system.cpu.memDep0.conflictingLoads 6163609 # Number of conflicting loads. 511system.cpu.memDep0.conflictingStores 12157039 # Number of conflicting stores. 512system.cpu.iq.iqInstsAdded 899825913 # Number of instructions added to the IQ (excludes non-spec) 513system.cpu.iq.iqNonSpecInstsAdded 12585 # Number of non-speculative instructions added to the IQ 514system.cpu.iq.iqInstsIssued 860027802 # Number of instructions issued 515system.cpu.iq.iqSquashedInstsIssued 9216351 # Number of squashed instructions issued 516system.cpu.iq.iqSquashedInstsExamined 111113540 # Number of squashed instructions iterated over during squash; mainly for profiling 517system.cpu.iq.iqSquashedOperandsExamined 244391790 # Number of squashed operands that are examined and possibly removed from graph 518system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed 519system.cpu.iq.issued_per_cycle::samples 677531262 # Number of insts issued each cycle 520system.cpu.iq.issued_per_cycle::mean 1.269355 # Number of insts issued each cycle 521system.cpu.iq.issued_per_cycle::stdev 1.103879 # Number of insts issued each cycle |
| 526system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 522system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 527system.cpu.iq.issued_per_cycle::0 214894884 31.72% 31.72% # Number of insts issued each cycle 528system.cpu.iq.issued_per_cycle::1 182407403 26.92% 58.64% # Number of insts issued each cycle 529system.cpu.iq.issued_per_cycle::2 175555467 25.91% 84.55% # Number of insts issued each cycle 530system.cpu.iq.issued_per_cycle::3 92273782 13.62% 98.17% # Number of insts issued each cycle 531system.cpu.iq.issued_per_cycle::4 12419846 1.83% 100.00% # Number of insts issued each cycle 532system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle | 523system.cpu.iq.issued_per_cycle::0 215443123 31.80% 31.80% # Number of insts issued each cycle 524system.cpu.iq.issued_per_cycle::1 182412778 26.92% 58.72% # Number of insts issued each cycle 525system.cpu.iq.issued_per_cycle::2 173833847 25.66% 84.38% # Number of insts issued each cycle 526system.cpu.iq.issued_per_cycle::3 93421038 13.79% 98.17% # Number of insts issued each cycle 527system.cpu.iq.issued_per_cycle::4 12418164 1.83% 100.00% # Number of insts issued each cycle 528system.cpu.iq.issued_per_cycle::5 2312 0.00% 100.00% # Number of insts issued each cycle |
| 533system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 534system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 535system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 536system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 537system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 538system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 529system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 530system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 531system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 532system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 533system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 534system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 539system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle | 535system.cpu.iq.issued_per_cycle::total 677531262 # Number of insts issued each cycle |
| 540system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 536system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 541system.cpu.iq.fu_full::IntAlu 66603323 23.99% 23.99% # attempts to use FU when none available 542system.cpu.iq.fu_full::IntMult 18142 0.01% 24.00% # attempts to use FU when none available | 537system.cpu.iq.fu_full::IntAlu 66604023 24.00% 24.00% # attempts to use FU when none available 538system.cpu.iq.fu_full::IntMult 18144 0.01% 24.00% # attempts to use FU when none available |
| 543system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available 544system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available 545system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available 546system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available 547system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available 548system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available 549system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available 550system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available --- 13 unchanged lines hidden (view full) --- 564system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available 565system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available 566system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available 567system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available 568system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available 569system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available 570system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available 571system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available | 539system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available 540system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available 541system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available 542system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available 543system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available 544system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available 545system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available 546system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available --- 13 unchanged lines hidden (view full) --- 560system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available 561system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available 562system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available 563system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available 564system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available 565system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available 566system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available 567system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available |
| 572system.cpu.iq.fu_full::MemRead 133475448 48.09% 72.32% # attempts to use FU when none available 573system.cpu.iq.fu_full::MemWrite 66440411 23.94% 96.25% # attempts to use FU when none available 574system.cpu.iq.fu_full::FloatMemRead 5100435 1.84% 98.09% # attempts to use FU when none available 575system.cpu.iq.fu_full::FloatMemWrite 5300037 1.91% 100.00% # attempts to use FU when none available | 568system.cpu.iq.fu_full::MemRead 132902314 47.88% 72.11% # attempts to use FU when none available 569system.cpu.iq.fu_full::MemWrite 66436214 23.93% 96.05% # attempts to use FU when none available 570system.cpu.iq.fu_full::FloatMemRead 5673709 2.04% 98.09% # attempts to use FU when none available 571system.cpu.iq.fu_full::FloatMemWrite 5298999 1.91% 100.00% # attempts to use FU when none available |
| 576system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 577system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 578system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 572system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 573system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 574system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 579system.cpu.iq.FU_type_0::IntAlu 413090046 48.03% 48.03% # Type of FU issued 580system.cpu.iq.FU_type_0::IntMult 5187659 0.60% 48.64% # Type of FU issued | 575system.cpu.iq.FU_type_0::IntAlu 413088657 48.03% 48.03% # Type of FU issued 576system.cpu.iq.FU_type_0::IntMult 5187663 0.60% 48.64% # Type of FU issued |
| 581system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued 582system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued 583system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued 584system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued 585system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued 586system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 48.64% # Type of FU issued 587system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued 588system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 48.64% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 596system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued 597system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued 598system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued 599system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued 600system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued 601system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued 602system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued 603system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued | 577system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued 578system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued 579system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued 580system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued 581system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued 582system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 48.64% # Type of FU issued 583system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued 584system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 48.64% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 592system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued 593system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued 594system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued 595system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued 596system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued 597system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued 598system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued 599system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued |
| 604system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued | 600system.cpu.iq.FU_type_0::SimdFloatCvt 2550152 0.30% 49.38% # Type of FU issued |
| 605system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued | 601system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued |
| 606system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued | 602system.cpu.iq.FU_type_0::SimdFloatMisc 11478195 1.33% 50.71% # Type of FU issued |
| 607system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued 608system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued 609system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued | 603system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued 604system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued 605system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued |
| 610system.cpu.iq.FU_type_0::MemRead 259646740 30.19% 80.90% # Type of FU issued 611system.cpu.iq.FU_type_0::MemWrite 153401509 17.84% 98.74% # Type of FU issued 612system.cpu.iq.FU_type_0::FloatMemRead 7019167 0.82% 99.55% # Type of FU issued | 606system.cpu.iq.FU_type_0::MemRead 259646328 30.19% 80.90% # Type of FU issued 607system.cpu.iq.FU_type_0::MemWrite 153400482 17.84% 98.74% # Type of FU issued 608system.cpu.iq.FU_type_0::FloatMemRead 7019166 0.82% 99.55% # Type of FU issued |
| 613system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued 614system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 615system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 609system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued 610system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 611system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 616system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued 617system.cpu.iq.rate 1.268433 # Inst issue rate 618system.cpu.iq.fu_busy_cnt 277574685 # FU busy when requested 619system.cpu.iq.fu_busy_rate 0.322750 # FU busy rate (busy events/executed inst) 620system.cpu.iq.int_inst_queue_reads 2622330507 # Number of integer instruction queue reads 621system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes 622system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses 623system.cpu.iq.fp_inst_queue_reads 62075995 # Number of floating instruction queue reads 624system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes 625system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses 626system.cpu.iq.int_alu_accesses 1101050958 # Number of integer alu accesses 627system.cpu.iq.fp_alu_accesses 36554349 # Number of floating point alu accesses 628system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores | 612system.cpu.iq.FU_type_0::total 860027802 # Type of FU issued 613system.cpu.iq.rate 1.268482 # Inst issue rate 614system.cpu.iq.fu_busy_cnt 277570292 # FU busy when requested 615system.cpu.iq.fu_busy_rate 0.322746 # FU busy rate (busy events/executed inst) 616system.cpu.iq.int_inst_queue_reads 2621725269 # Number of integer instruction queue reads 617system.cpu.iq.int_inst_queue_writes 980329256 # Number of integer instruction queue writes 618system.cpu.iq.int_inst_queue_wakeup_accesses 820080739 # Number of integer instruction queue wakeup accesses 619system.cpu.iq.fp_inst_queue_reads 62648240 # Number of floating instruction queue reads 620system.cpu.iq.fp_inst_queue_writes 30641595 # Number of floating instruction queue writes 621system.cpu.iq.fp_inst_queue_wakeup_accesses 24878674 # Number of floating instruction queue wakeup accesses 622system.cpu.iq.int_alu_accesses 1100471505 # Number of integer alu accesses 623system.cpu.iq.fp_alu_accesses 37126589 # Number of floating point alu accesses 624system.cpu.iew.lsq.thread0.forwLoads 13986954 # Number of loads that had data forwarded from stores |
| 629system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 625system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 630system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed 631system.cpu.iew.lsq.thread0.ignoredResponses 120 # Number of memory responses ignored because the instruction is squashed 632system.cpu.iew.lsq.thread0.memOrderViolation 18827 # Number of memory ordering violations 633system.cpu.iew.lsq.thread0.squashedStores 31606721 # Number of stores squashed | 626system.cpu.iew.lsq.thread0.squashedLoads 19639957 # Number of loads squashed 627system.cpu.iew.lsq.thread0.ignoredResponses 122 # Number of memory responses ignored because the instruction is squashed 628system.cpu.iew.lsq.thread0.memOrderViolation 18816 # Number of memory ordering violations 629system.cpu.iew.lsq.thread0.squashedStores 31605044 # Number of stores squashed |
| 634system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 635system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 630system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 631system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 636system.cpu.iew.lsq.thread0.rescheduledLoads 1918912 # Number of loads that were rescheduled 637system.cpu.iew.lsq.thread0.cacheBlocked 17820 # Number of times an access to memory failed due to the cache being blocked | 632system.cpu.iew.lsq.thread0.rescheduledLoads 1918903 # Number of loads that were rescheduled 633system.cpu.iew.lsq.thread0.cacheBlocked 17949 # Number of times an access to memory failed due to the cache being blocked |
| 638system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 634system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 639system.cpu.iew.iewSquashCycles 4021025 # Number of cycles IEW is squashing 640system.cpu.iew.iewBlockCycles 10591534 # Number of cycles IEW is blocking 641system.cpu.iew.iewUnblockCycles 6199 # Number of cycles IEW is unblocking 642system.cpu.iew.iewDispatchedInsts 899849877 # Number of instructions dispatched to IQ | 635system.cpu.iew.iewSquashCycles 4021011 # Number of cycles IEW is squashing 636system.cpu.iew.iewBlockCycles 10591594 # Number of cycles IEW is blocking 637system.cpu.iew.iewUnblockCycles 7946 # Number of cycles IEW is unblocking 638system.cpu.iew.iewDispatchedInsts 899848641 # Number of instructions dispatched to IQ |
| 643system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 639system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 644system.cpu.iew.iewDispLoadInsts 271882151 # Number of dispatched load instructions 645system.cpu.iew.iewDispStoreInsts 160587217 # Number of dispatched store instructions 646system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions 647system.cpu.iew.iewIQFullEvents 967 # Number of times the IQ has become full, causing a stall 648system.cpu.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall 649system.cpu.iew.memOrderViolationEvents 18827 # Number of memory order violations 650system.cpu.iew.predictedTakenIncorrect 3295145 # Number of branches that were predicted taken incorrectly 651system.cpu.iew.predictedNotTakenIncorrect 3289956 # Number of branches that were predicted not taken incorrectly 652system.cpu.iew.branchMispredicts 6585101 # Number of branch mispredicts detected at execute 653system.cpu.iew.iewExecutedInsts 850175089 # Number of executed instructions 654system.cpu.iew.iewExecLoadInsts 263374398 # Number of load instructions executed 655system.cpu.iew.iewExecSquashedInsts 9855533 # Number of squashed instructions skipped in execute | 640system.cpu.iew.iewDispLoadInsts 271880895 # Number of dispatched load instructions 641system.cpu.iew.iewDispStoreInsts 160585540 # Number of dispatched store instructions 642system.cpu.iew.iewDispNonSpecInsts 6845 # Number of dispatched non-speculative instructions 643system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall 644system.cpu.iew.iewLSQFullEvents 5082 # Number of times the LSQ has become full, causing a stall 645system.cpu.iew.memOrderViolationEvents 18816 # Number of memory order violations 646system.cpu.iew.predictedTakenIncorrect 3295133 # Number of branches that were predicted taken incorrectly 647system.cpu.iew.predictedNotTakenIncorrect 3290188 # Number of branches that were predicted not taken incorrectly 648system.cpu.iew.branchMispredicts 6585321 # Number of branch mispredicts detected at execute 649system.cpu.iew.iewExecutedInsts 850172394 # Number of executed instructions 650system.cpu.iew.iewExecLoadInsts 263373871 # Number of load instructions executed 651system.cpu.iew.iewExecSquashedInsts 9855408 # Number of squashed instructions skipped in execute |
| 656system.cpu.iew.exec_swp 0 # number of swp insts executed | 652system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 657system.cpu.iew.exec_nop 9874 # number of nop insts executed 658system.cpu.iew.exec_refs 416064413 # number of memory reference insts executed 659system.cpu.iew.exec_branches 143381564 # Number of branches executed 660system.cpu.iew.exec_stores 152690015 # Number of stores executed 661system.cpu.iew.exec_rate 1.253898 # Inst execution rate 662system.cpu.iew.wb_sent 846298256 # cumulative count of insts sent to commit 663system.cpu.iew.wb_count 844962326 # cumulative count of insts written-back 664system.cpu.iew.wb_producers 487342605 # num instructions producing a value 665system.cpu.iew.wb_consumers 808106527 # num instructions consuming a value 666system.cpu.iew.wb_rate 1.246210 # insts written-back per cycle 667system.cpu.iew.wb_fanout 0.603067 # average fanout of values written-back 668system.cpu.commit.commitSquashedInsts 103169288 # The number of squashed insts skipped by commit | 653system.cpu.iew.exec_nop 10143 # number of nop insts executed 654system.cpu.iew.exec_refs 416062863 # number of memory reference insts executed 655system.cpu.iew.exec_branches 143380865 # Number of branches executed 656system.cpu.iew.exec_stores 152688992 # Number of stores executed 657system.cpu.iew.exec_rate 1.253946 # Inst execution rate 658system.cpu.iew.wb_sent 846295545 # cumulative count of insts sent to commit 659system.cpu.iew.wb_count 844959413 # cumulative count of insts written-back 660system.cpu.iew.wb_producers 486195731 # num instructions producing a value 661system.cpu.iew.wb_consumers 804663900 # num instructions consuming a value 662system.cpu.iew.wb_rate 1.246257 # insts written-back per cycle 663system.cpu.iew.wb_fanout 0.604222 # average fanout of values written-back 664system.cpu.commit.commitSquashedInsts 103166103 # The number of squashed insts skipped by commit |
| 669system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards | 665system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards |
| 670system.cpu.commit.branchMispredicts 4002671 # The number of times a branch was mispredicted 671system.cpu.commit.committed_per_cycle::samples 662973012 # Number of insts commited each cycle 672system.cpu.commit.committed_per_cycle::mean 1.189687 # Number of insts commited each cycle 673system.cpu.commit.committed_per_cycle::stdev 2.047483 # Number of insts commited each cycle | 666system.cpu.commit.branchMispredicts 4002664 # The number of times a branch was mispredicted 667system.cpu.commit.committed_per_cycle::samples 662950558 # Number of insts commited each cycle 668system.cpu.commit.committed_per_cycle::mean 1.189727 # Number of insts commited each cycle 669system.cpu.commit.committed_per_cycle::stdev 2.047510 # Number of insts commited each cycle |
| 674system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 670system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 675system.cpu.commit.committed_per_cycle::0 372633677 56.21% 56.21% # Number of insts commited each cycle 676system.cpu.commit.committed_per_cycle::1 137240232 20.70% 76.91% # Number of insts commited each cycle 677system.cpu.commit.committed_per_cycle::2 51341106 7.74% 84.65% # Number of insts commited each cycle 678system.cpu.commit.committed_per_cycle::3 28220443 4.26% 88.91% # Number of insts commited each cycle 679system.cpu.commit.committed_per_cycle::4 14381462 2.17% 91.08% # Number of insts commited each cycle 680system.cpu.commit.committed_per_cycle::5 14774618 2.23% 93.31% # Number of insts commited each cycle 681system.cpu.commit.committed_per_cycle::6 7871678 1.19% 94.49% # Number of insts commited each cycle 682system.cpu.commit.committed_per_cycle::7 6561077 0.99% 95.48% # Number of insts commited each cycle 683system.cpu.commit.committed_per_cycle::8 29948719 4.52% 100.00% # Number of insts commited each cycle | 671system.cpu.commit.committed_per_cycle::0 372609039 56.20% 56.20% # Number of insts commited each cycle 672system.cpu.commit.committed_per_cycle::1 137243840 20.70% 76.91% # Number of insts commited each cycle 673system.cpu.commit.committed_per_cycle::2 51342182 7.74% 84.65% # Number of insts commited each cycle 674system.cpu.commit.committed_per_cycle::3 28218977 4.26% 88.91% # Number of insts commited each cycle 675system.cpu.commit.committed_per_cycle::4 14379686 2.17% 91.08% # Number of insts commited each cycle 676system.cpu.commit.committed_per_cycle::5 14774384 2.23% 93.31% # Number of insts commited each cycle 677system.cpu.commit.committed_per_cycle::6 7871744 1.19% 94.49% # Number of insts commited each cycle 678system.cpu.commit.committed_per_cycle::7 6561841 0.99% 95.48% # Number of insts commited each cycle 679system.cpu.commit.committed_per_cycle::8 29948865 4.52% 100.00% # Number of insts commited each cycle |
| 684system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 685system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 686system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 680system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 681system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 682system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 687system.cpu.commit.committed_per_cycle::total 662973012 # Number of insts commited each cycle | 683system.cpu.commit.committed_per_cycle::total 662950558 # Number of insts commited each cycle |
| 688system.cpu.commit.committedInsts 640654411 # Number of instructions committed 689system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed 690system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 691system.cpu.commit.refs 381221434 # Number of memory references committed 692system.cpu.commit.loads 252240938 # Number of loads committed 693system.cpu.commit.membars 5740 # Number of memory barriers committed 694system.cpu.commit.branches 137364860 # Number of branches committed 695system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 729system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 730system.cpu.commit.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction 731system.cpu.commit.op_class_0::MemWrite 125149822 15.87% 98.62% # Class of committed instruction 732system.cpu.commit.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction 733system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction 734system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 735system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 736system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction | 684system.cpu.commit.committedInsts 640654411 # Number of instructions committed 685system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed 686system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 687system.cpu.commit.refs 381221434 # Number of memory references committed 688system.cpu.commit.loads 252240938 # Number of loads committed 689system.cpu.commit.membars 5740 # Number of memory barriers committed 690system.cpu.commit.branches 137364860 # Number of branches committed 691system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 725system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 726system.cpu.commit.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction 727system.cpu.commit.op_class_0::MemWrite 125149822 15.87% 98.62% # Class of committed instruction 728system.cpu.commit.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction 729system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction 730system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 731system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 732system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction |
| 737system.cpu.commit.bw_lim_events 29948719 # number cycles where commit BW limit reached 738system.cpu.rob.rob_reads 1524914900 # The number of ROB reads 739system.cpu.rob.rob_writes 1798382781 # The number of ROB writes 740system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself 741system.cpu.idleCycles 472172 # Total number of cycles that the CPU has spent unscheduled due to idling | 733system.cpu.commit.bw_lim_events 29948865 # number cycles where commit BW limit reached 734system.cpu.rob.rob_reads 1524889115 # The number of ROB reads 735system.cpu.rob.rob_writes 1798376442 # The number of ROB writes 736system.cpu.timesIdled 10544 # Number of times that the entire CPU went into an idle state and unscheduled itself 737system.cpu.idleCycles 466491 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 742system.cpu.committedInsts 640649299 # Number of Instructions Simulated 743system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated | 738system.cpu.committedInsts 640649299 # Number of Instructions Simulated 739system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated |
| 744system.cpu.cpi 1.058342 # CPI: Cycles Per Instruction 745system.cpu.cpi_total 1.058342 # CPI: Total CPI of All Threads 746system.cpu.ipc 0.944874 # IPC: Instructions Per Cycle 747system.cpu.ipc_total 0.944874 # IPC: Total IPC of All Threads 748system.cpu.int_regfile_reads 868463326 # number of integer regfile reads 749system.cpu.int_regfile_writes 500698648 # number of integer regfile writes 750system.cpu.fp_regfile_reads 30616063 # number of floating regfile reads 751system.cpu.fp_regfile_writes 22959490 # number of floating regfile writes 752system.cpu.cc_regfile_reads 3322389826 # number of cc regfile reads 753system.cpu.cc_regfile_writes 369207773 # number of cc regfile writes 754system.cpu.misc_regfile_reads 606833337 # number of misc regfile reads | 740system.cpu.cpi 1.058298 # CPI: Cycles Per Instruction 741system.cpu.cpi_total 1.058298 # CPI: Total CPI of All Threads 742system.cpu.ipc 0.944914 # IPC: Instructions Per Cycle 743system.cpu.ipc_total 0.944914 # IPC: Total IPC of All Threads 744system.cpu.int_regfile_reads 868460616 # number of integer regfile reads 745system.cpu.int_regfile_writes 500698081 # number of integer regfile writes 746system.cpu.fp_regfile_reads 30616065 # number of floating regfile reads 747system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes 748system.cpu.cc_regfile_reads 3322380162 # number of cc regfile reads 749system.cpu.cc_regfile_writes 369206587 # number of cc regfile writes 750system.cpu.misc_regfile_reads 606831817 # number of misc regfile reads |
| 755system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes | 751system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes |
| 756system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 757system.cpu.dcache.tags.replacements 2756453 # number of replacements 758system.cpu.dcache.tags.tagsinuse 511.911144 # Cycle average of tags in use 759system.cpu.dcache.tags.total_refs 371050846 # Total number of references to valid blocks. 760system.cpu.dcache.tags.sampled_refs 2756965 # Sample count of references to valid blocks. 761system.cpu.dcache.tags.avg_refs 134.586709 # Average number of references to valid blocks. 762system.cpu.dcache.tags.warmup_cycle 285699000 # Cycle when the warmup percentage was hit. 763system.cpu.dcache.tags.occ_blocks::cpu.data 511.911144 # Average occupied blocks per requestor | 752system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 753system.cpu.dcache.tags.replacements 2756456 # number of replacements 754system.cpu.dcache.tags.tagsinuse 511.910987 # Cycle average of tags in use 755system.cpu.dcache.tags.total_refs 371049565 # Total number of references to valid blocks. 756system.cpu.dcache.tags.sampled_refs 2756968 # Sample count of references to valid blocks. 757system.cpu.dcache.tags.avg_refs 134.586098 # Average number of references to valid blocks. 758system.cpu.dcache.tags.warmup_cycle 285993000 # Cycle when the warmup percentage was hit. 759system.cpu.dcache.tags.occ_blocks::cpu.data 511.910987 # Average occupied blocks per requestor |
| 764system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy 765system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy 766system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 767system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id | 760system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy 761system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy 762system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 763system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id |
| 768system.cpu.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 769system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id | 764system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id 765system.cpu.dcache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id |
| 770system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 771system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 766system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 767system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 772system.cpu.dcache.tags.tag_accesses 751747893 # Number of tag accesses 773system.cpu.dcache.tags.data_accesses 751747893 # Number of data accesses 774system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 775system.cpu.dcache.ReadReq_hits::cpu.data 243127355 # number of ReadReq hits 776system.cpu.dcache.ReadReq_hits::total 243127355 # number of ReadReq hits 777system.cpu.dcache.WriteReq_hits::cpu.data 127907428 # number of WriteReq hits 778system.cpu.dcache.WriteReq_hits::total 127907428 # number of WriteReq hits | 768system.cpu.dcache.tags.tag_accesses 751745414 # Number of tag accesses 769system.cpu.dcache.tags.data_accesses 751745414 # Number of data accesses 770system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 771system.cpu.dcache.ReadReq_hits::cpu.data 243126159 # number of ReadReq hits 772system.cpu.dcache.ReadReq_hits::total 243126159 # number of ReadReq hits 773system.cpu.dcache.WriteReq_hits::cpu.data 127907378 # number of WriteReq hits 774system.cpu.dcache.WriteReq_hits::total 127907378 # number of WriteReq hits |
| 779system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits 780system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits 781system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 782system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 783system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 784system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits | 775system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits 776system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits 777system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 778system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 779system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 780system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits |
| 785system.cpu.dcache.demand_hits::cpu.data 371034783 # number of demand (read+write) hits 786system.cpu.dcache.demand_hits::total 371034783 # number of demand (read+write) hits 787system.cpu.dcache.overall_hits::cpu.data 371037940 # number of overall hits 788system.cpu.dcache.overall_hits::total 371037940 # number of overall hits 789system.cpu.dcache.ReadReq_misses::cpu.data 2401348 # number of ReadReq misses 790system.cpu.dcache.ReadReq_misses::total 2401348 # number of ReadReq misses 791system.cpu.dcache.WriteReq_misses::cpu.data 1044049 # number of WriteReq misses 792system.cpu.dcache.WriteReq_misses::total 1044049 # number of WriteReq misses | 781system.cpu.dcache.demand_hits::cpu.data 371033537 # number of demand (read+write) hits 782system.cpu.dcache.demand_hits::total 371033537 # number of demand (read+write) hits 783system.cpu.dcache.overall_hits::cpu.data 371036694 # number of overall hits 784system.cpu.dcache.overall_hits::total 371036694 # number of overall hits 785system.cpu.dcache.ReadReq_misses::cpu.data 2401303 # number of ReadReq misses 786system.cpu.dcache.ReadReq_misses::total 2401303 # number of ReadReq misses 787system.cpu.dcache.WriteReq_misses::cpu.data 1044099 # number of WriteReq misses 788system.cpu.dcache.WriteReq_misses::total 1044099 # number of WriteReq misses |
| 793system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses 794system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses 795system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 796system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 789system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses 790system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses 791system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 792system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 797system.cpu.dcache.demand_misses::cpu.data 3445397 # number of demand (read+write) misses 798system.cpu.dcache.demand_misses::total 3445397 # number of demand (read+write) misses 799system.cpu.dcache.overall_misses::cpu.data 3446044 # number of overall misses 800system.cpu.dcache.overall_misses::total 3446044 # number of overall misses 801system.cpu.dcache.ReadReq_miss_latency::cpu.data 80462385500 # number of ReadReq miss cycles 802system.cpu.dcache.ReadReq_miss_latency::total 80462385500 # number of ReadReq miss cycles 803system.cpu.dcache.WriteReq_miss_latency::cpu.data 10017236850 # number of WriteReq miss cycles 804system.cpu.dcache.WriteReq_miss_latency::total 10017236850 # number of WriteReq miss cycles | 793system.cpu.dcache.demand_misses::cpu.data 3445402 # number of demand (read+write) misses 794system.cpu.dcache.demand_misses::total 3445402 # number of demand (read+write) misses 795system.cpu.dcache.overall_misses::cpu.data 3446049 # number of overall misses 796system.cpu.dcache.overall_misses::total 3446049 # number of overall misses 797system.cpu.dcache.ReadReq_miss_latency::cpu.data 80431299000 # number of ReadReq miss cycles 798system.cpu.dcache.ReadReq_miss_latency::total 80431299000 # number of ReadReq miss cycles 799system.cpu.dcache.WriteReq_miss_latency::cpu.data 9946595850 # number of WriteReq miss cycles 800system.cpu.dcache.WriteReq_miss_latency::total 9946595850 # number of WriteReq miss cycles |
| 805system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles 806system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles | 801system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles 802system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles |
| 807system.cpu.dcache.demand_miss_latency::cpu.data 90479622350 # number of demand (read+write) miss cycles 808system.cpu.dcache.demand_miss_latency::total 90479622350 # number of demand (read+write) miss cycles 809system.cpu.dcache.overall_miss_latency::cpu.data 90479622350 # number of overall miss cycles 810system.cpu.dcache.overall_miss_latency::total 90479622350 # number of overall miss cycles 811system.cpu.dcache.ReadReq_accesses::cpu.data 245528703 # number of ReadReq accesses(hits+misses) 812system.cpu.dcache.ReadReq_accesses::total 245528703 # number of ReadReq accesses(hits+misses) | 803system.cpu.dcache.demand_miss_latency::cpu.data 90377894850 # number of demand (read+write) miss cycles 804system.cpu.dcache.demand_miss_latency::total 90377894850 # number of demand (read+write) miss cycles 805system.cpu.dcache.overall_miss_latency::cpu.data 90377894850 # number of overall miss cycles 806system.cpu.dcache.overall_miss_latency::total 90377894850 # number of overall miss cycles 807system.cpu.dcache.ReadReq_accesses::cpu.data 245527462 # number of ReadReq accesses(hits+misses) 808system.cpu.dcache.ReadReq_accesses::total 245527462 # number of ReadReq accesses(hits+misses) |
| 813system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 814system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 815system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) 816system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) 817system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) 818system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) 819system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 820system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) | 809system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 810system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 811system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) 812system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) 813system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) 814system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) 815system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 816system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) |
| 821system.cpu.dcache.demand_accesses::cpu.data 374480180 # number of demand (read+write) accesses 822system.cpu.dcache.demand_accesses::total 374480180 # number of demand (read+write) accesses 823system.cpu.dcache.overall_accesses::cpu.data 374483984 # number of overall (read+write) accesses 824system.cpu.dcache.overall_accesses::total 374483984 # number of overall (read+write) accesses | 817system.cpu.dcache.demand_accesses::cpu.data 374478939 # number of demand (read+write) accesses 818system.cpu.dcache.demand_accesses::total 374478939 # number of demand (read+write) accesses 819system.cpu.dcache.overall_accesses::cpu.data 374482743 # number of overall (read+write) accesses 820system.cpu.dcache.overall_accesses::total 374482743 # number of overall (read+write) accesses |
| 825system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses 826system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses | 821system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses 822system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses |
| 827system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008096 # miss rate for WriteReq accesses 828system.cpu.dcache.WriteReq_miss_rate::total 0.008096 # miss rate for WriteReq accesses | 823system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008097 # miss rate for WriteReq accesses 824system.cpu.dcache.WriteReq_miss_rate::total 0.008097 # miss rate for WriteReq accesses |
| 829system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses 830system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses 831system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses 832system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses | 825system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses 826system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses 827system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses 828system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses |
| 833system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses 834system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses | 829system.cpu.dcache.demand_miss_rate::cpu.data 0.009201 # miss rate for demand accesses 830system.cpu.dcache.demand_miss_rate::total 0.009201 # miss rate for demand accesses |
| 835system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses 836system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses | 831system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses 832system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses |
| 837system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33507.174096 # average ReadReq miss latency 838system.cpu.dcache.ReadReq_avg_miss_latency::total 33507.174096 # average ReadReq miss latency 839system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9594.604133 # average WriteReq miss latency 840system.cpu.dcache.WriteReq_avg_miss_latency::total 9594.604133 # average WriteReq miss latency | 833system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33494.856334 # average ReadReq miss latency 834system.cpu.dcache.ReadReq_avg_miss_latency::total 33494.856334 # average ReadReq miss latency 835system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9526.487287 # average WriteReq miss latency 836system.cpu.dcache.WriteReq_avg_miss_latency::total 9526.487287 # average WriteReq miss latency |
| 841system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency 842system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency | 837system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency 838system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency |
| 843system.cpu.dcache.demand_avg_miss_latency::cpu.data 26261.015015 # average overall miss latency 844system.cpu.dcache.demand_avg_miss_latency::total 26261.015015 # average overall miss latency 845system.cpu.dcache.overall_avg_miss_latency::cpu.data 26256.084470 # average overall miss latency 846system.cpu.dcache.overall_avg_miss_latency::total 26256.084470 # average overall miss latency 847system.cpu.dcache.blocked_cycles::no_mshrs 71 # number of cycles access was blocked 848system.cpu.dcache.blocked_cycles::no_targets 355259 # number of cycles access was blocked 849system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 850system.cpu.dcache.blocked::no_targets 4691 # number of cycles access was blocked 851system.cpu.dcache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked 852system.cpu.dcache.avg_blocked_cycles::no_targets 75.732040 # average number of cycles each access was blocked 853system.cpu.dcache.writebacks::writebacks 2756453 # number of writebacks 854system.cpu.dcache.writebacks::total 2756453 # number of writebacks 855system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365871 # number of ReadReq MSHR hits 856system.cpu.dcache.ReadReq_mshr_hits::total 365871 # number of ReadReq MSHR hits 857system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323013 # number of WriteReq MSHR hits 858system.cpu.dcache.WriteReq_mshr_hits::total 323013 # number of WriteReq MSHR hits | 839system.cpu.dcache.demand_avg_miss_latency::cpu.data 26231.451323 # average overall miss latency 840system.cpu.dcache.demand_avg_miss_latency::total 26231.451323 # average overall miss latency 841system.cpu.dcache.overall_avg_miss_latency::cpu.data 26226.526335 # average overall miss latency 842system.cpu.dcache.overall_avg_miss_latency::total 26226.526335 # average overall miss latency 843system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 844system.cpu.dcache.blocked_cycles::no_targets 336970 # number of cycles access was blocked 845system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 846system.cpu.dcache.blocked::no_targets 4742 # number of cycles access was blocked 847system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 848system.cpu.dcache.avg_blocked_cycles::no_targets 71.060734 # average number of cycles each access was blocked 849system.cpu.dcache.writebacks::writebacks 2756456 # number of writebacks 850system.cpu.dcache.writebacks::total 2756456 # number of writebacks 851system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365826 # number of ReadReq MSHR hits 852system.cpu.dcache.ReadReq_mshr_hits::total 365826 # number of ReadReq MSHR hits 853system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323069 # number of WriteReq MSHR hits 854system.cpu.dcache.WriteReq_mshr_hits::total 323069 # number of WriteReq MSHR hits |
| 859system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 860system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 855system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 856system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 861system.cpu.dcache.demand_mshr_hits::cpu.data 688884 # number of demand (read+write) MSHR hits 862system.cpu.dcache.demand_mshr_hits::total 688884 # number of demand (read+write) MSHR hits 863system.cpu.dcache.overall_mshr_hits::cpu.data 688884 # number of overall MSHR hits 864system.cpu.dcache.overall_mshr_hits::total 688884 # number of overall MSHR hits | 857system.cpu.dcache.demand_mshr_hits::cpu.data 688895 # number of demand (read+write) MSHR hits 858system.cpu.dcache.demand_mshr_hits::total 688895 # number of demand (read+write) MSHR hits 859system.cpu.dcache.overall_mshr_hits::cpu.data 688895 # number of overall MSHR hits 860system.cpu.dcache.overall_mshr_hits::total 688895 # number of overall MSHR hits |
| 865system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses 866system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses | 861system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses 862system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses |
| 867system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721036 # number of WriteReq MSHR misses 868system.cpu.dcache.WriteReq_mshr_misses::total 721036 # number of WriteReq MSHR misses | 863system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721030 # number of WriteReq MSHR misses 864system.cpu.dcache.WriteReq_mshr_misses::total 721030 # number of WriteReq MSHR misses |
| 869system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses 870system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses | 865system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses 866system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses |
| 871system.cpu.dcache.demand_mshr_misses::cpu.data 2756513 # number of demand (read+write) MSHR misses 872system.cpu.dcache.demand_mshr_misses::total 2756513 # number of demand (read+write) MSHR misses 873system.cpu.dcache.overall_mshr_misses::cpu.data 2757155 # number of overall MSHR misses 874system.cpu.dcache.overall_mshr_misses::total 2757155 # number of overall MSHR misses 875system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75218139500 # number of ReadReq MSHR miss cycles 876system.cpu.dcache.ReadReq_mshr_miss_latency::total 75218139500 # number of ReadReq MSHR miss cycles 877system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959023850 # number of WriteReq MSHR miss cycles 878system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959023850 # number of WriteReq MSHR miss cycles 879system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5957500 # number of SoftPFReq MSHR miss cycles 880system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5957500 # number of SoftPFReq MSHR miss cycles 881system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81177163350 # number of demand (read+write) MSHR miss cycles 882system.cpu.dcache.demand_mshr_miss_latency::total 81177163350 # number of demand (read+write) MSHR miss cycles 883system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81183120850 # number of overall MSHR miss cycles 884system.cpu.dcache.overall_mshr_miss_latency::total 81183120850 # number of overall MSHR miss cycles | 867system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses 868system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses 869system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses 870system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses 871system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75180323500 # number of ReadReq MSHR miss cycles 872system.cpu.dcache.ReadReq_mshr_miss_latency::total 75180323500 # number of ReadReq MSHR miss cycles 873system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5949856850 # number of WriteReq MSHR miss cycles 874system.cpu.dcache.WriteReq_mshr_miss_latency::total 5949856850 # number of WriteReq MSHR miss cycles 875system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5764000 # number of SoftPFReq MSHR miss cycles 876system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5764000 # number of SoftPFReq MSHR miss cycles 877system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81130180350 # number of demand (read+write) MSHR miss cycles 878system.cpu.dcache.demand_mshr_miss_latency::total 81130180350 # number of demand (read+write) MSHR miss cycles 879system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81135944350 # number of overall MSHR miss cycles 880system.cpu.dcache.overall_mshr_miss_latency::total 81135944350 # number of overall MSHR miss cycles |
| 885system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses 886system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses | 881system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses 882system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses |
| 887system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses 888system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses | 883system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses 884system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses |
| 889system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses 890system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses 891system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses 892system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses 893system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses 894system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses | 885system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses 886system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses 887system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses 888system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses 889system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses 890system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses |
| 895system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36953.568869 # average ReadReq mshr miss latency 896system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36953.568869 # average ReadReq mshr miss latency 897system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8264.530273 # average WriteReq mshr miss latency 898system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8264.530273 # average WriteReq mshr miss latency 899system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9279.595016 # average SoftPFReq mshr miss latency 900system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9279.595016 # average SoftPFReq mshr miss latency 901system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29449.222024 # average overall mshr miss latency 902system.cpu.dcache.demand_avg_mshr_miss_latency::total 29449.222024 # average overall mshr miss latency 903system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29444.525553 # average overall mshr miss latency 904system.cpu.dcache.overall_avg_mshr_miss_latency::total 29444.525553 # average overall mshr miss latency 905system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 906system.cpu.icache.tags.replacements 1979522 # number of replacements 907system.cpu.icache.tags.tagsinuse 510.550232 # Cycle average of tags in use 908system.cpu.icache.tags.total_refs 245757624 # Total number of references to valid blocks. 909system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. 910system.cpu.icache.tags.avg_refs 124.118006 # Average number of references to valid blocks. 911system.cpu.icache.tags.warmup_cycle 275112500 # Cycle when the warmup percentage was hit. 912system.cpu.icache.tags.occ_blocks::cpu.inst 510.550232 # Average occupied blocks per requestor 913system.cpu.icache.tags.occ_percent::cpu.inst 0.997168 # Average percentage of cache occupancy 914system.cpu.icache.tags.occ_percent::total 0.997168 # Average percentage of cache occupancy | 891system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36934.990422 # average ReadReq mshr miss latency 892system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36934.990422 # average ReadReq mshr miss latency 893system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8251.885289 # average WriteReq mshr miss latency 894system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8251.885289 # average WriteReq mshr miss latency 895system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8978.193146 # average SoftPFReq mshr miss latency 896system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8978.193146 # average SoftPFReq mshr miss latency 897system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29432.241728 # average overall mshr miss latency 898system.cpu.dcache.demand_avg_mshr_miss_latency::total 29432.241728 # average overall mshr miss latency 899system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29427.479019 # average overall mshr miss latency 900system.cpu.dcache.overall_avg_mshr_miss_latency::total 29427.479019 # average overall mshr miss latency 901system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 902system.cpu.icache.tags.replacements 1980154 # number of replacements 903system.cpu.icache.tags.tagsinuse 511.083769 # Cycle average of tags in use 904system.cpu.icache.tags.total_refs 245752724 # Total number of references to valid blocks. 905system.cpu.icache.tags.sampled_refs 1980664 # Sample count of references to valid blocks. 906system.cpu.icache.tags.avg_refs 124.075928 # Average number of references to valid blocks. 907system.cpu.icache.tags.warmup_cycle 275035500 # Cycle when the warmup percentage was hit. 908system.cpu.icache.tags.occ_blocks::cpu.inst 511.083769 # Average occupied blocks per requestor 909system.cpu.icache.tags.occ_percent::cpu.inst 0.998210 # Average percentage of cache occupancy 910system.cpu.icache.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy |
| 915system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 916system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id | 911system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 912system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id |
| 917system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id | 913system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id |
| 918system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id | 914system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id |
| 919system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 920system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id | 915system.cpu.icache.tags.age_task_id_blocks_1024::4 334 # Occupied blocks per task id |
| 921system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id | 916system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id |
| 922system.cpu.icache.tags.tag_accesses 497462038 # Number of tag accesses 923system.cpu.icache.tags.data_accesses 497462038 # Number of data accesses 924system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 925system.cpu.icache.ReadReq_hits::cpu.inst 245757684 # number of ReadReq hits 926system.cpu.icache.ReadReq_hits::total 245757684 # number of ReadReq hits 927system.cpu.icache.demand_hits::cpu.inst 245757684 # number of demand (read+write) hits 928system.cpu.icache.demand_hits::total 245757684 # number of demand (read+write) hits 929system.cpu.icache.overall_hits::cpu.inst 245757684 # number of overall hits 930system.cpu.icache.overall_hits::total 245757684 # number of overall hits 931system.cpu.icache.ReadReq_misses::cpu.inst 1983224 # number of ReadReq misses 932system.cpu.icache.ReadReq_misses::total 1983224 # number of ReadReq misses 933system.cpu.icache.demand_misses::cpu.inst 1983224 # number of demand (read+write) misses 934system.cpu.icache.demand_misses::total 1983224 # number of demand (read+write) misses 935system.cpu.icache.overall_misses::cpu.inst 1983224 # number of overall misses 936system.cpu.icache.overall_misses::total 1983224 # number of overall misses 937system.cpu.icache.ReadReq_miss_latency::cpu.inst 16215368926 # number of ReadReq miss cycles 938system.cpu.icache.ReadReq_miss_latency::total 16215368926 # number of ReadReq miss cycles 939system.cpu.icache.demand_miss_latency::cpu.inst 16215368926 # number of demand (read+write) miss cycles 940system.cpu.icache.demand_miss_latency::total 16215368926 # number of demand (read+write) miss cycles 941system.cpu.icache.overall_miss_latency::cpu.inst 16215368926 # number of overall miss cycles 942system.cpu.icache.overall_miss_latency::total 16215368926 # number of overall miss cycles 943system.cpu.icache.ReadReq_accesses::cpu.inst 247740908 # number of ReadReq accesses(hits+misses) 944system.cpu.icache.ReadReq_accesses::total 247740908 # number of ReadReq accesses(hits+misses) 945system.cpu.icache.demand_accesses::cpu.inst 247740908 # number of demand (read+write) accesses 946system.cpu.icache.demand_accesses::total 247740908 # number of demand (read+write) accesses 947system.cpu.icache.overall_accesses::cpu.inst 247740908 # number of overall (read+write) accesses 948system.cpu.icache.overall_accesses::total 247740908 # number of overall (read+write) accesses 949system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses 950system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses 951system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses 952system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses 953system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses 954system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses 955system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.266991 # average ReadReq miss latency 956system.cpu.icache.ReadReq_avg_miss_latency::total 8176.266991 # average ReadReq miss latency 957system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency 958system.cpu.icache.demand_avg_miss_latency::total 8176.266991 # average overall miss latency 959system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency 960system.cpu.icache.overall_avg_miss_latency::total 8176.266991 # average overall miss latency 961system.cpu.icache.blocked_cycles::no_mshrs 83168 # number of cycles access was blocked 962system.cpu.icache.blocked_cycles::no_targets 761 # number of cycles access was blocked 963system.cpu.icache.blocked::no_mshrs 2904 # number of cycles access was blocked | 917system.cpu.icache.tags.tag_accesses 497454087 # Number of tag accesses 918system.cpu.icache.tags.data_accesses 497454087 # Number of data accesses 919system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 920system.cpu.icache.ReadReq_hits::cpu.inst 245752746 # number of ReadReq hits 921system.cpu.icache.ReadReq_hits::total 245752746 # number of ReadReq hits 922system.cpu.icache.demand_hits::cpu.inst 245752746 # number of demand (read+write) hits 923system.cpu.icache.demand_hits::total 245752746 # number of demand (read+write) hits 924system.cpu.icache.overall_hits::cpu.inst 245752746 # number of overall hits 925system.cpu.icache.overall_hits::total 245752746 # number of overall hits 926system.cpu.icache.ReadReq_misses::cpu.inst 1983875 # number of ReadReq misses 927system.cpu.icache.ReadReq_misses::total 1983875 # number of ReadReq misses 928system.cpu.icache.demand_misses::cpu.inst 1983875 # number of demand (read+write) misses 929system.cpu.icache.demand_misses::total 1983875 # number of demand (read+write) misses 930system.cpu.icache.overall_misses::cpu.inst 1983875 # number of overall misses 931system.cpu.icache.overall_misses::total 1983875 # number of overall misses 932system.cpu.icache.ReadReq_miss_latency::cpu.inst 16221042426 # number of ReadReq miss cycles 933system.cpu.icache.ReadReq_miss_latency::total 16221042426 # number of ReadReq miss cycles 934system.cpu.icache.demand_miss_latency::cpu.inst 16221042426 # number of demand (read+write) miss cycles 935system.cpu.icache.demand_miss_latency::total 16221042426 # number of demand (read+write) miss cycles 936system.cpu.icache.overall_miss_latency::cpu.inst 16221042426 # number of overall miss cycles 937system.cpu.icache.overall_miss_latency::total 16221042426 # number of overall miss cycles 938system.cpu.icache.ReadReq_accesses::cpu.inst 247736621 # number of ReadReq accesses(hits+misses) 939system.cpu.icache.ReadReq_accesses::total 247736621 # number of ReadReq accesses(hits+misses) 940system.cpu.icache.demand_accesses::cpu.inst 247736621 # number of demand (read+write) accesses 941system.cpu.icache.demand_accesses::total 247736621 # number of demand (read+write) accesses 942system.cpu.icache.overall_accesses::cpu.inst 247736621 # number of overall (read+write) accesses 943system.cpu.icache.overall_accesses::total 247736621 # number of overall (read+write) accesses 944system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008008 # miss rate for ReadReq accesses 945system.cpu.icache.ReadReq_miss_rate::total 0.008008 # miss rate for ReadReq accesses 946system.cpu.icache.demand_miss_rate::cpu.inst 0.008008 # miss rate for demand accesses 947system.cpu.icache.demand_miss_rate::total 0.008008 # miss rate for demand accesses 948system.cpu.icache.overall_miss_rate::cpu.inst 0.008008 # miss rate for overall accesses 949system.cpu.icache.overall_miss_rate::total 0.008008 # miss rate for overall accesses 950system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.443791 # average ReadReq miss latency 951system.cpu.icache.ReadReq_avg_miss_latency::total 8176.443791 # average ReadReq miss latency 952system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency 953system.cpu.icache.demand_avg_miss_latency::total 8176.443791 # average overall miss latency 954system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency 955system.cpu.icache.overall_avg_miss_latency::total 8176.443791 # average overall miss latency 956system.cpu.icache.blocked_cycles::no_mshrs 85075 # number of cycles access was blocked 957system.cpu.icache.blocked_cycles::no_targets 747 # number of cycles access was blocked 958system.cpu.icache.blocked::no_mshrs 2929 # number of cycles access was blocked |
| 964system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked | 959system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked |
| 965system.cpu.icache.avg_blocked_cycles::no_mshrs 28.639118 # average number of cycles each access was blocked 966system.cpu.icache.avg_blocked_cycles::no_targets 108.714286 # average number of cycles each access was blocked 967system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks 968system.cpu.icache.writebacks::total 1979522 # number of writebacks 969system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3000 # number of ReadReq MSHR hits 970system.cpu.icache.ReadReq_mshr_hits::total 3000 # number of ReadReq MSHR hits 971system.cpu.icache.demand_mshr_hits::cpu.inst 3000 # number of demand (read+write) MSHR hits 972system.cpu.icache.demand_mshr_hits::total 3000 # number of demand (read+write) MSHR hits 973system.cpu.icache.overall_mshr_hits::cpu.inst 3000 # number of overall MSHR hits 974system.cpu.icache.overall_mshr_hits::total 3000 # number of overall MSHR hits 975system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980224 # number of ReadReq MSHR misses 976system.cpu.icache.ReadReq_mshr_misses::total 1980224 # number of ReadReq MSHR misses 977system.cpu.icache.demand_mshr_misses::cpu.inst 1980224 # number of demand (read+write) MSHR misses 978system.cpu.icache.demand_mshr_misses::total 1980224 # number of demand (read+write) MSHR misses 979system.cpu.icache.overall_mshr_misses::cpu.inst 1980224 # number of overall MSHR misses 980system.cpu.icache.overall_mshr_misses::total 1980224 # number of overall MSHR misses 981system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15180539440 # number of ReadReq MSHR miss cycles 982system.cpu.icache.ReadReq_mshr_miss_latency::total 15180539440 # number of ReadReq MSHR miss cycles 983system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15180539440 # number of demand (read+write) MSHR miss cycles 984system.cpu.icache.demand_mshr_miss_latency::total 15180539440 # number of demand (read+write) MSHR miss cycles 985system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15180539440 # number of overall MSHR miss cycles 986system.cpu.icache.overall_mshr_miss_latency::total 15180539440 # number of overall MSHR miss cycles 987system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses 988system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses 989system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses 990system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses 991system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses 992system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses 993system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.071838 # average ReadReq mshr miss latency 994system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.071838 # average ReadReq mshr miss latency 995system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency 996system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency 997system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency 998system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency 999system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 1000system.cpu.l2cache.prefetcher.num_hwpf_issued 1350153 # number of hwpf issued 1001system.cpu.l2cache.prefetcher.pfIdentified 1355017 # number of prefetch candidates identified 1002system.cpu.l2cache.prefetcher.pfBufferHit 4256 # number of redundant prefetches already in prefetch queue | 960system.cpu.icache.avg_blocked_cycles::no_mshrs 29.045749 # average number of cycles each access was blocked 961system.cpu.icache.avg_blocked_cycles::no_targets 106.714286 # average number of cycles each access was blocked 962system.cpu.icache.writebacks::writebacks 1980154 # number of writebacks 963system.cpu.icache.writebacks::total 1980154 # number of writebacks 964system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3028 # number of ReadReq MSHR hits 965system.cpu.icache.ReadReq_mshr_hits::total 3028 # number of ReadReq MSHR hits 966system.cpu.icache.demand_mshr_hits::cpu.inst 3028 # number of demand (read+write) MSHR hits 967system.cpu.icache.demand_mshr_hits::total 3028 # number of demand (read+write) MSHR hits 968system.cpu.icache.overall_mshr_hits::cpu.inst 3028 # number of overall MSHR hits 969system.cpu.icache.overall_mshr_hits::total 3028 # number of overall MSHR hits 970system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980847 # number of ReadReq MSHR misses 971system.cpu.icache.ReadReq_mshr_misses::total 1980847 # number of ReadReq MSHR misses 972system.cpu.icache.demand_mshr_misses::cpu.inst 1980847 # number of demand (read+write) MSHR misses 973system.cpu.icache.demand_mshr_misses::total 1980847 # number of demand (read+write) MSHR misses 974system.cpu.icache.overall_mshr_misses::cpu.inst 1980847 # number of overall MSHR misses 975system.cpu.icache.overall_mshr_misses::total 1980847 # number of overall MSHR misses 976system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15183658439 # number of ReadReq MSHR miss cycles 977system.cpu.icache.ReadReq_mshr_miss_latency::total 15183658439 # number of ReadReq MSHR miss cycles 978system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15183658439 # number of demand (read+write) MSHR miss cycles 979system.cpu.icache.demand_mshr_miss_latency::total 15183658439 # number of demand (read+write) MSHR miss cycles 980system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15183658439 # number of overall MSHR miss cycles 981system.cpu.icache.overall_mshr_miss_latency::total 15183658439 # number of overall MSHR miss cycles 982system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for ReadReq accesses 983system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007996 # mshr miss rate for ReadReq accesses 984system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for demand accesses 985system.cpu.icache.demand_mshr_miss_rate::total 0.007996 # mshr miss rate for demand accesses 986system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for overall accesses 987system.cpu.icache.overall_mshr_miss_rate::total 0.007996 # mshr miss rate for overall accesses 988system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7665.235346 # average ReadReq mshr miss latency 989system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7665.235346 # average ReadReq mshr miss latency 990system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency 991system.cpu.icache.demand_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency 992system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency 993system.cpu.icache.overall_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency 994system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 995system.cpu.l2cache.prefetcher.num_hwpf_issued 1350785 # number of hwpf issued 996system.cpu.l2cache.prefetcher.pfIdentified 1355219 # number of prefetch candidates identified 997system.cpu.l2cache.prefetcher.pfBufferHit 3879 # number of redundant prefetches already in prefetch queue |
| 1003system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1004system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 998system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 999system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1005system.cpu.l2cache.prefetcher.pfSpanPage 4789879 # number of prefetches not generated due to page crossing 1006system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 1007system.cpu.l2cache.tags.replacements 297323 # number of replacements 1008system.cpu.l2cache.tags.tagsinuse 16097.800949 # Cycle average of tags in use 1009system.cpu.l2cache.tags.total_refs 3937547 # Total number of references to valid blocks. 1010system.cpu.l2cache.tags.sampled_refs 313525 # Sample count of references to valid blocks. 1011system.cpu.l2cache.tags.avg_refs 12.558957 # Average number of references to valid blocks. | 1000system.cpu.l2cache.prefetcher.pfSpanPage 4789973 # number of prefetches not generated due to page crossing 1001system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 1002system.cpu.l2cache.tags.replacements 297120 # number of replacements 1003system.cpu.l2cache.tags.tagsinuse 16096.917401 # Cycle average of tags in use 1004system.cpu.l2cache.tags.total_refs 3841839 # Total number of references to valid blocks. 1005system.cpu.l2cache.tags.sampled_refs 313315 # Sample count of references to valid blocks. 1006system.cpu.l2cache.tags.avg_refs 12.261906 # Average number of references to valid blocks. |
| 1012system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1007system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1013system.cpu.l2cache.tags.occ_blocks::writebacks 15677.943381 # Average occupied blocks per requestor 1014system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 419.857568 # Average occupied blocks per requestor 1015system.cpu.l2cache.tags.occ_percent::writebacks 0.956906 # Average percentage of cache occupancy 1016system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025626 # Average percentage of cache occupancy 1017system.cpu.l2cache.tags.occ_percent::total 0.982532 # Average percentage of cache occupancy 1018system.cpu.l2cache.tags.occ_task_id_blocks::1022 424 # Occupied blocks per task id 1019system.cpu.l2cache.tags.occ_task_id_blocks::1024 15778 # Occupied blocks per task id | 1008system.cpu.l2cache.tags.occ_blocks::writebacks 15676.222250 # Average occupied blocks per requestor 1009system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.695151 # Average occupied blocks per requestor 1010system.cpu.l2cache.tags.occ_percent::writebacks 0.956801 # Average percentage of cache occupancy 1011system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025677 # Average percentage of cache occupancy 1012system.cpu.l2cache.tags.occ_percent::total 0.982478 # Average percentage of cache occupancy 1013system.cpu.l2cache.tags.occ_task_id_blocks::1022 430 # Occupied blocks per task id 1014system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id |
| 1020system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id | 1015system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id |
| 1021system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id 1022system.cpu.l2cache.tags.age_task_id_blocks_1022::3 273 # Occupied blocks per task id 1023system.cpu.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id | 1016system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id 1017system.cpu.l2cache.tags.age_task_id_blocks_1022::3 263 # Occupied blocks per task id 1018system.cpu.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id |
| 1024system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id | 1019system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id |
| 1025system.cpu.l2cache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id 1026system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id 1027system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3670 # Occupied blocks per task id 1028system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10056 # Occupied blocks per task id 1029system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025879 # Percentage of cache occupancy per task id 1030system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963013 # Percentage of cache occupancy per task id 1031system.cpu.l2cache.tags.tag_accesses 145579085 # Number of tag accesses 1032system.cpu.l2cache.tags.data_accesses 145579085 # Number of data accesses 1033system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 1034system.cpu.l2cache.WritebackDirty_hits::writebacks 735952 # number of WritebackDirty hits 1035system.cpu.l2cache.WritebackDirty_hits::total 735952 # number of WritebackDirty hits 1036system.cpu.l2cache.WritebackClean_hits::writebacks 3357075 # number of WritebackClean hits 1037system.cpu.l2cache.WritebackClean_hits::total 3357075 # number of WritebackClean hits 1038system.cpu.l2cache.ReadExReq_hits::cpu.data 718660 # number of ReadExReq hits 1039system.cpu.l2cache.ReadExReq_hits::total 718660 # number of ReadExReq hits 1040system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975820 # number of ReadCleanReq hits 1041system.cpu.l2cache.ReadCleanReq_hits::total 1975820 # number of ReadCleanReq hits 1042system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1285803 # number of ReadSharedReq hits 1043system.cpu.l2cache.ReadSharedReq_hits::total 1285803 # number of ReadSharedReq hits 1044system.cpu.l2cache.demand_hits::cpu.inst 1975820 # number of demand (read+write) hits 1045system.cpu.l2cache.demand_hits::cpu.data 2004463 # number of demand (read+write) hits 1046system.cpu.l2cache.demand_hits::total 3980283 # number of demand (read+write) hits 1047system.cpu.l2cache.overall_hits::cpu.inst 1975820 # number of overall hits 1048system.cpu.l2cache.overall_hits::cpu.data 2004463 # number of overall hits 1049system.cpu.l2cache.overall_hits::total 3980283 # number of overall hits 1050system.cpu.l2cache.UpgradeReq_misses::cpu.data 190 # number of UpgradeReq misses 1051system.cpu.l2cache.UpgradeReq_misses::total 190 # number of UpgradeReq misses 1052system.cpu.l2cache.ReadExReq_misses::cpu.data 2186 # number of ReadExReq misses 1053system.cpu.l2cache.ReadExReq_misses::total 2186 # number of ReadExReq misses 1054system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4215 # number of ReadCleanReq misses 1055system.cpu.l2cache.ReadCleanReq_misses::total 4215 # number of ReadCleanReq misses 1056system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750316 # number of ReadSharedReq misses 1057system.cpu.l2cache.ReadSharedReq_misses::total 750316 # number of ReadSharedReq misses 1058system.cpu.l2cache.demand_misses::cpu.inst 4215 # number of demand (read+write) misses 1059system.cpu.l2cache.demand_misses::cpu.data 752502 # number of demand (read+write) misses 1060system.cpu.l2cache.demand_misses::total 756717 # number of demand (read+write) misses 1061system.cpu.l2cache.overall_misses::cpu.inst 4215 # number of overall misses 1062system.cpu.l2cache.overall_misses::cpu.data 752502 # number of overall misses 1063system.cpu.l2cache.overall_misses::total 756717 # number of overall misses 1064system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 197785000 # number of ReadExReq miss cycles 1065system.cpu.l2cache.ReadExReq_miss_latency::total 197785000 # number of ReadExReq miss cycles 1066system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351484000 # number of ReadCleanReq miss cycles 1067system.cpu.l2cache.ReadCleanReq_miss_latency::total 351484000 # number of ReadCleanReq miss cycles 1068system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63803558500 # number of ReadSharedReq miss cycles 1069system.cpu.l2cache.ReadSharedReq_miss_latency::total 63803558500 # number of ReadSharedReq miss cycles 1070system.cpu.l2cache.demand_miss_latency::cpu.inst 351484000 # number of demand (read+write) miss cycles 1071system.cpu.l2cache.demand_miss_latency::cpu.data 64001343500 # number of demand (read+write) miss cycles 1072system.cpu.l2cache.demand_miss_latency::total 64352827500 # number of demand (read+write) miss cycles 1073system.cpu.l2cache.overall_miss_latency::cpu.inst 351484000 # number of overall miss cycles 1074system.cpu.l2cache.overall_miss_latency::cpu.data 64001343500 # number of overall miss cycles 1075system.cpu.l2cache.overall_miss_latency::total 64352827500 # number of overall miss cycles 1076system.cpu.l2cache.WritebackDirty_accesses::writebacks 735952 # number of WritebackDirty accesses(hits+misses) 1077system.cpu.l2cache.WritebackDirty_accesses::total 735952 # number of WritebackDirty accesses(hits+misses) 1078system.cpu.l2cache.WritebackClean_accesses::writebacks 3357075 # number of WritebackClean accesses(hits+misses) 1079system.cpu.l2cache.WritebackClean_accesses::total 3357075 # number of WritebackClean accesses(hits+misses) 1080system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190 # number of UpgradeReq accesses(hits+misses) 1081system.cpu.l2cache.UpgradeReq_accesses::total 190 # number of UpgradeReq accesses(hits+misses) 1082system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) 1083system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) 1084system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980035 # number of ReadCleanReq accesses(hits+misses) 1085system.cpu.l2cache.ReadCleanReq_accesses::total 1980035 # number of ReadCleanReq accesses(hits+misses) | 1020system.cpu.l2cache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id 1021system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id 1022system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3686 # Occupied blocks per task id 1023system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10031 # Occupied blocks per task id 1024system.cpu.l2cache.tags.occ_task_id_percent::1022 0.026245 # Percentage of cache occupancy per task id 1025system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id 1026system.cpu.l2cache.tags.tag_accesses 145605931 # Number of tag accesses 1027system.cpu.l2cache.tags.data_accesses 145605931 # Number of data accesses 1028system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 1029system.cpu.l2cache.WritebackDirty_hits::writebacks 735798 # number of WritebackDirty hits 1030system.cpu.l2cache.WritebackDirty_hits::total 735798 # number of WritebackDirty hits 1031system.cpu.l2cache.WritebackClean_hits::writebacks 3358223 # number of WritebackClean hits 1032system.cpu.l2cache.WritebackClean_hits::total 3358223 # number of WritebackClean hits 1033system.cpu.l2cache.ReadExReq_hits::cpu.data 718689 # number of ReadExReq hits 1034system.cpu.l2cache.ReadExReq_hits::total 718689 # number of ReadExReq hits 1035system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976463 # number of ReadCleanReq hits 1036system.cpu.l2cache.ReadCleanReq_hits::total 1976463 # number of ReadCleanReq hits 1037system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286254 # number of ReadSharedReq hits 1038system.cpu.l2cache.ReadSharedReq_hits::total 1286254 # number of ReadSharedReq hits 1039system.cpu.l2cache.demand_hits::cpu.inst 1976463 # number of demand (read+write) hits 1040system.cpu.l2cache.demand_hits::cpu.data 2004943 # number of demand (read+write) hits 1041system.cpu.l2cache.demand_hits::total 3981406 # number of demand (read+write) hits 1042system.cpu.l2cache.overall_hits::cpu.inst 1976463 # number of overall hits 1043system.cpu.l2cache.overall_hits::cpu.data 2004943 # number of overall hits 1044system.cpu.l2cache.overall_hits::total 3981406 # number of overall hits 1045system.cpu.l2cache.UpgradeReq_misses::cpu.data 181 # number of UpgradeReq misses 1046system.cpu.l2cache.UpgradeReq_misses::total 181 # number of UpgradeReq misses 1047system.cpu.l2cache.ReadExReq_misses::cpu.data 2160 # number of ReadExReq misses 1048system.cpu.l2cache.ReadExReq_misses::total 2160 # number of ReadExReq misses 1049system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4204 # number of ReadCleanReq misses 1050system.cpu.l2cache.ReadCleanReq_misses::total 4204 # number of ReadCleanReq misses 1051system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749865 # number of ReadSharedReq misses 1052system.cpu.l2cache.ReadSharedReq_misses::total 749865 # number of ReadSharedReq misses 1053system.cpu.l2cache.demand_misses::cpu.inst 4204 # number of demand (read+write) misses 1054system.cpu.l2cache.demand_misses::cpu.data 752025 # number of demand (read+write) misses 1055system.cpu.l2cache.demand_misses::total 756229 # number of demand (read+write) misses 1056system.cpu.l2cache.overall_misses::cpu.inst 4204 # number of overall misses 1057system.cpu.l2cache.overall_misses::cpu.data 752025 # number of overall misses 1058system.cpu.l2cache.overall_misses::total 756229 # number of overall misses 1059system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 187813000 # number of ReadExReq miss cycles 1060system.cpu.l2cache.ReadExReq_miss_latency::total 187813000 # number of ReadExReq miss cycles 1061system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 349759500 # number of ReadCleanReq miss cycles 1062system.cpu.l2cache.ReadCleanReq_miss_latency::total 349759500 # number of ReadCleanReq miss cycles 1063system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63761970000 # number of ReadSharedReq miss cycles 1064system.cpu.l2cache.ReadSharedReq_miss_latency::total 63761970000 # number of ReadSharedReq miss cycles 1065system.cpu.l2cache.demand_miss_latency::cpu.inst 349759500 # number of demand (read+write) miss cycles 1066system.cpu.l2cache.demand_miss_latency::cpu.data 63949783000 # number of demand (read+write) miss cycles 1067system.cpu.l2cache.demand_miss_latency::total 64299542500 # number of demand (read+write) miss cycles 1068system.cpu.l2cache.overall_miss_latency::cpu.inst 349759500 # number of overall miss cycles 1069system.cpu.l2cache.overall_miss_latency::cpu.data 63949783000 # number of overall miss cycles 1070system.cpu.l2cache.overall_miss_latency::total 64299542500 # number of overall miss cycles 1071system.cpu.l2cache.WritebackDirty_accesses::writebacks 735798 # number of WritebackDirty accesses(hits+misses) 1072system.cpu.l2cache.WritebackDirty_accesses::total 735798 # number of WritebackDirty accesses(hits+misses) 1073system.cpu.l2cache.WritebackClean_accesses::writebacks 3358223 # number of WritebackClean accesses(hits+misses) 1074system.cpu.l2cache.WritebackClean_accesses::total 3358223 # number of WritebackClean accesses(hits+misses) 1075system.cpu.l2cache.UpgradeReq_accesses::cpu.data 181 # number of UpgradeReq accesses(hits+misses) 1076system.cpu.l2cache.UpgradeReq_accesses::total 181 # number of UpgradeReq accesses(hits+misses) 1077system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses) 1078system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses) 1079system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980667 # number of ReadCleanReq accesses(hits+misses) 1080system.cpu.l2cache.ReadCleanReq_accesses::total 1980667 # number of ReadCleanReq accesses(hits+misses) |
| 1086system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses) 1087system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses) | 1081system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses) 1082system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses) |
| 1088system.cpu.l2cache.demand_accesses::cpu.inst 1980035 # number of demand (read+write) accesses 1089system.cpu.l2cache.demand_accesses::cpu.data 2756965 # number of demand (read+write) accesses 1090system.cpu.l2cache.demand_accesses::total 4737000 # number of demand (read+write) accesses 1091system.cpu.l2cache.overall_accesses::cpu.inst 1980035 # number of overall (read+write) accesses 1092system.cpu.l2cache.overall_accesses::cpu.data 2756965 # number of overall (read+write) accesses 1093system.cpu.l2cache.overall_accesses::total 4737000 # number of overall (read+write) accesses | 1083system.cpu.l2cache.demand_accesses::cpu.inst 1980667 # number of demand (read+write) accesses 1084system.cpu.l2cache.demand_accesses::cpu.data 2756968 # number of demand (read+write) accesses 1085system.cpu.l2cache.demand_accesses::total 4737635 # number of demand (read+write) accesses 1086system.cpu.l2cache.overall_accesses::cpu.inst 1980667 # number of overall (read+write) accesses 1087system.cpu.l2cache.overall_accesses::cpu.data 2756968 # number of overall (read+write) accesses 1088system.cpu.l2cache.overall_accesses::total 4737635 # number of overall (read+write) accesses |
| 1094system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1095system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 1089system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1090system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1096system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003033 # miss rate for ReadExReq accesses 1097system.cpu.l2cache.ReadExReq_miss_rate::total 0.003033 # miss rate for ReadExReq accesses 1098system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002129 # miss rate for ReadCleanReq accesses 1099system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002129 # miss rate for ReadCleanReq accesses 1100system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368503 # miss rate for ReadSharedReq accesses 1101system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368503 # miss rate for ReadSharedReq accesses 1102system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002129 # miss rate for demand accesses 1103system.cpu.l2cache.demand_miss_rate::cpu.data 0.272946 # miss rate for demand accesses 1104system.cpu.l2cache.demand_miss_rate::total 0.159746 # miss rate for demand accesses 1105system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002129 # miss rate for overall accesses 1106system.cpu.l2cache.overall_miss_rate::cpu.data 0.272946 # miss rate for overall accesses 1107system.cpu.l2cache.overall_miss_rate::total 0.159746 # miss rate for overall accesses 1108system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90478.042086 # average ReadExReq miss latency 1109system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90478.042086 # average ReadExReq miss latency 1110system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83388.849348 # average ReadCleanReq miss latency 1111system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83388.849348 # average ReadCleanReq miss latency 1112system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85035.583008 # average ReadSharedReq miss latency 1113system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85035.583008 # average ReadSharedReq miss latency 1114system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency 1115system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency 1116system.cpu.l2cache.demand_avg_miss_latency::total 85042.132660 # average overall miss latency 1117system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency 1118system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency 1119system.cpu.l2cache.overall_avg_miss_latency::total 85042.132660 # average overall miss latency | 1091system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002996 # miss rate for ReadExReq accesses 1092system.cpu.l2cache.ReadExReq_miss_rate::total 0.002996 # miss rate for ReadExReq accesses 1093system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002123 # miss rate for ReadCleanReq accesses 1094system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002123 # miss rate for ReadCleanReq accesses 1095system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368282 # miss rate for ReadSharedReq accesses 1096system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368282 # miss rate for ReadSharedReq accesses 1097system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002123 # miss rate for demand accesses 1098system.cpu.l2cache.demand_miss_rate::cpu.data 0.272772 # miss rate for demand accesses 1099system.cpu.l2cache.demand_miss_rate::total 0.159622 # miss rate for demand accesses 1100system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002123 # miss rate for overall accesses 1101system.cpu.l2cache.overall_miss_rate::cpu.data 0.272772 # miss rate for overall accesses 1102system.cpu.l2cache.overall_miss_rate::total 0.159622 # miss rate for overall accesses 1103system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86950.462963 # average ReadExReq miss latency 1104system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86950.462963 # average ReadExReq miss latency 1105system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83196.836346 # average ReadCleanReq miss latency 1106system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83196.836346 # average ReadCleanReq miss latency 1107system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85031.265628 # average ReadSharedReq miss latency 1108system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85031.265628 # average ReadSharedReq miss latency 1109system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency 1110system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency 1111system.cpu.l2cache.demand_avg_miss_latency::total 85026.549498 # average overall miss latency 1112system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency 1113system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency 1114system.cpu.l2cache.overall_avg_miss_latency::total 85026.549498 # average overall miss latency |
| 1120system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1121system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1122system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1123system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1124system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1125system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1115system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1116system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1117system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1118system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1119system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1120system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1126system.cpu.l2cache.unused_prefetches 3567 # number of HardPF blocks evicted w/o reference 1127system.cpu.l2cache.writebacks::writebacks 66339 # number of writebacks 1128system.cpu.l2cache.writebacks::total 66339 # number of writebacks 1129system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 799 # number of ReadExReq MSHR hits 1130system.cpu.l2cache.ReadExReq_mshr_hits::total 799 # number of ReadExReq MSHR hits | 1121system.cpu.l2cache.unused_prefetches 3549 # number of HardPF blocks evicted w/o reference 1122system.cpu.l2cache.writebacks::writebacks 66317 # number of writebacks 1123system.cpu.l2cache.writebacks::total 66317 # number of writebacks 1124system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 785 # number of ReadExReq MSHR hits 1125system.cpu.l2cache.ReadExReq_mshr_hits::total 785 # number of ReadExReq MSHR hits |
| 1131system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1132system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits | 1126system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1127system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits |
| 1133system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1026 # number of ReadSharedReq MSHR hits 1134system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1026 # number of ReadSharedReq MSHR hits | 1128system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1052 # number of ReadSharedReq MSHR hits 1129system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1052 # number of ReadSharedReq MSHR hits |
| 1135system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits | 1130system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits |
| 1136system.cpu.l2cache.demand_mshr_hits::cpu.data 1825 # number of demand (read+write) MSHR hits 1137system.cpu.l2cache.demand_mshr_hits::total 1826 # number of demand (read+write) MSHR hits | 1131system.cpu.l2cache.demand_mshr_hits::cpu.data 1837 # number of demand (read+write) MSHR hits 1132system.cpu.l2cache.demand_mshr_hits::total 1838 # number of demand (read+write) MSHR hits |
| 1138system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits | 1133system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits |
| 1139system.cpu.l2cache.overall_mshr_hits::cpu.data 1825 # number of overall MSHR hits 1140system.cpu.l2cache.overall_mshr_hits::total 1826 # number of overall MSHR hits 1141system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202675 # number of HardPFReq MSHR misses 1142system.cpu.l2cache.HardPFReq_mshr_misses::total 202675 # number of HardPFReq MSHR misses 1143system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 190 # number of UpgradeReq MSHR misses 1144system.cpu.l2cache.UpgradeReq_mshr_misses::total 190 # number of UpgradeReq MSHR misses 1145system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses 1146system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses 1147system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4214 # number of ReadCleanReq MSHR misses 1148system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4214 # number of ReadCleanReq MSHR misses 1149system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 749290 # number of ReadSharedReq MSHR misses 1150system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749290 # number of ReadSharedReq MSHR misses 1151system.cpu.l2cache.demand_mshr_misses::cpu.inst 4214 # number of demand (read+write) MSHR misses 1152system.cpu.l2cache.demand_mshr_misses::cpu.data 750677 # number of demand (read+write) MSHR misses 1153system.cpu.l2cache.demand_mshr_misses::total 754891 # number of demand (read+write) MSHR misses 1154system.cpu.l2cache.overall_mshr_misses::cpu.inst 4214 # number of overall MSHR misses 1155system.cpu.l2cache.overall_mshr_misses::cpu.data 750677 # number of overall MSHR misses 1156system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202675 # number of overall MSHR misses 1157system.cpu.l2cache.overall_mshr_misses::total 957566 # number of overall MSHR misses 1158system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of HardPFReq MSHR miss cycles 1159system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20310287954 # number of HardPFReq MSHR miss cycles 1160system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2871000 # number of UpgradeReq MSHR miss cycles 1161system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2871000 # number of UpgradeReq MSHR miss cycles 1162system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 146425000 # number of ReadExReq MSHR miss cycles 1163system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 146425000 # number of ReadExReq MSHR miss cycles 1164system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 326144500 # number of ReadCleanReq MSHR miss cycles 1165system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 326144500 # number of ReadCleanReq MSHR miss cycles 1166system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59240775500 # number of ReadSharedReq MSHR miss cycles 1167system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59240775500 # number of ReadSharedReq MSHR miss cycles 1168system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 326144500 # number of demand (read+write) MSHR miss cycles 1169system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59387200500 # number of demand (read+write) MSHR miss cycles 1170system.cpu.l2cache.demand_mshr_miss_latency::total 59713345000 # number of demand (read+write) MSHR miss cycles 1171system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 326144500 # number of overall MSHR miss cycles 1172system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59387200500 # number of overall MSHR miss cycles 1173system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of overall MSHR miss cycles 1174system.cpu.l2cache.overall_mshr_miss_latency::total 80023632954 # number of overall MSHR miss cycles | 1134system.cpu.l2cache.overall_mshr_hits::cpu.data 1837 # number of overall MSHR hits 1135system.cpu.l2cache.overall_mshr_hits::total 1838 # number of overall MSHR hits 1136system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202613 # number of HardPFReq MSHR misses 1137system.cpu.l2cache.HardPFReq_mshr_misses::total 202613 # number of HardPFReq MSHR misses 1138system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 181 # number of UpgradeReq MSHR misses 1139system.cpu.l2cache.UpgradeReq_mshr_misses::total 181 # number of UpgradeReq MSHR misses 1140system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1375 # number of ReadExReq MSHR misses 1141system.cpu.l2cache.ReadExReq_mshr_misses::total 1375 # number of ReadExReq MSHR misses 1142system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4203 # number of ReadCleanReq MSHR misses 1143system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4203 # number of ReadCleanReq MSHR misses 1144system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748813 # number of ReadSharedReq MSHR misses 1145system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748813 # number of ReadSharedReq MSHR misses 1146system.cpu.l2cache.demand_mshr_misses::cpu.inst 4203 # number of demand (read+write) MSHR misses 1147system.cpu.l2cache.demand_mshr_misses::cpu.data 750188 # number of demand (read+write) MSHR misses 1148system.cpu.l2cache.demand_mshr_misses::total 754391 # number of demand (read+write) MSHR misses 1149system.cpu.l2cache.overall_mshr_misses::cpu.inst 4203 # number of overall MSHR misses 1150system.cpu.l2cache.overall_mshr_misses::cpu.data 750188 # number of overall MSHR misses 1151system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202613 # number of overall MSHR misses 1152system.cpu.l2cache.overall_mshr_misses::total 957004 # number of overall MSHR misses 1153system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of HardPFReq MSHR miss cycles 1154system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20275662144 # number of HardPFReq MSHR miss cycles 1155system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2881000 # number of UpgradeReq MSHR miss cycles 1156system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2881000 # number of UpgradeReq MSHR miss cycles 1157system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 136635500 # number of ReadExReq MSHR miss cycles 1158system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 136635500 # number of ReadExReq MSHR miss cycles 1159system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 324486000 # number of ReadCleanReq MSHR miss cycles 1160system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 324486000 # number of ReadCleanReq MSHR miss cycles 1161system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59198284500 # number of ReadSharedReq MSHR miss cycles 1162system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59198284500 # number of ReadSharedReq MSHR miss cycles 1163system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 324486000 # number of demand (read+write) MSHR miss cycles 1164system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59334920000 # number of demand (read+write) MSHR miss cycles 1165system.cpu.l2cache.demand_mshr_miss_latency::total 59659406000 # number of demand (read+write) MSHR miss cycles 1166system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 324486000 # number of overall MSHR miss cycles 1167system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59334920000 # number of overall MSHR miss cycles 1168system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of overall MSHR miss cycles 1169system.cpu.l2cache.overall_mshr_miss_latency::total 79935068144 # number of overall MSHR miss cycles |
| 1175system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1176system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1177system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1178system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 1170system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1171system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1172system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1173system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1179system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses 1180system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses 1181system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for ReadCleanReq accesses 1182system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002128 # mshr miss rate for ReadCleanReq accesses 1183system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367999 # mshr miss rate for ReadSharedReq accesses 1184system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367999 # mshr miss rate for ReadSharedReq accesses 1185system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for demand accesses 1186system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for demand accesses 1187system.cpu.l2cache.demand_mshr_miss_rate::total 0.159361 # mshr miss rate for demand accesses 1188system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for overall accesses 1189system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for overall accesses | 1174system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadExReq accesses 1175system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadExReq accesses 1176system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for ReadCleanReq accesses 1177system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002122 # mshr miss rate for ReadCleanReq accesses 1178system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367765 # mshr miss rate for ReadSharedReq accesses 1179system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367765 # mshr miss rate for ReadSharedReq accesses 1180system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for demand accesses 1181system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for demand accesses 1182system.cpu.l2cache.demand_mshr_miss_rate::total 0.159234 # mshr miss rate for demand accesses 1183system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for overall accesses 1184system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for overall accesses |
| 1190system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1185system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1191system.cpu.l2cache.overall_mshr_miss_rate::total 0.202146 # mshr miss rate for overall accesses 1192system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average HardPFReq mshr miss latency 1193system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100211.116092 # average HardPFReq mshr miss latency 1194system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15110.526316 # average UpgradeReq mshr miss latency 1195system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15110.526316 # average UpgradeReq mshr miss latency 1196system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 105569.574621 # average ReadExReq mshr miss latency 1197system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 105569.574621 # average ReadExReq mshr miss latency 1198system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77395.467489 # average ReadCleanReq mshr miss latency 1199system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77395.467489 # average ReadCleanReq mshr miss latency 1200system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79062.546544 # average ReadSharedReq mshr miss latency 1201system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79062.546544 # average ReadSharedReq mshr miss latency 1202system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency 1203system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency 1204system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79101.943194 # average overall mshr miss latency 1205system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency 1206system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency 1207system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average overall mshr miss latency 1208system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83569.835347 # average overall mshr miss latency 1209system.cpu.toL2Bus.snoop_filter.tot_requests 9473354 # Total number of requests made to the snoop filter. 1210system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736191 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1211system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1212system.cpu.toL2Bus.snoop_filter.tot_snoops 89 # Total number of snoops made to the snoop filter. 1213system.cpu.toL2Bus.snoop_filter.hit_single_snoops 88 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1186system.cpu.l2cache.overall_mshr_miss_rate::total 0.202000 # mshr miss rate for overall accesses 1187system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average HardPFReq mshr miss latency 1188system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100070.884613 # average HardPFReq mshr miss latency 1189system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15917.127072 # average UpgradeReq mshr miss latency 1190system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15917.127072 # average UpgradeReq mshr miss latency 1191system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99371.272727 # average ReadExReq mshr miss latency 1192system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99371.272727 # average ReadExReq mshr miss latency 1193system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77203.426124 # average ReadCleanReq mshr miss latency 1194system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77203.426124 # average ReadCleanReq mshr miss latency 1195system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79056.165558 # average ReadSharedReq mshr miss latency 1196system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79056.165558 # average ReadSharedReq mshr miss latency 1197system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency 1198system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency 1199system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79082.870819 # average overall mshr miss latency 1200system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency 1201system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency 1202system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average overall mshr miss latency 1203system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83526.367856 # average overall mshr miss latency 1204system.cpu.toL2Bus.snoop_filter.tot_requests 9474606 # Total number of requests made to the snoop filter. 1205system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736642 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1206system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1207system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. 1208system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1214system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1209system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1215system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 1216system.cpu.toL2Bus.trans_dist::ReadResp 4016341 # Transaction distribution 1217system.cpu.toL2Bus.trans_dist::WritebackDirty 802291 # Transaction distribution 1218system.cpu.toL2Bus.trans_dist::WritebackClean 4000023 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::CleanEvict 230984 # Transaction distribution 1220system.cpu.toL2Bus.trans_dist::HardPFReq 255300 # Transaction distribution 1221system.cpu.toL2Bus.trans_dist::UpgradeReq 190 # Transaction distribution 1222system.cpu.toL2Bus.trans_dist::UpgradeResp 190 # Transaction distribution 1223system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution 1224system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution 1225system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980224 # Transaction distribution | 1210system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 1211system.cpu.toL2Bus.trans_dist::ReadResp 4016964 # Transaction distribution 1212system.cpu.toL2Bus.trans_dist::WritebackDirty 802115 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::WritebackClean 4000812 # Transaction distribution 1214system.cpu.toL2Bus.trans_dist::CleanEvict 230803 # Transaction distribution 1215system.cpu.toL2Bus.trans_dist::HardPFReq 255056 # Transaction distribution 1216system.cpu.toL2Bus.trans_dist::UpgradeReq 181 # Transaction distribution 1217system.cpu.toL2Bus.trans_dist::UpgradeResp 181 # Transaction distribution 1218system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution 1220system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980847 # Transaction distribution |
| 1226system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution | 1221system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution |
| 1227system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939779 # Packet count per connected master and slave (bytes) 1228system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270763 # Packet count per connected master and slave (bytes) 1229system.cpu.toL2Bus.pkt_count::total 14210542 # Packet count per connected master and slave (bytes) 1230system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) 1231system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858752 # Cumulative packet size per connected master and slave (bytes) 1232system.cpu.toL2Bus.pkt_size::total 606270272 # Cumulative packet size per connected master and slave (bytes) 1233system.cpu.toL2Bus.snoops 552812 # Total snoops (count) 1234system.cpu.toL2Bus.snoopTraffic 4257792 # Total snoop traffic (bytes) 1235system.cpu.toL2Bus.snoop_fanout::samples 5290002 # Request fanout histogram 1236system.cpu.toL2Bus.snoop_fanout::mean 0.121634 # Request fanout histogram 1237system.cpu.toL2Bus.snoop_fanout::stdev 0.326863 # Request fanout histogram | 1222system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5941666 # Packet count per connected master and slave (bytes) 1223system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270754 # Packet count per connected master and slave (bytes) 1224system.cpu.toL2Bus.pkt_count::total 14212420 # Packet count per connected master and slave (bytes) 1225system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253492416 # Cumulative packet size per connected master and slave (bytes) 1226system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859136 # Cumulative packet size per connected master and slave (bytes) 1227system.cpu.toL2Bus.pkt_size::total 606351552 # Cumulative packet size per connected master and slave (bytes) 1228system.cpu.toL2Bus.snoops 552356 # Total snoops (count) 1229system.cpu.toL2Bus.snoopTraffic 4255808 # Total snoop traffic (bytes) 1230system.cpu.toL2Bus.snoop_fanout::samples 5290172 # Request fanout histogram 1231system.cpu.toL2Bus.snoop_fanout::mean 0.121625 # Request fanout histogram 1232system.cpu.toL2Bus.snoop_fanout::stdev 0.326853 # Request fanout histogram |
| 1238system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1233system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1239system.cpu.toL2Bus.snoop_fanout::0 4646559 87.84% 87.84% # Request fanout histogram 1240system.cpu.toL2Bus.snoop_fanout::1 643442 12.16% 100.00% # Request fanout histogram | 1234system.cpu.toL2Bus.snoop_fanout::0 4646755 87.84% 87.84% # Request fanout histogram 1235system.cpu.toL2Bus.snoop_fanout::1 643416 12.16% 100.00% # Request fanout histogram |
| 1241system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1242system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1243system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1244system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1236system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1237system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1238system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1239system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1245system.cpu.toL2Bus.snoop_fanout::total 5290002 # Request fanout histogram 1246system.cpu.toL2Bus.reqLayer0.occupancy 9472652000 # Layer occupancy (ticks) | 1240system.cpu.toL2Bus.snoop_fanout::total 5290172 # Request fanout histogram 1241system.cpu.toL2Bus.reqLayer0.occupancy 9473913000 # Layer occupancy (ticks) |
| 1247system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) | 1242system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) |
| 1248system.cpu.toL2Bus.respLayer0.occupancy 2970335495 # Layer occupancy (ticks) | 1243system.cpu.toL2Bus.respLayer0.occupancy 2971268997 # Layer occupancy (ticks) |
| 1249system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) | 1244system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) |
| 1250system.cpu.toL2Bus.respLayer1.occupancy 4135554975 # Layer occupancy (ticks) | 1245system.cpu.toL2Bus.respLayer1.occupancy 4135554476 # Layer occupancy (ticks) |
| 1251system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) | 1246system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) |
| 1252system.membus.snoop_filter.tot_requests 1254990 # Total number of requests made to the snoop filter. 1253system.membus.snoop_filter.hit_single_requests 940467 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1247system.membus.snoop_filter.tot_requests 1254210 # Total number of requests made to the snoop filter. 1248system.membus.snoop_filter.hit_single_requests 939897 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1254system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1255system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1256system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1257system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1249system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1250system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1251system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1252system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1258system.membus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 1259system.membus.trans_dist::ReadResp 956088 # Transaction distribution 1260system.membus.trans_dist::WritebackDirty 66339 # Transaction distribution 1261system.membus.trans_dist::CleanEvict 230984 # Transaction distribution 1262system.membus.trans_dist::UpgradeReq 190 # Transaction distribution 1263system.membus.trans_dist::ReadExReq 1387 # Transaction distribution 1264system.membus.trans_dist::ReadExResp 1387 # Transaction distribution 1265system.membus.trans_dist::ReadSharedReq 956090 # Transaction distribution 1266system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2212465 # Packet count per connected master and slave (bytes) 1267system.membus.pkt_count::total 2212465 # Packet count per connected master and slave (bytes) 1268system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65524096 # Cumulative packet size per connected master and slave (bytes) 1269system.membus.pkt_size::total 65524096 # Cumulative packet size per connected master and slave (bytes) | 1253system.membus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states 1254system.membus.trans_dist::ReadResp 955532 # Transaction distribution 1255system.membus.trans_dist::WritebackDirty 66317 # Transaction distribution 1256system.membus.trans_dist::CleanEvict 230803 # Transaction distribution 1257system.membus.trans_dist::UpgradeReq 181 # Transaction distribution 1258system.membus.trans_dist::ReadExReq 1375 # Transaction distribution 1259system.membus.trans_dist::ReadExResp 1375 # Transaction distribution 1260system.membus.trans_dist::ReadSharedReq 955534 # Transaction distribution 1261system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211117 # Packet count per connected master and slave (bytes) 1262system.membus.pkt_count::total 2211117 # Packet count per connected master and slave (bytes) 1263system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65486336 # Cumulative packet size per connected master and slave (bytes) 1264system.membus.pkt_size::total 65486336 # Cumulative packet size per connected master and slave (bytes) |
| 1270system.membus.snoops 0 # Total snoops (count) 1271system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1265system.membus.snoops 0 # Total snoops (count) 1266system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1272system.membus.snoop_fanout::samples 957667 # Request fanout histogram | 1267system.membus.snoop_fanout::samples 957090 # Request fanout histogram |
| 1273system.membus.snoop_fanout::mean 0 # Request fanout histogram 1274system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1275system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1268system.membus.snoop_fanout::mean 0 # Request fanout histogram 1269system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1270system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1276system.membus.snoop_fanout::0 957667 100.00% 100.00% # Request fanout histogram | 1271system.membus.snoop_fanout::0 957090 100.00% 100.00% # Request fanout histogram |
| 1277system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1278system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1279system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1280system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1272system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1273system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1274system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1275system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1281system.membus.snoop_fanout::total 957667 # Request fanout histogram 1282system.membus.reqLayer0.occupancy 1758860478 # Layer occupancy (ticks) | 1276system.membus.snoop_fanout::total 957090 # Request fanout histogram 1277system.membus.reqLayer0.occupancy 1757256327 # Layer occupancy (ticks) |
| 1283system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) | 1278system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) |
| 1284system.membus.respLayer1.occupancy 5031633569 # Layer occupancy (ticks) | 1279system.membus.respLayer1.occupancy 5028523066 # Layer occupancy (ticks) |
| 1285system.membus.respLayer1.utilization 1.5 # Layer utilization (%) 1286 1287---------- End Simulation Statistics ---------- | 1280system.membus.respLayer1.utilization 1.5 # Layer utilization (%) 1281 1282---------- End Simulation Statistics ---------- |