| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.327896 # Number of seconds simulated 4sim_ticks 327895638000 # Number of ticks simulated 5final_tick 327895638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.339013 # Number of seconds simulated 4sim_ticks 339012932000 # Number of ticks simulated 5final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 125299 # Simulator instruction rate (inst/s) 8host_op_rate 154259 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 64130088 # Simulator tick rate (ticks/s) 10host_mem_usage 277300 # Number of bytes of host memory used 11host_seconds 5112.98 # Real time elapsed on the host | 7host_inst_rate 140345 # Simulator instruction rate (inst/s) 8host_op_rate 172783 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 74266222 # Simulator tick rate (ticks/s) 10host_mem_usage 275384 # Number of bytes of host memory used 11host_seconds 4564.83 # Real time elapsed on the host |
| 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 266368 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 48003200 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 12980224 # Number of bytes read from this memory 20system.physmem.bytes_read::total 61249792 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 266368 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 266368 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 4244096 # Number of bytes written to this memory 24system.physmem.bytes_written::total 4244096 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 4162 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 750050 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 202816 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 957028 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 66314 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 66314 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 812356 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 146397800 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 39586449 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 186796605 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 812356 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 812356 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 12943435 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 12943435 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 12943435 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 812356 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 146397800 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 39586449 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 199740040 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 957029 # Number of read requests accepted 45system.physmem.writeReqs 66314 # Number of write requests accepted 46system.physmem.readBursts 957029 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 66314 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 61231232 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue 50system.physmem.bytesWritten 4237440 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 61249856 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 4244096 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 72 # Number of DRAM write bursts merged with an existing one | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 269632 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 48043328 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 12965504 # Number of bytes read from this memory 20system.physmem.bytes_read::total 61278464 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 269632 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 269632 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 4245696 # Number of bytes written to this memory 24system.physmem.bytes_written::total 4245696 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 4213 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 750677 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 202586 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 957476 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 66339 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 66339 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 795344 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 141715325 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 38244866 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 180755535 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 795344 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 795344 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 12523699 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 12523699 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 12523699 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 795344 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 141715325 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 38244866 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 193279235 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 957477 # Number of read requests accepted 45system.physmem.writeReqs 66339 # Number of write requests accepted 46system.physmem.readBursts 957477 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 66339 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 61258752 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 19776 # Total number of bytes read from write queue 50system.physmem.bytesWritten 4240576 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 61278528 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 4245696 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 309 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 54 # Number of DRAM write bursts merged with an existing one |
| 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 19913 # Per bank write bursts 57system.physmem.perBankRdBursts::1 19609 # Per bank write bursts 58system.physmem.perBankRdBursts::2 657177 # Per bank write bursts 59system.physmem.perBankRdBursts::3 20974 # Per bank write bursts 60system.physmem.perBankRdBursts::4 19738 # Per bank write bursts 61system.physmem.perBankRdBursts::5 20841 # Per bank write bursts 62system.physmem.perBankRdBursts::6 19544 # Per bank write bursts 63system.physmem.perBankRdBursts::7 20056 # Per bank write bursts 64system.physmem.perBankRdBursts::8 19527 # Per bank write bursts 65system.physmem.perBankRdBursts::9 20071 # Per bank write bursts 66system.physmem.perBankRdBursts::10 19467 # Per bank write bursts 67system.physmem.perBankRdBursts::11 19786 # Per bank write bursts 68system.physmem.perBankRdBursts::12 19618 # Per bank write bursts 69system.physmem.perBankRdBursts::13 21115 # Per bank write bursts 70system.physmem.perBankRdBursts::14 19501 # Per bank write bursts 71system.physmem.perBankRdBursts::15 19801 # Per bank write bursts 72system.physmem.perBankWrBursts::0 4241 # Per bank write bursts 73system.physmem.perBankWrBursts::1 4104 # Per bank write bursts 74system.physmem.perBankWrBursts::2 4141 # Per bank write bursts 75system.physmem.perBankWrBursts::3 4151 # Per bank write bursts 76system.physmem.perBankWrBursts::4 4245 # Per bank write bursts 77system.physmem.perBankWrBursts::5 4233 # Per bank write bursts 78system.physmem.perBankWrBursts::6 4174 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 19910 # Per bank write bursts 57system.physmem.perBankRdBursts::1 19533 # Per bank write bursts 58system.physmem.perBankRdBursts::2 657271 # Per bank write bursts 59system.physmem.perBankRdBursts::3 20982 # Per bank write bursts 60system.physmem.perBankRdBursts::4 19710 # Per bank write bursts 61system.physmem.perBankRdBursts::5 21143 # Per bank write bursts 62system.physmem.perBankRdBursts::6 19634 # Per bank write bursts 63system.physmem.perBankRdBursts::7 20055 # Per bank write bursts 64system.physmem.perBankRdBursts::8 19495 # Per bank write bursts 65system.physmem.perBankRdBursts::9 20079 # Per bank write bursts 66system.physmem.perBankRdBursts::10 19428 # Per bank write bursts 67system.physmem.perBankRdBursts::11 19728 # Per bank write bursts 68system.physmem.perBankRdBursts::12 19649 # Per bank write bursts 69system.physmem.perBankRdBursts::13 21208 # Per bank write bursts 70system.physmem.perBankRdBursts::14 19490 # Per bank write bursts 71system.physmem.perBankRdBursts::15 19853 # Per bank write bursts 72system.physmem.perBankWrBursts::0 4286 # Per bank write bursts 73system.physmem.perBankWrBursts::1 4105 # Per bank write bursts 74system.physmem.perBankWrBursts::2 4145 # Per bank write bursts 75system.physmem.perBankWrBursts::3 4153 # Per bank write bursts 76system.physmem.perBankWrBursts::4 4249 # Per bank write bursts 77system.physmem.perBankWrBursts::5 4230 # Per bank write bursts 78system.physmem.perBankWrBursts::6 4173 # Per bank write bursts |
| 79system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::8 4096 # Per bank write bursts | 79system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::8 4096 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::9 4095 # Per bank write bursts 82system.physmem.perBankWrBursts::10 4096 # Per bank write bursts | 81system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::10 4094 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 84system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 85system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 86system.physmem.perBankWrBursts::14 4096 # Per bank write bursts | 83system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 84system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 85system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 86system.physmem.perBankWrBursts::14 4096 # Per bank write bursts |
| 87system.physmem.perBankWrBursts::15 4151 # Per bank write bursts | 87system.physmem.perBankWrBursts::15 4149 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 90system.physmem.totGap 327895627500 # Total gap between requests | 90system.physmem.totGap 339012921500 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 957029 # Read request sizes (log2) | 97system.physmem.readPktSize::6 957477 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 66314 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 765529 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 120932 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 14410 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 6427 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 7705 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 8957 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 9890 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 6812 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 3724 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 2470 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 1588 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1057 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 621 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 66339 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 764538 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 120546 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 15621 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 6697 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 6433 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 7720 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 9109 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 10145 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 6841 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 3643 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 2525 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 1571 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1107 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see --- 17 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see --- 17 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 852 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 1419 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 2097 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 2585 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 3077 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 3558 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 4078 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 4529 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 5085 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 5480 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 5966 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6331 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 5957 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 4447 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 4147 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 4057 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 137 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 98 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 96 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 82 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 68 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 45 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 38 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 25 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 20 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 18 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 15 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 2 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 537 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 883 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 1456 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 2089 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 2622 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 3068 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 3545 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 4065 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 4483 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 4939 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 5348 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 5856 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6147 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 4797 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 4234 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 4114 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 131 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 91 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 74 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 66 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 67 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 62 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 52 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 41 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 43 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 28 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 16 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 13 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 7 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see |
| 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 201system.physmem.bytesPerActivate::samples 194181 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 337.148207 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 191.280987 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 364.158297 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 64676 33.31% 33.31% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 60636 31.23% 64.53% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 15729 8.10% 72.63% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3217 1.66% 74.29% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 3574 1.84% 76.13% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2317 1.19% 77.32% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 2364 1.22% 78.54% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 21831 11.24% 89.78% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 19837 10.22% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 194181 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 3990 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 177.226065 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::gmean 34.842577 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::stdev 1813.556545 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::0-4095 3969 99.47% 99.47% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.70% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::8192-12287 4 0.10% 99.80% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::12288-16383 2 0.05% 99.85% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.87% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.90% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::28672-32767 2 0.05% 99.95% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.97% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::86016-90111 1 0.03% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::total 3990 # Reads before turning the bus around for writes 229system.physmem.wrPerTurnAround::samples 3990 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::mean 16.593985 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::gmean 16.513577 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::stdev 1.886226 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::16 3332 83.51% 83.51% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::17 5 0.13% 83.63% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::18 452 11.33% 94.96% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::19 50 1.25% 96.22% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20 19 0.48% 96.69% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::21 17 0.43% 97.12% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::22 10 0.25% 97.37% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::23 19 0.48% 97.84% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::24 12 0.30% 98.15% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::25 15 0.38% 98.52% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::26 16 0.40% 98.92% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::27 15 0.38% 99.30% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::28 9 0.23% 99.52% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::29 5 0.13% 99.65% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::30 4 0.10% 99.75% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::31 3 0.08% 99.82% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::32 1 0.03% 99.85% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::33 1 0.03% 99.87% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::34 3 0.08% 99.95% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::35 1 0.03% 99.97% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::37 1 0.03% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::total 3990 # Writes before turning the bus around for reads 255system.physmem.totQLat 12587538724 # Total ticks spent queuing 256system.physmem.totMemAccLat 30526376224 # Total ticks spent from burst creation until serviced by the DRAM 257system.physmem.totBusLat 4783690000 # Total ticks spent in databus transfers 258system.physmem.avgQLat 13156.72 # Average queueing delay per DRAM burst | 201system.physmem.bytesPerActivate::samples 195212 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 335.517735 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 192.597798 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 355.506182 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 64341 32.96% 32.96% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 60661 31.07% 64.03% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 15753 8.07% 72.10% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3211 1.64% 73.75% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 3578 1.83% 75.58% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2458 1.26% 76.84% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 2478 1.27% 78.11% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 34211 17.53% 95.64% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 8521 4.36% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 195212 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 3994 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 204.692539 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::gmean 35.349556 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::stdev 2360.542955 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::0-4095 3971 99.42% 99.42% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::4096-8191 10 0.25% 99.67% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::8192-12287 5 0.13% 99.80% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::12288-16383 1 0.03% 99.82% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.85% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.87% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::28672-32767 1 0.03% 99.90% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.92% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.95% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::69632-73727 1 0.03% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::98304-102399 1 0.03% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 3994 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 3994 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 16.589634 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 16.506417 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 1.926291 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16 3368 84.33% 84.33% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::17 17 0.43% 84.75% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::18 396 9.91% 94.67% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::19 46 1.15% 95.82% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20 24 0.60% 96.42% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::21 17 0.43% 96.85% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::22 21 0.53% 97.37% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::23 18 0.45% 97.82% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::24 15 0.38% 98.20% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::25 17 0.43% 98.62% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::26 13 0.33% 98.95% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::27 10 0.25% 99.20% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::28 7 0.18% 99.37% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::29 8 0.20% 99.57% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::30 8 0.20% 99.77% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::32 4 0.10% 99.87% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::33 1 0.03% 99.90% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::34 1 0.03% 99.92% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::35 1 0.03% 99.95% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::37 1 0.03% 99.97% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::39 1 0.03% 100.00% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::total 3994 # Writes before turning the bus around for reads 257system.physmem.totQLat 27473404757 # Total ticks spent queuing 258system.physmem.totMemAccLat 45420304757 # Total ticks spent from burst creation until serviced by the DRAM 259system.physmem.totBusLat 4785840000 # Total ticks spent in databus transfers 260system.physmem.avgQLat 28702.80 # Average queueing delay per DRAM burst |
| 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 261system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 260system.physmem.avgMemAccLat 31906.72 # Average memory access latency per DRAM burst 261system.physmem.avgRdBW 186.74 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 12.92 # Average achieved write bandwidth in MiByte/s 263system.physmem.avgRdBWSys 186.80 # Average system read bandwidth in MiByte/s 264system.physmem.avgWrBWSys 12.94 # Average system write bandwidth in MiByte/s | 262system.physmem.avgMemAccLat 47452.80 # Average memory access latency per DRAM burst 263system.physmem.avgRdBW 180.70 # Average DRAM read bandwidth in MiByte/s 264system.physmem.avgWrBW 12.51 # Average achieved write bandwidth in MiByte/s 265system.physmem.avgRdBWSys 180.76 # Average system read bandwidth in MiByte/s 266system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s |
| 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 267system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 266system.physmem.busUtil 1.56 # Data bus utilization in percentage 267system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads | 268system.physmem.busUtil 1.51 # Data bus utilization in percentage 269system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads |
| 268system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes 269system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing | 270system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes 271system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing |
| 270system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing 271system.physmem.readRowHits 805843 # Number of row buffer hits during reads 272system.physmem.writeRowHits 22921 # Number of row buffer hits during writes 273system.physmem.readRowHitRate 84.23 # Row buffer hit rate for reads 274system.physmem.writeRowHitRate 34.60 # Row buffer hit rate for writes 275system.physmem.avgGap 320416.15 # Average gap between requests 276system.physmem.pageHitRate 81.01 # Row buffer hit rate, read and write combined 277system.physmem_0.actEnergy 934317720 # Energy for activate commands per rank (pJ) 278system.physmem_0.preEnergy 509796375 # Energy for precharge commands per rank (pJ) 279system.physmem_0.readEnergy 6223237800 # Energy for read commands per rank (pJ) 280system.physmem_0.writeEnergy 216334800 # Energy for write commands per rank (pJ) 281system.physmem_0.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) 282system.physmem_0.actBackEnergy 220944760020 # Energy for active background per rank (pJ) 283system.physmem_0.preBackEnergy 2925699000 # Energy for precharge background per rank (pJ) 284system.physmem_0.totalEnergy 253170624435 # Total energy per rank (pJ) 285system.physmem_0.averagePower 772.109253 # Core power per rank (mW) 286system.physmem_0.memoryStateTime::IDLE 3595093339 # Time in different power states 287system.physmem_0.memoryStateTime::REF 10949120000 # Time in different power states 288system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 289system.physmem_0.memoryStateTime::ACT 313351421161 # Time in different power states 290system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 291system.physmem_1.actEnergy 533690640 # Energy for activate commands per rank (pJ) 292system.physmem_1.preEnergy 291200250 # Energy for precharge commands per rank (pJ) 293system.physmem_1.readEnergy 1239209400 # Energy for read commands per rank (pJ) 294system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) 295system.physmem_1.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) 296system.physmem_1.actBackEnergy 88116969465 # Energy for active background per rank (pJ) 297system.physmem_1.preBackEnergy 119441319000 # Energy for precharge background per rank (pJ) 298system.physmem_1.totalEnergy 231251573475 # Total energy per rank (pJ) 299system.physmem_1.averagePower 705.261391 # Core power per rank (mW) 300system.physmem_1.memoryStateTime::IDLE 198129163855 # Time in different power states 301system.physmem_1.memoryStateTime::REF 10949120000 # Time in different power states 302system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 303system.physmem_1.memoryStateTime::ACT 118816573145 # Time in different power states 304system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 305system.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 306system.cpu.branchPred.lookups 174659739 # Number of BP lookups 307system.cpu.branchPred.condPredicted 119113225 # Number of conditional branches predicted 308system.cpu.branchPred.condIncorrect 4015668 # Number of conditional branches incorrect 309system.cpu.branchPred.BTBLookups 96720974 # Number of BTB lookups 310system.cpu.branchPred.BTBHits 67755362 # Number of BTB hits | 272system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing 273system.physmem.readRowHits 805066 # Number of row buffer hits during reads 274system.physmem.writeRowHits 23137 # Number of row buffer hits during writes 275system.physmem.readRowHitRate 84.11 # Row buffer hit rate for reads 276system.physmem.writeRowHitRate 34.91 # Row buffer hit rate for writes 277system.physmem.avgGap 331126.81 # Average gap between requests 278system.physmem.pageHitRate 80.92 # Row buffer hit rate, read and write combined 279system.physmem_0.actEnergy 894020820 # Energy for activate commands per rank (pJ) 280system.physmem_0.preEnergy 475164360 # Energy for precharge commands per rank (pJ) 281system.physmem_0.readEnergy 5699412180 # Energy for read commands per rank (pJ) 282system.physmem_0.writeEnergy 174541140 # Energy for write commands per rank (pJ) 283system.physmem_0.refreshEnergy 27331811520.000008 # Energy for refresh commands per rank (pJ) 284system.physmem_0.actBackEnergy 14462317590 # Energy for active background per rank (pJ) 285system.physmem_0.preBackEnergy 674820000 # Energy for precharge background per rank (pJ) 286system.physmem_0.actPowerDownEnergy 138340924320 # Energy for active power-down per rank (pJ) 287system.physmem_0.prePowerDownEnergy 704060640 # Energy for precharge power-down per rank (pJ) 288system.physmem_0.selfRefreshEnergy 673701120.000000 # Energy for self refresh per rank (pJ) 289system.physmem_0.totalEnergy 189477322380 # Total energy per rank (pJ) 290system.physmem_0.averagePower 558.908824 # Core power per rank (mW) 291system.physmem_0.totalIdleTime 305437641889 # Total Idle time Per DRAM Rank 292system.physmem_0.memoryStateTime::IDLE 528629764 # Time in different power states 293system.physmem_0.memoryStateTime::REF 11569144000 # Time in different power states 294system.physmem_0.memoryStateTime::SREF 223118500 # Time in different power states 295system.physmem_0.memoryStateTime::PRE_PDN 1833570381 # Time in different power states 296system.physmem_0.memoryStateTime::ACT 21477516347 # Time in different power states 297system.physmem_0.memoryStateTime::ACT_PDN 303380953008 # Time in different power states 298system.physmem_1.actEnergy 499878540 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 265665180 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 1134760200 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 171330840 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 25420895760.000004 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 7011060990 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 1362065280 # Energy for precharge background per rank (pJ) 305system.physmem_1.actPowerDownEnergy 70491607590 # Energy for active power-down per rank (pJ) 306system.physmem_1.prePowerDownEnergy 31027049280 # Energy for precharge power-down per rank (pJ) 307system.physmem_1.selfRefreshEnergy 25487678070 # Energy for self refresh per rank (pJ) 308system.physmem_1.totalEnergy 162872491950 # Total energy per rank (pJ) 309system.physmem_1.averagePower 480.431501 # Core power per rank (mW) 310system.physmem_1.totalIdleTime 320089357075 # Total Idle time Per DRAM Rank 311system.physmem_1.memoryStateTime::IDLE 2604072271 # Time in different power states 312system.physmem_1.memoryStateTime::REF 10809446000 # Time in different power states 313system.physmem_1.memoryStateTime::SREF 84703185250 # Time in different power states 314system.physmem_1.memoryStateTime::PRE_PDN 80799625521 # Time in different power states 315system.physmem_1.memoryStateTime::ACT 5510033904 # Time in different power states 316system.physmem_1.memoryStateTime::ACT_PDN 154586569054 # Time in different power states 317system.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 318system.cpu.branchPred.lookups 174656775 # Number of BP lookups 319system.cpu.branchPred.condPredicted 119110803 # Number of conditional branches predicted 320system.cpu.branchPred.condIncorrect 4015685 # Number of conditional branches incorrect 321system.cpu.branchPred.BTBLookups 96721345 # Number of BTB lookups 322system.cpu.branchPred.BTBHits 67754534 # Number of BTB hits |
| 311system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 323system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 312system.cpu.branchPred.BTBHitPct 70.052398 # BTB Hit Percentage 313system.cpu.branchPred.usedRAS 18785155 # Number of times the RAS was used to get a target. 314system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. 315system.cpu.branchPred.indirectLookups 16716286 # Number of indirect predictor lookups. 316system.cpu.branchPred.indirectHits 16701799 # Number of indirect target hits. 317system.cpu.branchPred.indirectMisses 14487 # Number of indirect misses. 318system.cpu.branchPredindirectMispredicted 1279501 # Number of mispredicted indirect branches. | 324system.cpu.branchPred.BTBHitPct 70.051274 # BTB Hit Percentage 325system.cpu.branchPred.usedRAS 18785121 # Number of times the RAS was used to get a target. 326system.cpu.branchPred.RASInCorrect 1299599 # Number of incorrect RAS predictions. 327system.cpu.branchPred.indirectLookups 16716580 # Number of indirect predictor lookups. 328system.cpu.branchPred.indirectHits 16702336 # Number of indirect target hits. 329system.cpu.branchPred.indirectMisses 14244 # Number of indirect misses. 330system.cpu.branchPredindirectMispredicted 1279516 # Number of mispredicted indirect branches. |
| 319system.cpu_clk_domain.clock 500 # Clock period in ticks | 331system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 320system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states | 332system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states |
| 321system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 326system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 327system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 328system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 342system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 343system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 344system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 345system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 346system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 347system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 348system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 349system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 333system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 334system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 337system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 354system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 355system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 356system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 357system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 358system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 359system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 360system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 361system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 350system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states | 362system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states |
| 351system.cpu.dtb.walker.walks 0 # Table walker walks requested 352system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 353system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 354system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 355system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 358system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 372system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 373system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 374system.cpu.dtb.read_accesses 0 # DTB read accesses 375system.cpu.dtb.write_accesses 0 # DTB write accesses 376system.cpu.dtb.inst_accesses 0 # ITB inst accesses 377system.cpu.dtb.hits 0 # DTB hits 378system.cpu.dtb.misses 0 # DTB misses 379system.cpu.dtb.accesses 0 # DTB accesses | 363system.cpu.dtb.walker.walks 0 # Table walker walks requested 364system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 367system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 368system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 370system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 384system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 385system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 386system.cpu.dtb.read_accesses 0 # DTB read accesses 387system.cpu.dtb.write_accesses 0 # DTB write accesses 388system.cpu.dtb.inst_accesses 0 # ITB inst accesses 389system.cpu.dtb.hits 0 # DTB hits 390system.cpu.dtb.misses 0 # DTB misses 391system.cpu.dtb.accesses 0 # DTB accesses |
| 380system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states | 392system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states |
| 381system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 382system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 383system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 384system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 385system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 386system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 388system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 402system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 403system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 404system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 405system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 406system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 407system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 408system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 409system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 393system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 394system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 395system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 397system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 398system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 400system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 414system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 415system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 416system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 417system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 418system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 419system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 420system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 421system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 410system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states | 422system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states |
| 411system.cpu.itb.walker.walks 0 # Table walker walks requested 412system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 413system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 414system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 415system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 416system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 417system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 418system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 433system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 434system.cpu.itb.read_accesses 0 # DTB read accesses 435system.cpu.itb.write_accesses 0 # DTB write accesses 436system.cpu.itb.inst_accesses 0 # ITB inst accesses 437system.cpu.itb.hits 0 # DTB hits 438system.cpu.itb.misses 0 # DTB misses 439system.cpu.itb.accesses 0 # DTB accesses 440system.cpu.workload.num_syscalls 673 # Number of system calls | 423system.cpu.itb.walker.walks 0 # Table walker walks requested 424system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 425system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 426system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 427system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 428system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 429system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 430system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 445system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 446system.cpu.itb.read_accesses 0 # DTB read accesses 447system.cpu.itb.write_accesses 0 # DTB write accesses 448system.cpu.itb.inst_accesses 0 # ITB inst accesses 449system.cpu.itb.hits 0 # DTB hits 450system.cpu.itb.misses 0 # DTB misses 451system.cpu.itb.accesses 0 # DTB accesses 452system.cpu.workload.num_syscalls 673 # Number of system calls |
| 441system.cpu.pwrStateResidencyTicks::ON 327895638000 # Cumulative time (in ticks) in various power states 442system.cpu.numCycles 655791277 # number of cpu cycles simulated | 453system.cpu.pwrStateResidencyTicks::ON 339012932000 # Cumulative time (in ticks) in various power states 454system.cpu.numCycles 678025865 # number of cpu cycles simulated |
| 443system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 444system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 455system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 456system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 445system.cpu.fetch.icacheStallCycles 34353189 # Number of cycles fetch is stalled on an Icache miss 446system.cpu.fetch.Insts 824276690 # Number of instructions fetch has processed 447system.cpu.fetch.Branches 174659739 # Number of branches that fetch encountered 448system.cpu.fetch.predictedBranches 103242316 # Number of branches that fetch has predicted taken 449system.cpu.fetch.Cycles 616975428 # Number of cycles fetch has run and was not squashing or blocked 450system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing 451system.cpu.fetch.MiscStallCycles 2182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 457system.cpu.fetch.icacheStallCycles 34354212 # Number of cycles fetch is stalled on an Icache miss 458system.cpu.fetch.Insts 824273790 # Number of instructions fetch has processed 459system.cpu.fetch.Branches 174656775 # Number of branches that fetch encountered 460system.cpu.fetch.predictedBranches 103241991 # Number of branches that fetch has predicted taken 461system.cpu.fetch.Cycles 639159762 # Number of cycles fetch has run and was not squashing or blocked 462system.cpu.fetch.SquashCycles 8068079 # Number of cycles fetch has spent squashing 463system.cpu.fetch.MiscStallCycles 2457 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 452system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps | 464system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps |
| 453system.cpu.fetch.IcacheWaitRetryStallCycles 3170 # Number of stall cycles due to full MSHR 454system.cpu.fetch.CacheLines 247740649 # Number of cache lines fetched 455system.cpu.fetch.IcacheSquashes 12515 # Number of outstanding Icache misses that were squashed 456system.cpu.fetch.rateDist::samples 655368010 # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.rateDist::mean 1.551156 # Number of instructions fetched each cycle (Total) 458system.cpu.fetch.rateDist::stdev 1.253828 # Number of instructions fetched each cycle (Total) | 465system.cpu.fetch.IcacheWaitRetryStallCycles 3206 # Number of stall cycles due to full MSHR 466system.cpu.fetch.CacheLines 247740942 # Number of cache lines fetched 467system.cpu.fetch.IcacheSquashes 12520 # Number of outstanding Icache misses that were squashed 468system.cpu.fetch.rateDist::samples 677553693 # Number of instructions fetched each cycle (Total) 469system.cpu.fetch.rateDist::mean 1.500365 # Number of instructions fetched each cycle (Total) 470system.cpu.fetch.rateDist::stdev 1.263651 # Number of instructions fetched each cycle (Total) |
| 459system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 471system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 460system.cpu.fetch.rateDist::0 193301276 29.50% 29.50% # Number of instructions fetched each cycle (Total) 461system.cpu.fetch.rateDist::1 148337850 22.63% 52.13% # Number of instructions fetched each cycle (Total) 462system.cpu.fetch.rateDist::2 72946568 11.13% 63.26% # Number of instructions fetched each cycle (Total) 463system.cpu.fetch.rateDist::3 240782316 36.74% 100.00% # Number of instructions fetched each cycle (Total) | 472system.cpu.fetch.rateDist::0 215486043 31.80% 31.80% # Number of instructions fetched each cycle (Total) 473system.cpu.fetch.rateDist::1 148340760 21.89% 53.70% # Number of instructions fetched each cycle (Total) 474system.cpu.fetch.rateDist::2 72943473 10.77% 64.46% # Number of instructions fetched each cycle (Total) 475system.cpu.fetch.rateDist::3 240783417 35.54% 100.00% # Number of instructions fetched each cycle (Total) |
| 464system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 465system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 466system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 476system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 477system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 478system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 467system.cpu.fetch.rateDist::total 655368010 # Number of instructions fetched each cycle (Total) 468system.cpu.fetch.branchRate 0.266334 # Number of branch fetches per cycle 469system.cpu.fetch.rate 1.256919 # Number of inst fetches per cycle 470system.cpu.decode.IdleCycles 75112130 # Number of cycles decode is idle 471system.cpu.decode.BlockedCycles 236493276 # Number of cycles decode is blocked 472system.cpu.decode.RunCycles 277761287 # Number of cycles decode is running 473system.cpu.decode.UnblockCycles 61980307 # Number of cycles decode is unblocking 474system.cpu.decode.SquashCycles 4021010 # Number of cycles decode is squashing 475system.cpu.decode.BranchResolved 20809608 # Number of times decode resolved a branch 476system.cpu.decode.BranchMispred 13112 # Number of times decode detected a branch misprediction 477system.cpu.decode.DecodedInsts 924575224 # Number of instructions handled by decode 478system.cpu.decode.SquashedInsts 11804312 # Number of squashed instructions handled by decode 479system.cpu.rename.SquashCycles 4021010 # Number of cycles rename is squashing 480system.cpu.rename.IdleCycles 118055519 # Number of cycles rename is idle 481system.cpu.rename.BlockCycles 135785787 # Number of cycles rename is blocking 482system.cpu.rename.serializeStallCycles 212608 # count of cycles rename stalled for serializing inst 483system.cpu.rename.RunCycles 294557237 # Number of cycles rename is running 484system.cpu.rename.UnblockCycles 102735849 # Number of cycles rename is unblocking 485system.cpu.rename.RenamedInsts 906541412 # Number of instructions processed by rename 486system.cpu.rename.SquashedInsts 6891100 # Number of squashed instructions processed by rename 487system.cpu.rename.ROBFullEvents 27959034 # Number of times rename has blocked due to ROB full 488system.cpu.rename.IQFullEvents 2218150 # Number of times rename has blocked due to IQ full 489system.cpu.rename.LQFullEvents 49337765 # Number of times rename has blocked due to LQ full 490system.cpu.rename.SQFullEvents 468731 # Number of times rename has blocked due to SQ full 491system.cpu.rename.RenamedOperands 980926815 # Number of destination operands rename has renamed 492system.cpu.rename.RenameLookups 4318009248 # Number of register rename lookups that rename has made 493system.cpu.rename.int_rename_lookups 1001835221 # Number of integer rename lookups 494system.cpu.rename.fp_rename_lookups 34457086 # Number of floating rename lookups | 479system.cpu.fetch.rateDist::total 677553693 # Number of instructions fetched each cycle (Total) 480system.cpu.fetch.branchRate 0.257596 # Number of branch fetches per cycle 481system.cpu.fetch.rate 1.215697 # Number of inst fetches per cycle 482system.cpu.decode.IdleCycles 75112537 # Number of cycles decode is idle 483system.cpu.decode.BlockedCycles 258679606 # Number of cycles decode is blocked 484system.cpu.decode.RunCycles 277758053 # Number of cycles decode is running 485system.cpu.decode.UnblockCycles 61982472 # Number of cycles decode is unblocking 486system.cpu.decode.SquashCycles 4021025 # Number of cycles decode is squashing 487system.cpu.decode.BranchResolved 20810112 # Number of times decode resolved a branch 488system.cpu.decode.BranchMispred 13117 # Number of times decode detected a branch misprediction 489system.cpu.decode.DecodedInsts 924576668 # Number of instructions handled by decode 490system.cpu.decode.SquashedInsts 11804380 # Number of squashed instructions handled by decode 491system.cpu.rename.SquashCycles 4021025 # Number of cycles rename is squashing 492system.cpu.rename.IdleCycles 118056358 # Number of cycles rename is idle 493system.cpu.rename.BlockCycles 157938220 # Number of cycles rename is blocking 494system.cpu.rename.serializeStallCycles 213059 # count of cycles rename stalled for serializing inst 495system.cpu.rename.RunCycles 294555904 # Number of cycles rename is running 496system.cpu.rename.UnblockCycles 102769127 # Number of cycles rename is unblocking 497system.cpu.rename.RenamedInsts 906541450 # Number of instructions processed by rename 498system.cpu.rename.SquashedInsts 6890856 # Number of squashed instructions processed by rename 499system.cpu.rename.ROBFullEvents 27990855 # Number of times rename has blocked due to ROB full 500system.cpu.rename.IQFullEvents 2220094 # Number of times rename has blocked due to IQ full 501system.cpu.rename.LQFullEvents 49338949 # Number of times rename has blocked due to LQ full 502system.cpu.rename.SQFullEvents 500517 # Number of times rename has blocked due to SQ full 503system.cpu.rename.RenamedOperands 980921468 # Number of destination operands rename has renamed 504system.cpu.rename.RenameLookups 4318014727 # Number of register rename lookups that rename has made 505system.cpu.rename.int_rename_lookups 1001837715 # Number of integer rename lookups 506system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups |
| 495system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed | 507system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed |
| 496system.cpu.rename.UndoneMaps 106148585 # Number of HB maps that are undone due to squashing 497system.cpu.rename.serializingInsts 6844 # count of serializing insts renamed 498system.cpu.rename.tempSerializingInsts 6835 # count of temporary serializing insts renamed 499system.cpu.rename.skidInsts 138814111 # count of insts added to the skid buffer 500system.cpu.memDep0.insertedLoads 271882035 # Number of loads inserted to the mem dependence unit. 501system.cpu.memDep0.insertedStores 160585921 # Number of stores inserted to the mem dependence unit. 502system.cpu.memDep0.conflictingLoads 6159068 # Number of conflicting loads. 503system.cpu.memDep0.conflictingStores 12159693 # Number of conflicting stores. 504system.cpu.iq.iqInstsAdded 899827224 # Number of instructions added to the IQ (excludes non-spec) 505system.cpu.iq.iqNonSpecInstsAdded 12580 # Number of non-speculative instructions added to the IQ 506system.cpu.iq.iqInstsIssued 860029296 # Number of instructions issued 507system.cpu.iq.iqSquashedInstsIssued 9216848 # Number of squashed instructions issued 508system.cpu.iq.iqSquashedInstsExamined 111114846 # Number of squashed instructions iterated over during squash; mainly for profiling 509system.cpu.iq.iqSquashedOperandsExamined 244387313 # Number of squashed operands that are examined and possibly removed from graph 510system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed 511system.cpu.iq.issued_per_cycle::samples 655368010 # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::mean 1.312285 # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::stdev 1.094624 # Number of insts issued each cycle | 508system.cpu.rename.UndoneMaps 106143238 # Number of HB maps that are undone due to squashing 509system.cpu.rename.serializingInsts 6855 # count of serializing insts renamed 510system.cpu.rename.tempSerializingInsts 6838 # count of temporary serializing insts renamed 511system.cpu.rename.skidInsts 138815476 # count of insts added to the skid buffer 512system.cpu.memDep0.insertedLoads 271882151 # Number of loads inserted to the mem dependence unit. 513system.cpu.memDep0.insertedStores 160587217 # Number of stores inserted to the mem dependence unit. 514system.cpu.memDep0.conflictingLoads 6164479 # Number of conflicting loads. 515system.cpu.memDep0.conflictingStores 12153288 # Number of conflicting stores. 516system.cpu.iq.iqInstsAdded 899827421 # Number of instructions added to the IQ (excludes non-spec) 517system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ 518system.cpu.iq.iqInstsIssued 860030622 # Number of instructions issued 519system.cpu.iq.iqSquashedInstsIssued 9216880 # Number of squashed instructions issued 520system.cpu.iq.iqSquashedInstsExamined 111115045 # Number of squashed instructions iterated over during squash; mainly for profiling 521system.cpu.iq.iqSquashedOperandsExamined 244388609 # Number of squashed operands that are examined and possibly removed from graph 522system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed 523system.cpu.iq.issued_per_cycle::samples 677553693 # Number of insts issued each cycle 524system.cpu.iq.issued_per_cycle::mean 1.269317 # Number of insts issued each cycle 525system.cpu.iq.issued_per_cycle::stdev 1.101593 # Number of insts issued each cycle |
| 514system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 526system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 515system.cpu.iq.issued_per_cycle::0 192710599 29.40% 29.40% # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::1 182406257 27.83% 57.24% # Number of insts issued each cycle 517system.cpu.iq.issued_per_cycle::2 175554116 26.79% 84.02% # Number of insts issued each cycle 518system.cpu.iq.issued_per_cycle::3 92275656 14.08% 98.10% # Number of insts issued each cycle 519system.cpu.iq.issued_per_cycle::4 12419071 1.89% 100.00% # Number of insts issued each cycle | 527system.cpu.iq.issued_per_cycle::0 214894884 31.72% 31.72% # Number of insts issued each cycle 528system.cpu.iq.issued_per_cycle::1 182407403 26.92% 58.64% # Number of insts issued each cycle 529system.cpu.iq.issued_per_cycle::2 175555467 25.91% 84.55% # Number of insts issued each cycle 530system.cpu.iq.issued_per_cycle::3 92273782 13.62% 98.17% # Number of insts issued each cycle 531system.cpu.iq.issued_per_cycle::4 12419846 1.83% 100.00% # Number of insts issued each cycle |
| 520system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle 521system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 522system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 523system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 524system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 525system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 526system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 532system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle 533system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 534system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 535system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 536system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 537system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 538system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 527system.cpu.iq.issued_per_cycle::total 655368010 # Number of insts issued each cycle | 539system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle |
| 528system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 540system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 529system.cpu.iq.fu_full::IntAlu 66605310 24.62% 24.62% # attempts to use FU when none available | 541system.cpu.iq.fu_full::IntAlu 66603323 24.62% 24.62% # attempts to use FU when none available |
| 530system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available 531system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available 532system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available 533system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available 534system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available 535system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available 536system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available 537system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 550system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available 551system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available 552system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available 553system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available 554system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available 555system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available 556system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available 557system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available | 542system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available 543system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available 544system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available 545system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available 546system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available 547system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available 548system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available 549system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 562system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available 563system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available 564system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available 565system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available 566system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available 567system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available 568system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available 569system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available |
| 558system.cpu.iq.fu_full::MemRead 134121363 49.58% 74.45% # attempts to use FU when none available 559system.cpu.iq.fu_full::MemWrite 69112589 25.55% 100.00% # attempts to use FU when none available | 570system.cpu.iq.fu_full::MemRead 134116736 49.58% 74.45% # attempts to use FU when none available 571system.cpu.iq.fu_full::MemWrite 69116750 25.55% 100.00% # attempts to use FU when none available |
| 560system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 561system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 562system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 572system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 573system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 574system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 563system.cpu.iq.FU_type_0::IntAlu 413090005 48.03% 48.03% # Type of FU issued 564system.cpu.iq.FU_type_0::IntMult 5187656 0.60% 48.64% # Type of FU issued | 575system.cpu.iq.FU_type_0::IntAlu 413090046 48.03% 48.03% # Type of FU issued 576system.cpu.iq.FU_type_0::IntMult 5187659 0.60% 48.64% # Type of FU issued |
| 565system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued 566system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued 567system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued 568system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued 569system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued 570system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued 571system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 578system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued 582system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued 583system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued 584system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued 585system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued | 577system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued 578system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued 579system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued 580system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued 581system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued 582system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued 583system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued 584system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 590system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued 591system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued 592system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued 593system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued 594system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued 595system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued 596system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued 597system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued |
| 586system.cpu.iq.FU_type_0::SimdFloatCvt 2550150 0.30% 49.38% # Type of FU issued | 598system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued |
| 587system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued | 599system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued |
| 588system.cpu.iq.FU_type_0::SimdFloatMisc 11478194 1.33% 50.71% # Type of FU issued | 600system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued |
| 589system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued 590system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued 591system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued | 601system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued 602system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued 603system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued |
| 592system.cpu.iq.FU_type_0::MemRead 266665504 31.01% 81.72% # Type of FU issued 593system.cpu.iq.FU_type_0::MemWrite 157232585 18.28% 100.00% # Type of FU issued | 604system.cpu.iq.FU_type_0::MemRead 266665907 31.01% 81.72% # Type of FU issued 605system.cpu.iq.FU_type_0::MemWrite 157233466 18.28% 100.00% # Type of FU issued |
| 594system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 595system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 606system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 607system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 596system.cpu.iq.FU_type_0::total 860029296 # Type of FU issued 597system.cpu.iq.rate 1.311438 # Inst issue rate 598system.cpu.iq.fu_busy_cnt 270494293 # FU busy when requested 599system.cpu.iq.fu_busy_rate 0.314518 # FU busy rate (busy events/executed inst) 600system.cpu.iq.int_inst_queue_reads 2597595667 # Number of integer instruction queue reads 601system.cpu.iq.int_inst_queue_writes 980331886 # Number of integer instruction queue writes 602system.cpu.iq.int_inst_queue_wakeup_accesses 820082893 # Number of integer instruction queue wakeup accesses 603system.cpu.iq.fp_inst_queue_reads 57542076 # Number of floating instruction queue reads | 608system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued 609system.cpu.iq.rate 1.268433 # Inst issue rate 610system.cpu.iq.fu_busy_cnt 270491840 # FU busy when requested 611system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) 612system.cpu.iq.int_inst_queue_reads 2619781164 # Number of integer instruction queue reads 613system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes 614system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses 615system.cpu.iq.fp_inst_queue_reads 57542493 # Number of floating instruction queue reads |
| 604system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes | 616system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes |
| 605system.cpu.iq.fp_inst_queue_wakeup_accesses 24878673 # Number of floating instruction queue wakeup accesses 606system.cpu.iq.int_alu_accesses 1098503163 # Number of integer alu accesses 607system.cpu.iq.fp_alu_accesses 32020426 # Number of floating point alu accesses 608system.cpu.iew.lsq.thread0.forwLoads 13986768 # Number of loads that had data forwarded from stores | 617system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses 618system.cpu.iq.int_alu_accesses 1098501615 # Number of integer alu accesses 619system.cpu.iq.fp_alu_accesses 32020847 # Number of floating point alu accesses 620system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores |
| 609system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 621system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 610system.cpu.iew.lsq.thread0.squashedLoads 19641097 # Number of loads squashed 611system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed 612system.cpu.iew.lsq.thread0.memOrderViolation 18820 # Number of memory ordering violations 613system.cpu.iew.lsq.thread0.squashedStores 31605425 # Number of stores squashed | 622system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed 623system.cpu.iew.lsq.thread0.ignoredResponses 120 # Number of memory responses ignored because the instruction is squashed 624system.cpu.iew.lsq.thread0.memOrderViolation 18827 # Number of memory ordering violations 625system.cpu.iew.lsq.thread0.squashedStores 31606721 # Number of stores squashed |
| 614system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 615system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 626system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 627system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 616system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled 617system.cpu.iew.lsq.thread0.cacheBlocked 17201 # Number of times an access to memory failed due to the cache being blocked | 628system.cpu.iew.lsq.thread0.rescheduledLoads 1918912 # Number of loads that were rescheduled 629system.cpu.iew.lsq.thread0.cacheBlocked 17820 # Number of times an access to memory failed due to the cache being blocked |
| 618system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 630system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 619system.cpu.iew.iewSquashCycles 4021010 # Number of cycles IEW is squashing 620system.cpu.iew.iewBlockCycles 10590461 # Number of cycles IEW is blocking 621system.cpu.iew.iewUnblockCycles 6281 # Number of cycles IEW is unblocking 622system.cpu.iew.iewDispatchedInsts 899849934 # Number of instructions dispatched to IQ | 631system.cpu.iew.iewSquashCycles 4021025 # Number of cycles IEW is squashing 632system.cpu.iew.iewBlockCycles 10591534 # Number of cycles IEW is blocking 633system.cpu.iew.iewUnblockCycles 6199 # Number of cycles IEW is unblocking 634system.cpu.iew.iewDispatchedInsts 899849877 # Number of instructions dispatched to IQ |
| 623system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 635system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 624system.cpu.iew.iewDispLoadInsts 271882035 # Number of dispatched load instructions 625system.cpu.iew.iewDispStoreInsts 160585921 # Number of dispatched store instructions 626system.cpu.iew.iewDispNonSpecInsts 6840 # Number of dispatched non-speculative instructions 627system.cpu.iew.iewIQFullEvents 959 # Number of times the IQ has become full, causing a stall 628system.cpu.iew.iewLSQFullEvents 3423 # Number of times the LSQ has become full, causing a stall 629system.cpu.iew.memOrderViolationEvents 18820 # Number of memory order violations 630system.cpu.iew.predictedTakenIncorrect 3295129 # Number of branches that were predicted taken incorrectly 631system.cpu.iew.predictedNotTakenIncorrect 3290187 # Number of branches that were predicted not taken incorrectly 632system.cpu.iew.branchMispredicts 6585316 # Number of branch mispredicts detected at execute 633system.cpu.iew.iewExecutedInsts 850173752 # Number of executed instructions 634system.cpu.iew.iewExecLoadInsts 263373804 # Number of load instructions executed 635system.cpu.iew.iewExecSquashedInsts 9855544 # Number of squashed instructions skipped in execute | 636system.cpu.iew.iewDispLoadInsts 271882151 # Number of dispatched load instructions 637system.cpu.iew.iewDispStoreInsts 160587217 # Number of dispatched store instructions 638system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions 639system.cpu.iew.iewIQFullEvents 967 # Number of times the IQ has become full, causing a stall 640system.cpu.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall 641system.cpu.iew.memOrderViolationEvents 18827 # Number of memory order violations 642system.cpu.iew.predictedTakenIncorrect 3295145 # Number of branches that were predicted taken incorrectly 643system.cpu.iew.predictedNotTakenIncorrect 3289956 # Number of branches that were predicted not taken incorrectly 644system.cpu.iew.branchMispredicts 6585101 # Number of branch mispredicts detected at execute 645system.cpu.iew.iewExecutedInsts 850175089 # Number of executed instructions 646system.cpu.iew.iewExecLoadInsts 263374398 # Number of load instructions executed 647system.cpu.iew.iewExecSquashedInsts 9855533 # Number of squashed instructions skipped in execute |
| 636system.cpu.iew.exec_swp 0 # number of swp insts executed | 648system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 637system.cpu.iew.exec_nop 10130 # number of nop insts executed 638system.cpu.iew.exec_refs 416063188 # number of memory reference insts executed 639system.cpu.iew.exec_branches 143381327 # Number of branches executed 640system.cpu.iew.exec_stores 152689384 # Number of stores executed 641system.cpu.iew.exec_rate 1.296409 # Inst execution rate 642system.cpu.iew.wb_sent 846297655 # cumulative count of insts sent to commit 643system.cpu.iew.wb_count 844961566 # cumulative count of insts written-back 644system.cpu.iew.wb_producers 487343298 # num instructions producing a value 645system.cpu.iew.wb_consumers 808106626 # num instructions consuming a value 646system.cpu.iew.wb_rate 1.288461 # insts written-back per cycle 647system.cpu.iew.wb_fanout 0.603068 # average fanout of values written-back 648system.cpu.commit.commitSquashedInsts 103169122 # The number of squashed insts skipped by commit | 649system.cpu.iew.exec_nop 9874 # number of nop insts executed 650system.cpu.iew.exec_refs 416064413 # number of memory reference insts executed 651system.cpu.iew.exec_branches 143381564 # Number of branches executed 652system.cpu.iew.exec_stores 152690015 # Number of stores executed 653system.cpu.iew.exec_rate 1.253898 # Inst execution rate 654system.cpu.iew.wb_sent 846298256 # cumulative count of insts sent to commit 655system.cpu.iew.wb_count 844962326 # cumulative count of insts written-back 656system.cpu.iew.wb_producers 487342605 # num instructions producing a value 657system.cpu.iew.wb_consumers 808106527 # num instructions consuming a value 658system.cpu.iew.wb_rate 1.246210 # insts written-back per cycle 659system.cpu.iew.wb_fanout 0.603067 # average fanout of values written-back 660system.cpu.commit.commitSquashedInsts 103169288 # The number of squashed insts skipped by commit |
| 649system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards | 661system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards |
| 650system.cpu.commit.branchMispredicts 4002654 # The number of times a branch was mispredicted 651system.cpu.commit.committed_per_cycle::samples 640787345 # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::mean 1.230876 # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::stdev 2.070419 # Number of insts commited each cycle | 662system.cpu.commit.branchMispredicts 4002671 # The number of times a branch was mispredicted 663system.cpu.commit.committed_per_cycle::samples 662973012 # Number of insts commited each cycle 664system.cpu.commit.committed_per_cycle::mean 1.189687 # Number of insts commited each cycle 665system.cpu.commit.committed_per_cycle::stdev 2.047483 # Number of insts commited each cycle |
| 654system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 666system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 655system.cpu.commit.committed_per_cycle::0 350447626 54.69% 54.69% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::1 137241088 21.42% 76.11% # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::2 51341072 8.01% 84.12% # Number of insts commited each cycle 658system.cpu.commit.committed_per_cycle::3 28220230 4.40% 88.52% # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::4 14380949 2.24% 90.77% # Number of insts commited each cycle 660system.cpu.commit.committed_per_cycle::5 14774505 2.31% 93.07% # Number of insts commited each cycle 661system.cpu.commit.committed_per_cycle::6 7871971 1.23% 94.30% # Number of insts commited each cycle 662system.cpu.commit.committed_per_cycle::7 6561231 1.02% 95.33% # Number of insts commited each cycle 663system.cpu.commit.committed_per_cycle::8 29948673 4.67% 100.00% # Number of insts commited each cycle | 667system.cpu.commit.committed_per_cycle::0 372633677 56.21% 56.21% # Number of insts commited each cycle 668system.cpu.commit.committed_per_cycle::1 137240232 20.70% 76.91% # Number of insts commited each cycle 669system.cpu.commit.committed_per_cycle::2 51341106 7.74% 84.65% # Number of insts commited each cycle 670system.cpu.commit.committed_per_cycle::3 28220443 4.26% 88.91% # Number of insts commited each cycle 671system.cpu.commit.committed_per_cycle::4 14381462 2.17% 91.08% # Number of insts commited each cycle 672system.cpu.commit.committed_per_cycle::5 14774618 2.23% 93.31% # Number of insts commited each cycle 673system.cpu.commit.committed_per_cycle::6 7871678 1.19% 94.49% # Number of insts commited each cycle 674system.cpu.commit.committed_per_cycle::7 6561077 0.99% 95.48% # Number of insts commited each cycle 675system.cpu.commit.committed_per_cycle::8 29948719 4.52% 100.00% # Number of insts commited each cycle |
| 664system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 665system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 666system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 676system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 677system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 678system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 667system.cpu.commit.committed_per_cycle::total 640787345 # Number of insts commited each cycle | 679system.cpu.commit.committed_per_cycle::total 662973012 # Number of insts commited each cycle |
| 668system.cpu.commit.committedInsts 640654411 # Number of instructions committed 669system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed 670system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 671system.cpu.commit.refs 381221434 # Number of memory references committed 672system.cpu.commit.loads 252240938 # Number of loads committed 673system.cpu.commit.membars 5740 # Number of memory barriers committed 674system.cpu.commit.branches 137364860 # Number of branches committed 675system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 705system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 706system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 707system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 708system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 709system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 710system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 711system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 712system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction | 680system.cpu.commit.committedInsts 640654411 # Number of instructions committed 681system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed 682system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 683system.cpu.commit.refs 381221434 # Number of memory references committed 684system.cpu.commit.loads 252240938 # Number of loads committed 685system.cpu.commit.membars 5740 # Number of memory barriers committed 686system.cpu.commit.branches 137364860 # Number of branches committed 687system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 717system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 718system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 719system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 720system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 721system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 722system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 723system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 724system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction |
| 713system.cpu.commit.bw_lim_events 29948673 # number cycles where commit BW limit reached 714system.cpu.rob.rob_reads 1502729113 # The number of ROB reads 715system.cpu.rob.rob_writes 1798382436 # The number of ROB writes 716system.cpu.timesIdled 10485 # Number of times that the entire CPU went into an idle state and unscheduled itself 717system.cpu.idleCycles 423267 # Total number of cycles that the CPU has spent unscheduled due to idling | 725system.cpu.commit.bw_lim_events 29948719 # number cycles where commit BW limit reached 726system.cpu.rob.rob_reads 1524914900 # The number of ROB reads 727system.cpu.rob.rob_writes 1798382781 # The number of ROB writes 728system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself 729system.cpu.idleCycles 472172 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 718system.cpu.committedInsts 640649299 # Number of Instructions Simulated 719system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated | 730system.cpu.committedInsts 640649299 # Number of Instructions Simulated 731system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated |
| 720system.cpu.cpi 1.023635 # CPI: Cycles Per Instruction 721system.cpu.cpi_total 1.023635 # CPI: Total CPI of All Threads 722system.cpu.ipc 0.976910 # IPC: Instructions Per Cycle 723system.cpu.ipc_total 0.976910 # IPC: Total IPC of All Threads 724system.cpu.int_regfile_reads 868461212 # number of integer regfile reads 725system.cpu.int_regfile_writes 500699124 # number of integer regfile writes 726system.cpu.fp_regfile_reads 30616064 # number of floating regfile reads 727system.cpu.fp_regfile_writes 22959493 # number of floating regfile writes 728system.cpu.cc_regfile_reads 3322386264 # number of cc regfile reads 729system.cpu.cc_regfile_writes 369207629 # number of cc regfile writes 730system.cpu.misc_regfile_reads 606832888 # number of misc regfile reads | 732system.cpu.cpi 1.058342 # CPI: Cycles Per Instruction 733system.cpu.cpi_total 1.058342 # CPI: Total CPI of All Threads 734system.cpu.ipc 0.944874 # IPC: Instructions Per Cycle 735system.cpu.ipc_total 0.944874 # IPC: Total IPC of All Threads 736system.cpu.int_regfile_reads 868463326 # number of integer regfile reads 737system.cpu.int_regfile_writes 500698648 # number of integer regfile writes 738system.cpu.fp_regfile_reads 30616063 # number of floating regfile reads 739system.cpu.fp_regfile_writes 22959490 # number of floating regfile writes 740system.cpu.cc_regfile_reads 3322389826 # number of cc regfile reads 741system.cpu.cc_regfile_writes 369207773 # number of cc regfile writes 742system.cpu.misc_regfile_reads 606833337 # number of misc regfile reads |
| 731system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes | 743system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes |
| 732system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 733system.cpu.dcache.tags.replacements 2756458 # number of replacements 734system.cpu.dcache.tags.tagsinuse 511.912011 # Cycle average of tags in use 735system.cpu.dcache.tags.total_refs 371050492 # Total number of references to valid blocks. 736system.cpu.dcache.tags.sampled_refs 2756970 # Sample count of references to valid blocks. 737system.cpu.dcache.tags.avg_refs 134.586336 # Average number of references to valid blocks. 738system.cpu.dcache.tags.warmup_cycle 274880000 # Cycle when the warmup percentage was hit. 739system.cpu.dcache.tags.occ_blocks::cpu.data 511.912011 # Average occupied blocks per requestor 740system.cpu.dcache.tags.occ_percent::cpu.data 0.999828 # Average percentage of cache occupancy 741system.cpu.dcache.tags.occ_percent::total 0.999828 # Average percentage of cache occupancy | 744system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 745system.cpu.dcache.tags.replacements 2756453 # number of replacements 746system.cpu.dcache.tags.tagsinuse 511.911144 # Cycle average of tags in use 747system.cpu.dcache.tags.total_refs 371050846 # Total number of references to valid blocks. 748system.cpu.dcache.tags.sampled_refs 2756965 # Sample count of references to valid blocks. 749system.cpu.dcache.tags.avg_refs 134.586709 # Average number of references to valid blocks. 750system.cpu.dcache.tags.warmup_cycle 285699000 # Cycle when the warmup percentage was hit. 751system.cpu.dcache.tags.occ_blocks::cpu.data 511.911144 # Average occupied blocks per requestor 752system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy 753system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy |
| 742system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 754system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 743system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 744system.cpu.dcache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id 745system.cpu.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id | 755system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 756system.cpu.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 757system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id |
| 746system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 747system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 758system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 759system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 748system.cpu.dcache.tags.tag_accesses 751746846 # Number of tag accesses 749system.cpu.dcache.tags.data_accesses 751746846 # Number of data accesses 750system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 751system.cpu.dcache.ReadReq_hits::cpu.data 243126867 # number of ReadReq hits 752system.cpu.dcache.ReadReq_hits::total 243126867 # number of ReadReq hits 753system.cpu.dcache.WriteReq_hits::cpu.data 127907624 # number of WriteReq hits 754system.cpu.dcache.WriteReq_hits::total 127907624 # number of WriteReq hits | 760system.cpu.dcache.tags.tag_accesses 751747893 # Number of tag accesses 761system.cpu.dcache.tags.data_accesses 751747893 # Number of data accesses 762system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 763system.cpu.dcache.ReadReq_hits::cpu.data 243127355 # number of ReadReq hits 764system.cpu.dcache.ReadReq_hits::total 243127355 # number of ReadReq hits 765system.cpu.dcache.WriteReq_hits::cpu.data 127907428 # number of WriteReq hits 766system.cpu.dcache.WriteReq_hits::total 127907428 # number of WriteReq hits |
| 755system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits 756system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits | 767system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits 768system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits |
| 757system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits 758system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits | 769system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 770system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits |
| 759system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 760system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits | 771system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 772system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits |
| 761system.cpu.dcache.demand_hits::cpu.data 371034491 # number of demand (read+write) hits 762system.cpu.dcache.demand_hits::total 371034491 # number of demand (read+write) hits 763system.cpu.dcache.overall_hits::cpu.data 371037648 # number of overall hits 764system.cpu.dcache.overall_hits::total 371037648 # number of overall hits 765system.cpu.dcache.ReadReq_misses::cpu.data 2401310 # number of ReadReq misses 766system.cpu.dcache.ReadReq_misses::total 2401310 # number of ReadReq misses 767system.cpu.dcache.WriteReq_misses::cpu.data 1043853 # number of WriteReq misses 768system.cpu.dcache.WriteReq_misses::total 1043853 # number of WriteReq misses | 773system.cpu.dcache.demand_hits::cpu.data 371034783 # number of demand (read+write) hits 774system.cpu.dcache.demand_hits::total 371034783 # number of demand (read+write) hits 775system.cpu.dcache.overall_hits::cpu.data 371037940 # number of overall hits 776system.cpu.dcache.overall_hits::total 371037940 # number of overall hits 777system.cpu.dcache.ReadReq_misses::cpu.data 2401348 # number of ReadReq misses 778system.cpu.dcache.ReadReq_misses::total 2401348 # number of ReadReq misses 779system.cpu.dcache.WriteReq_misses::cpu.data 1044049 # number of WriteReq misses 780system.cpu.dcache.WriteReq_misses::total 1044049 # number of WriteReq misses |
| 769system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses 770system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses | 781system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses 782system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses |
| 771system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 772system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 773system.cpu.dcache.demand_misses::cpu.data 3445163 # number of demand (read+write) misses 774system.cpu.dcache.demand_misses::total 3445163 # number of demand (read+write) misses 775system.cpu.dcache.overall_misses::cpu.data 3445810 # number of overall misses 776system.cpu.dcache.overall_misses::total 3445810 # number of overall misses 777system.cpu.dcache.ReadReq_miss_latency::cpu.data 69278020000 # number of ReadReq miss cycles 778system.cpu.dcache.ReadReq_miss_latency::total 69278020000 # number of ReadReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::cpu.data 9882341350 # number of WriteReq miss cycles 780system.cpu.dcache.WriteReq_miss_latency::total 9882341350 # number of WriteReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 168500 # number of LoadLockedReq miss cycles 782system.cpu.dcache.LoadLockedReq_miss_latency::total 168500 # number of LoadLockedReq miss cycles 783system.cpu.dcache.demand_miss_latency::cpu.data 79160361350 # number of demand (read+write) miss cycles 784system.cpu.dcache.demand_miss_latency::total 79160361350 # number of demand (read+write) miss cycles 785system.cpu.dcache.overall_miss_latency::cpu.data 79160361350 # number of overall miss cycles 786system.cpu.dcache.overall_miss_latency::total 79160361350 # number of overall miss cycles 787system.cpu.dcache.ReadReq_accesses::cpu.data 245528177 # number of ReadReq accesses(hits+misses) 788system.cpu.dcache.ReadReq_accesses::total 245528177 # number of ReadReq accesses(hits+misses) | 783system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 784system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 785system.cpu.dcache.demand_misses::cpu.data 3445397 # number of demand (read+write) misses 786system.cpu.dcache.demand_misses::total 3445397 # number of demand (read+write) misses 787system.cpu.dcache.overall_misses::cpu.data 3446044 # number of overall misses 788system.cpu.dcache.overall_misses::total 3446044 # number of overall misses 789system.cpu.dcache.ReadReq_miss_latency::cpu.data 80462385500 # number of ReadReq miss cycles 790system.cpu.dcache.ReadReq_miss_latency::total 80462385500 # number of ReadReq miss cycles 791system.cpu.dcache.WriteReq_miss_latency::cpu.data 10017236850 # number of WriteReq miss cycles 792system.cpu.dcache.WriteReq_miss_latency::total 10017236850 # number of WriteReq miss cycles 793system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles 794system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles 795system.cpu.dcache.demand_miss_latency::cpu.data 90479622350 # number of demand (read+write) miss cycles 796system.cpu.dcache.demand_miss_latency::total 90479622350 # number of demand (read+write) miss cycles 797system.cpu.dcache.overall_miss_latency::cpu.data 90479622350 # number of overall miss cycles 798system.cpu.dcache.overall_miss_latency::total 90479622350 # number of overall miss cycles 799system.cpu.dcache.ReadReq_accesses::cpu.data 245528703 # number of ReadReq accesses(hits+misses) 800system.cpu.dcache.ReadReq_accesses::total 245528703 # number of ReadReq accesses(hits+misses) |
| 789system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 791system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) 792system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) 793system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) 794system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) 795system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 796system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) | 801system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 802system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 803system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) 804system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) 805system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) 806system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) 807system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 808system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) |
| 797system.cpu.dcache.demand_accesses::cpu.data 374479654 # number of demand (read+write) accesses 798system.cpu.dcache.demand_accesses::total 374479654 # number of demand (read+write) accesses 799system.cpu.dcache.overall_accesses::cpu.data 374483458 # number of overall (read+write) accesses 800system.cpu.dcache.overall_accesses::total 374483458 # number of overall (read+write) accesses | 809system.cpu.dcache.demand_accesses::cpu.data 374480180 # number of demand (read+write) accesses 810system.cpu.dcache.demand_accesses::total 374480180 # number of demand (read+write) accesses 811system.cpu.dcache.overall_accesses::cpu.data 374483984 # number of overall (read+write) accesses 812system.cpu.dcache.overall_accesses::total 374483984 # number of overall (read+write) accesses |
| 801system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses 802system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses | 813system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses 814system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses |
| 803system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses 804system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses | 815system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008096 # miss rate for WriteReq accesses 816system.cpu.dcache.WriteReq_miss_rate::total 0.008096 # miss rate for WriteReq accesses |
| 805system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses 806system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses | 817system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses 818system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses |
| 807system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 808system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses | 819system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses 820system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses |
| 809system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses 810system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses 811system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses 812system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses | 821system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses 822system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses 823system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses 824system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses |
| 813system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28850.094324 # average ReadReq miss latency 814system.cpu.dcache.ReadReq_avg_miss_latency::total 28850.094324 # average ReadReq miss latency 815system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9467.177227 # average WriteReq miss latency 816system.cpu.dcache.WriteReq_avg_miss_latency::total 9467.177227 # average WriteReq miss latency 817system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56166.666667 # average LoadLockedReq miss latency 818system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56166.666667 # average LoadLockedReq miss latency 819system.cpu.dcache.demand_avg_miss_latency::cpu.data 22977.247042 # average overall miss latency 820system.cpu.dcache.demand_avg_miss_latency::total 22977.247042 # average overall miss latency 821system.cpu.dcache.overall_avg_miss_latency::cpu.data 22972.932736 # average overall miss latency 822system.cpu.dcache.overall_avg_miss_latency::total 22972.932736 # average overall miss latency 823system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 824system.cpu.dcache.blocked_cycles::no_targets 322646 # number of cycles access was blocked 825system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 826system.cpu.dcache.blocked::no_targets 4628 # number of cycles access was blocked 827system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 828system.cpu.dcache.avg_blocked_cycles::no_targets 69.716076 # average number of cycles each access was blocked 829system.cpu.dcache.writebacks::writebacks 2756458 # number of writebacks 830system.cpu.dcache.writebacks::total 2756458 # number of writebacks 831system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365828 # number of ReadReq MSHR hits 832system.cpu.dcache.ReadReq_mshr_hits::total 365828 # number of ReadReq MSHR hits 833system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322833 # number of WriteReq MSHR hits 834system.cpu.dcache.WriteReq_mshr_hits::total 322833 # number of WriteReq MSHR hits 835system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 836system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 837system.cpu.dcache.demand_mshr_hits::cpu.data 688661 # number of demand (read+write) MSHR hits 838system.cpu.dcache.demand_mshr_hits::total 688661 # number of demand (read+write) MSHR hits 839system.cpu.dcache.overall_mshr_hits::cpu.data 688661 # number of overall MSHR hits 840system.cpu.dcache.overall_mshr_hits::total 688661 # number of overall MSHR hits 841system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035482 # number of ReadReq MSHR misses 842system.cpu.dcache.ReadReq_mshr_misses::total 2035482 # number of ReadReq MSHR misses 843system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721020 # number of WriteReq MSHR misses 844system.cpu.dcache.WriteReq_mshr_misses::total 721020 # number of WriteReq MSHR misses | 825system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33507.174096 # average ReadReq miss latency 826system.cpu.dcache.ReadReq_avg_miss_latency::total 33507.174096 # average ReadReq miss latency 827system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9594.604133 # average WriteReq miss latency 828system.cpu.dcache.WriteReq_avg_miss_latency::total 9594.604133 # average WriteReq miss latency 829system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency 830system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency 831system.cpu.dcache.demand_avg_miss_latency::cpu.data 26261.015015 # average overall miss latency 832system.cpu.dcache.demand_avg_miss_latency::total 26261.015015 # average overall miss latency 833system.cpu.dcache.overall_avg_miss_latency::cpu.data 26256.084470 # average overall miss latency 834system.cpu.dcache.overall_avg_miss_latency::total 26256.084470 # average overall miss latency 835system.cpu.dcache.blocked_cycles::no_mshrs 71 # number of cycles access was blocked 836system.cpu.dcache.blocked_cycles::no_targets 355259 # number of cycles access was blocked 837system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 838system.cpu.dcache.blocked::no_targets 4691 # number of cycles access was blocked 839system.cpu.dcache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked 840system.cpu.dcache.avg_blocked_cycles::no_targets 75.732040 # average number of cycles each access was blocked 841system.cpu.dcache.writebacks::writebacks 2756453 # number of writebacks 842system.cpu.dcache.writebacks::total 2756453 # number of writebacks 843system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365871 # number of ReadReq MSHR hits 844system.cpu.dcache.ReadReq_mshr_hits::total 365871 # number of ReadReq MSHR hits 845system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323013 # number of WriteReq MSHR hits 846system.cpu.dcache.WriteReq_mshr_hits::total 323013 # number of WriteReq MSHR hits 847system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 848system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 849system.cpu.dcache.demand_mshr_hits::cpu.data 688884 # number of demand (read+write) MSHR hits 850system.cpu.dcache.demand_mshr_hits::total 688884 # number of demand (read+write) MSHR hits 851system.cpu.dcache.overall_mshr_hits::cpu.data 688884 # number of overall MSHR hits 852system.cpu.dcache.overall_mshr_hits::total 688884 # number of overall MSHR hits 853system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses 854system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses 855system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721036 # number of WriteReq MSHR misses 856system.cpu.dcache.WriteReq_mshr_misses::total 721036 # number of WriteReq MSHR misses |
| 845system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses 846system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses | 857system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses 858system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses |
| 847system.cpu.dcache.demand_mshr_misses::cpu.data 2756502 # number of demand (read+write) MSHR misses 848system.cpu.dcache.demand_mshr_misses::total 2756502 # number of demand (read+write) MSHR misses 849system.cpu.dcache.overall_mshr_misses::cpu.data 2757144 # number of overall MSHR misses 850system.cpu.dcache.overall_mshr_misses::total 2757144 # number of overall MSHR misses 851system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64102936000 # number of ReadReq MSHR miss cycles 852system.cpu.dcache.ReadReq_mshr_miss_latency::total 64102936000 # number of ReadReq MSHR miss cycles 853system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5940509850 # number of WriteReq MSHR miss cycles 854system.cpu.dcache.WriteReq_mshr_miss_latency::total 5940509850 # number of WriteReq MSHR miss cycles 855system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5561000 # number of SoftPFReq MSHR miss cycles 856system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5561000 # number of SoftPFReq MSHR miss cycles 857system.cpu.dcache.demand_mshr_miss_latency::cpu.data 70043445850 # number of demand (read+write) MSHR miss cycles 858system.cpu.dcache.demand_mshr_miss_latency::total 70043445850 # number of demand (read+write) MSHR miss cycles 859system.cpu.dcache.overall_mshr_miss_latency::cpu.data 70049006850 # number of overall MSHR miss cycles 860system.cpu.dcache.overall_mshr_miss_latency::total 70049006850 # number of overall MSHR miss cycles | 859system.cpu.dcache.demand_mshr_misses::cpu.data 2756513 # number of demand (read+write) MSHR misses 860system.cpu.dcache.demand_mshr_misses::total 2756513 # number of demand (read+write) MSHR misses 861system.cpu.dcache.overall_mshr_misses::cpu.data 2757155 # number of overall MSHR misses 862system.cpu.dcache.overall_mshr_misses::total 2757155 # number of overall MSHR misses 863system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75218139500 # number of ReadReq MSHR miss cycles 864system.cpu.dcache.ReadReq_mshr_miss_latency::total 75218139500 # number of ReadReq MSHR miss cycles 865system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959023850 # number of WriteReq MSHR miss cycles 866system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959023850 # number of WriteReq MSHR miss cycles 867system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5957500 # number of SoftPFReq MSHR miss cycles 868system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5957500 # number of SoftPFReq MSHR miss cycles 869system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81177163350 # number of demand (read+write) MSHR miss cycles 870system.cpu.dcache.demand_mshr_miss_latency::total 81177163350 # number of demand (read+write) MSHR miss cycles 871system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81183120850 # number of overall MSHR miss cycles 872system.cpu.dcache.overall_mshr_miss_latency::total 81183120850 # number of overall MSHR miss cycles |
| 861system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses 862system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses | 873system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses 874system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses |
| 863system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses 864system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses | 875system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses 876system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses |
| 865system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses 866system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses 867system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses 868system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses 869system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses 870system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses | 877system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses 878system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses 879system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses 880system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses 881system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses 882system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses |
| 871system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31492.755033 # average ReadReq mshr miss latency 872system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31492.755033 # average ReadReq mshr miss latency 873system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8239.036157 # average WriteReq mshr miss latency 874system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8239.036157 # average WriteReq mshr miss latency 875system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8661.993769 # average SoftPFReq mshr miss latency 876system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8661.993769 # average SoftPFReq mshr miss latency 877system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25410.264839 # average overall mshr miss latency 878system.cpu.dcache.demand_avg_mshr_miss_latency::total 25410.264839 # average overall mshr miss latency 879system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25406.365010 # average overall mshr miss latency 880system.cpu.dcache.overall_avg_mshr_miss_latency::total 25406.365010 # average overall mshr miss latency 881system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states | 883system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36953.568869 # average ReadReq mshr miss latency 884system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36953.568869 # average ReadReq mshr miss latency 885system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8264.530273 # average WriteReq mshr miss latency 886system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8264.530273 # average WriteReq mshr miss latency 887system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9279.595016 # average SoftPFReq mshr miss latency 888system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9279.595016 # average SoftPFReq mshr miss latency 889system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29449.222024 # average overall mshr miss latency 890system.cpu.dcache.demand_avg_mshr_miss_latency::total 29449.222024 # average overall mshr miss latency 891system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29444.525553 # average overall mshr miss latency 892system.cpu.dcache.overall_avg_mshr_miss_latency::total 29444.525553 # average overall mshr miss latency 893system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states |
| 882system.cpu.icache.tags.replacements 1979522 # number of replacements | 894system.cpu.icache.tags.replacements 1979522 # number of replacements |
| 883system.cpu.icache.tags.tagsinuse 510.874726 # Cycle average of tags in use 884system.cpu.icache.tags.total_refs 245757404 # Total number of references to valid blocks. | 895system.cpu.icache.tags.tagsinuse 510.550232 # Cycle average of tags in use 896system.cpu.icache.tags.total_refs 245757624 # Total number of references to valid blocks. |
| 885system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. | 897system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. |
| 886system.cpu.icache.tags.avg_refs 124.117895 # Average number of references to valid blocks. 887system.cpu.icache.tags.warmup_cycle 264413500 # Cycle when the warmup percentage was hit. 888system.cpu.icache.tags.occ_blocks::cpu.inst 510.874726 # Average occupied blocks per requestor 889system.cpu.icache.tags.occ_percent::cpu.inst 0.997802 # Average percentage of cache occupancy 890system.cpu.icache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy | 898system.cpu.icache.tags.avg_refs 124.118006 # Average number of references to valid blocks. 899system.cpu.icache.tags.warmup_cycle 275112500 # Cycle when the warmup percentage was hit. 900system.cpu.icache.tags.occ_blocks::cpu.inst 510.550232 # Average occupied blocks per requestor 901system.cpu.icache.tags.occ_percent::cpu.inst 0.997168 # Average percentage of cache occupancy 902system.cpu.icache.tags.occ_percent::total 0.997168 # Average percentage of cache occupancy |
| 891system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 892system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id | 903system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 904system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id |
| 893system.cpu.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id | 905system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id |
| 894system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id | 906system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id |
| 895system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id | 907system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 908system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id |
| 896system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id | 909system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id |
| 897system.cpu.icache.tags.tag_accesses 497461440 # Number of tag accesses 898system.cpu.icache.tags.data_accesses 497461440 # Number of data accesses 899system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 900system.cpu.icache.ReadReq_hits::cpu.inst 245757408 # number of ReadReq hits 901system.cpu.icache.ReadReq_hits::total 245757408 # number of ReadReq hits 902system.cpu.icache.demand_hits::cpu.inst 245757408 # number of demand (read+write) hits 903system.cpu.icache.demand_hits::total 245757408 # number of demand (read+write) hits 904system.cpu.icache.overall_hits::cpu.inst 245757408 # number of overall hits 905system.cpu.icache.overall_hits::total 245757408 # number of overall hits 906system.cpu.icache.ReadReq_misses::cpu.inst 1983209 # number of ReadReq misses 907system.cpu.icache.ReadReq_misses::total 1983209 # number of ReadReq misses 908system.cpu.icache.demand_misses::cpu.inst 1983209 # number of demand (read+write) misses 909system.cpu.icache.demand_misses::total 1983209 # number of demand (read+write) misses 910system.cpu.icache.overall_misses::cpu.inst 1983209 # number of overall misses 911system.cpu.icache.overall_misses::total 1983209 # number of overall misses 912system.cpu.icache.ReadReq_miss_latency::cpu.inst 16177953926 # number of ReadReq miss cycles 913system.cpu.icache.ReadReq_miss_latency::total 16177953926 # number of ReadReq miss cycles 914system.cpu.icache.demand_miss_latency::cpu.inst 16177953926 # number of demand (read+write) miss cycles 915system.cpu.icache.demand_miss_latency::total 16177953926 # number of demand (read+write) miss cycles 916system.cpu.icache.overall_miss_latency::cpu.inst 16177953926 # number of overall miss cycles 917system.cpu.icache.overall_miss_latency::total 16177953926 # number of overall miss cycles 918system.cpu.icache.ReadReq_accesses::cpu.inst 247740617 # number of ReadReq accesses(hits+misses) 919system.cpu.icache.ReadReq_accesses::total 247740617 # number of ReadReq accesses(hits+misses) 920system.cpu.icache.demand_accesses::cpu.inst 247740617 # number of demand (read+write) accesses 921system.cpu.icache.demand_accesses::total 247740617 # number of demand (read+write) accesses 922system.cpu.icache.overall_accesses::cpu.inst 247740617 # number of overall (read+write) accesses 923system.cpu.icache.overall_accesses::total 247740617 # number of overall (read+write) accesses | 910system.cpu.icache.tags.tag_accesses 497462038 # Number of tag accesses 911system.cpu.icache.tags.data_accesses 497462038 # Number of data accesses 912system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 913system.cpu.icache.ReadReq_hits::cpu.inst 245757684 # number of ReadReq hits 914system.cpu.icache.ReadReq_hits::total 245757684 # number of ReadReq hits 915system.cpu.icache.demand_hits::cpu.inst 245757684 # number of demand (read+write) hits 916system.cpu.icache.demand_hits::total 245757684 # number of demand (read+write) hits 917system.cpu.icache.overall_hits::cpu.inst 245757684 # number of overall hits 918system.cpu.icache.overall_hits::total 245757684 # number of overall hits 919system.cpu.icache.ReadReq_misses::cpu.inst 1983224 # number of ReadReq misses 920system.cpu.icache.ReadReq_misses::total 1983224 # number of ReadReq misses 921system.cpu.icache.demand_misses::cpu.inst 1983224 # number of demand (read+write) misses 922system.cpu.icache.demand_misses::total 1983224 # number of demand (read+write) misses 923system.cpu.icache.overall_misses::cpu.inst 1983224 # number of overall misses 924system.cpu.icache.overall_misses::total 1983224 # number of overall misses 925system.cpu.icache.ReadReq_miss_latency::cpu.inst 16215368926 # number of ReadReq miss cycles 926system.cpu.icache.ReadReq_miss_latency::total 16215368926 # number of ReadReq miss cycles 927system.cpu.icache.demand_miss_latency::cpu.inst 16215368926 # number of demand (read+write) miss cycles 928system.cpu.icache.demand_miss_latency::total 16215368926 # number of demand (read+write) miss cycles 929system.cpu.icache.overall_miss_latency::cpu.inst 16215368926 # number of overall miss cycles 930system.cpu.icache.overall_miss_latency::total 16215368926 # number of overall miss cycles 931system.cpu.icache.ReadReq_accesses::cpu.inst 247740908 # number of ReadReq accesses(hits+misses) 932system.cpu.icache.ReadReq_accesses::total 247740908 # number of ReadReq accesses(hits+misses) 933system.cpu.icache.demand_accesses::cpu.inst 247740908 # number of demand (read+write) accesses 934system.cpu.icache.demand_accesses::total 247740908 # number of demand (read+write) accesses 935system.cpu.icache.overall_accesses::cpu.inst 247740908 # number of overall (read+write) accesses 936system.cpu.icache.overall_accesses::total 247740908 # number of overall (read+write) accesses |
| 924system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses 925system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses 926system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses 927system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses 928system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses 929system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses | 937system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses 938system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses 939system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses 940system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses 941system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses 942system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses |
| 930system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8157.462943 # average ReadReq miss latency 931system.cpu.icache.ReadReq_avg_miss_latency::total 8157.462943 # average ReadReq miss latency 932system.cpu.icache.demand_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency 933system.cpu.icache.demand_avg_miss_latency::total 8157.462943 # average overall miss latency 934system.cpu.icache.overall_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency 935system.cpu.icache.overall_avg_miss_latency::total 8157.462943 # average overall miss latency 936system.cpu.icache.blocked_cycles::no_mshrs 75964 # number of cycles access was blocked 937system.cpu.icache.blocked_cycles::no_targets 122 # number of cycles access was blocked 938system.cpu.icache.blocked::no_mshrs 2856 # number of cycles access was blocked 939system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 940system.cpu.icache.avg_blocked_cycles::no_mshrs 26.598039 # average number of cycles each access was blocked 941system.cpu.icache.avg_blocked_cycles::no_targets 24.400000 # average number of cycles each access was blocked | 943system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.266991 # average ReadReq miss latency 944system.cpu.icache.ReadReq_avg_miss_latency::total 8176.266991 # average ReadReq miss latency 945system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency 946system.cpu.icache.demand_avg_miss_latency::total 8176.266991 # average overall miss latency 947system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency 948system.cpu.icache.overall_avg_miss_latency::total 8176.266991 # average overall miss latency 949system.cpu.icache.blocked_cycles::no_mshrs 83168 # number of cycles access was blocked 950system.cpu.icache.blocked_cycles::no_targets 761 # number of cycles access was blocked 951system.cpu.icache.blocked::no_mshrs 2904 # number of cycles access was blocked 952system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked 953system.cpu.icache.avg_blocked_cycles::no_mshrs 28.639118 # average number of cycles each access was blocked 954system.cpu.icache.avg_blocked_cycles::no_targets 108.714286 # average number of cycles each access was blocked |
| 942system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks 943system.cpu.icache.writebacks::total 1979522 # number of writebacks | 955system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks 956system.cpu.icache.writebacks::total 1979522 # number of writebacks |
| 944system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3001 # number of ReadReq MSHR hits 945system.cpu.icache.ReadReq_mshr_hits::total 3001 # number of ReadReq MSHR hits 946system.cpu.icache.demand_mshr_hits::cpu.inst 3001 # number of demand (read+write) MSHR hits 947system.cpu.icache.demand_mshr_hits::total 3001 # number of demand (read+write) MSHR hits 948system.cpu.icache.overall_mshr_hits::cpu.inst 3001 # number of overall MSHR hits 949system.cpu.icache.overall_mshr_hits::total 3001 # number of overall MSHR hits 950system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980208 # number of ReadReq MSHR misses 951system.cpu.icache.ReadReq_mshr_misses::total 1980208 # number of ReadReq MSHR misses 952system.cpu.icache.demand_mshr_misses::cpu.inst 1980208 # number of demand (read+write) MSHR misses 953system.cpu.icache.demand_mshr_misses::total 1980208 # number of demand (read+write) MSHR misses 954system.cpu.icache.overall_mshr_misses::cpu.inst 1980208 # number of overall MSHR misses 955system.cpu.icache.overall_mshr_misses::total 1980208 # number of overall MSHR misses 956system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15149087440 # number of ReadReq MSHR miss cycles 957system.cpu.icache.ReadReq_mshr_miss_latency::total 15149087440 # number of ReadReq MSHR miss cycles 958system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15149087440 # number of demand (read+write) MSHR miss cycles 959system.cpu.icache.demand_mshr_miss_latency::total 15149087440 # number of demand (read+write) MSHR miss cycles 960system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15149087440 # number of overall MSHR miss cycles 961system.cpu.icache.overall_mshr_miss_latency::total 15149087440 # number of overall MSHR miss cycles | 957system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3000 # number of ReadReq MSHR hits 958system.cpu.icache.ReadReq_mshr_hits::total 3000 # number of ReadReq MSHR hits 959system.cpu.icache.demand_mshr_hits::cpu.inst 3000 # number of demand (read+write) MSHR hits 960system.cpu.icache.demand_mshr_hits::total 3000 # number of demand (read+write) MSHR hits 961system.cpu.icache.overall_mshr_hits::cpu.inst 3000 # number of overall MSHR hits 962system.cpu.icache.overall_mshr_hits::total 3000 # number of overall MSHR hits 963system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980224 # number of ReadReq MSHR misses 964system.cpu.icache.ReadReq_mshr_misses::total 1980224 # number of ReadReq MSHR misses 965system.cpu.icache.demand_mshr_misses::cpu.inst 1980224 # number of demand (read+write) MSHR misses 966system.cpu.icache.demand_mshr_misses::total 1980224 # number of demand (read+write) MSHR misses 967system.cpu.icache.overall_mshr_misses::cpu.inst 1980224 # number of overall MSHR misses 968system.cpu.icache.overall_mshr_misses::total 1980224 # number of overall MSHR misses 969system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15180539440 # number of ReadReq MSHR miss cycles 970system.cpu.icache.ReadReq_mshr_miss_latency::total 15180539440 # number of ReadReq MSHR miss cycles 971system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15180539440 # number of demand (read+write) MSHR miss cycles 972system.cpu.icache.demand_mshr_miss_latency::total 15180539440 # number of demand (read+write) MSHR miss cycles 973system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15180539440 # number of overall MSHR miss cycles 974system.cpu.icache.overall_mshr_miss_latency::total 15180539440 # number of overall MSHR miss cycles |
| 962system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses 963system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses 964system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses 965system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses 966system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses 967system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses | 975system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses 976system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses 977system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses 978system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses 979system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses 980system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses |
| 968system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7650.250600 # average ReadReq mshr miss latency 969system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7650.250600 # average ReadReq mshr miss latency 970system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7650.250600 # average overall mshr miss latency 971system.cpu.icache.demand_avg_mshr_miss_latency::total 7650.250600 # average overall mshr miss latency 972system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7650.250600 # average overall mshr miss latency 973system.cpu.icache.overall_avg_mshr_miss_latency::total 7650.250600 # average overall mshr miss latency 974system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 975system.cpu.l2cache.prefetcher.num_hwpf_issued 1350340 # number of hwpf issued 976system.cpu.l2cache.prefetcher.pfIdentified 1355050 # number of prefetch candidates identified 977system.cpu.l2cache.prefetcher.pfBufferHit 4121 # number of redundant prefetches already in prefetch queue | 981system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.071838 # average ReadReq mshr miss latency 982system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.071838 # average ReadReq mshr miss latency 983system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency 984system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency 985system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency 986system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency 987system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 988system.cpu.l2cache.prefetcher.num_hwpf_issued 1350153 # number of hwpf issued 989system.cpu.l2cache.prefetcher.pfIdentified 1355017 # number of prefetch candidates identified 990system.cpu.l2cache.prefetcher.pfBufferHit 4256 # number of redundant prefetches already in prefetch queue |
| 978system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 979system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 991system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 992system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 980system.cpu.l2cache.prefetcher.pfSpanPage 4790102 # number of prefetches not generated due to page crossing 981system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 982system.cpu.l2cache.tags.replacements 297234 # number of replacements 983system.cpu.l2cache.tags.tagsinuse 16098.063865 # Cycle average of tags in use 984system.cpu.l2cache.tags.total_refs 3815891 # Total number of references to valid blocks. 985system.cpu.l2cache.tags.sampled_refs 313429 # Sample count of references to valid blocks. 986system.cpu.l2cache.tags.avg_refs 12.174658 # Average number of references to valid blocks. | 993system.cpu.l2cache.prefetcher.pfSpanPage 4789879 # number of prefetches not generated due to page crossing 994system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 995system.cpu.l2cache.tags.replacements 297323 # number of replacements 996system.cpu.l2cache.tags.tagsinuse 16097.800949 # Cycle average of tags in use 997system.cpu.l2cache.tags.total_refs 3937547 # Total number of references to valid blocks. 998system.cpu.l2cache.tags.sampled_refs 313525 # Sample count of references to valid blocks. 999system.cpu.l2cache.tags.avg_refs 12.558957 # Average number of references to valid blocks. |
| 987system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1000system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 988system.cpu.l2cache.tags.occ_blocks::writebacks 15670.505298 # Average occupied blocks per requestor 989system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 427.558566 # Average occupied blocks per requestor 990system.cpu.l2cache.tags.occ_percent::writebacks 0.956452 # Average percentage of cache occupancy 991system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.026096 # Average percentage of cache occupancy 992system.cpu.l2cache.tags.occ_percent::total 0.982548 # Average percentage of cache occupancy 993system.cpu.l2cache.tags.occ_task_id_blocks::1022 418 # Occupied blocks per task id 994system.cpu.l2cache.tags.occ_task_id_blocks::1024 15777 # Occupied blocks per task id | 1001system.cpu.l2cache.tags.occ_blocks::writebacks 15677.943381 # Average occupied blocks per requestor 1002system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 419.857568 # Average occupied blocks per requestor 1003system.cpu.l2cache.tags.occ_percent::writebacks 0.956906 # Average percentage of cache occupancy 1004system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025626 # Average percentage of cache occupancy 1005system.cpu.l2cache.tags.occ_percent::total 0.982532 # Average percentage of cache occupancy 1006system.cpu.l2cache.tags.occ_task_id_blocks::1022 424 # Occupied blocks per task id 1007system.cpu.l2cache.tags.occ_task_id_blocks::1024 15778 # Occupied blocks per task id |
| 995system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id | 1008system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id |
| 996system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id 997system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id 998system.cpu.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id 999system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 1000system.cpu.l2cache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id 1001system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1577 # Occupied blocks per task id 1002system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3842 # Occupied blocks per task id 1003system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9849 # Occupied blocks per task id 1004system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025513 # Percentage of cache occupancy per task id 1005system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962952 # Percentage of cache occupancy per task id 1006system.cpu.l2cache.tags.tag_accesses 145585225 # Number of tag accesses 1007system.cpu.l2cache.tags.data_accesses 145585225 # Number of data accesses 1008system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 1009system.cpu.l2cache.WritebackDirty_hits::writebacks 735545 # number of WritebackDirty hits 1010system.cpu.l2cache.WritebackDirty_hits::total 735545 # number of WritebackDirty hits 1011system.cpu.l2cache.WritebackClean_hits::writebacks 3357840 # number of WritebackClean hits 1012system.cpu.l2cache.WritebackClean_hits::total 3357840 # number of WritebackClean hits 1013system.cpu.l2cache.ReadExReq_hits::cpu.data 718742 # number of ReadExReq hits 1014system.cpu.l2cache.ReadExReq_hits::total 718742 # number of ReadExReq hits 1015system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975871 # number of ReadCleanReq hits 1016system.cpu.l2cache.ReadCleanReq_hits::total 1975871 # number of ReadCleanReq hits 1017system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286733 # number of ReadSharedReq hits 1018system.cpu.l2cache.ReadSharedReq_hits::total 1286733 # number of ReadSharedReq hits 1019system.cpu.l2cache.demand_hits::cpu.inst 1975871 # number of demand (read+write) hits 1020system.cpu.l2cache.demand_hits::cpu.data 2005475 # number of demand (read+write) hits 1021system.cpu.l2cache.demand_hits::total 3981346 # number of demand (read+write) hits 1022system.cpu.l2cache.overall_hits::cpu.inst 1975871 # number of overall hits 1023system.cpu.l2cache.overall_hits::cpu.data 2005475 # number of overall hits 1024system.cpu.l2cache.overall_hits::total 3981346 # number of overall hits 1025system.cpu.l2cache.UpgradeReq_misses::cpu.data 174 # number of UpgradeReq misses 1026system.cpu.l2cache.UpgradeReq_misses::total 174 # number of UpgradeReq misses 1027system.cpu.l2cache.ReadExReq_misses::cpu.data 2104 # number of ReadExReq misses 1028system.cpu.l2cache.ReadExReq_misses::total 2104 # number of ReadExReq misses 1029system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4164 # number of ReadCleanReq misses 1030system.cpu.l2cache.ReadCleanReq_misses::total 4164 # number of ReadCleanReq misses 1031system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749391 # number of ReadSharedReq misses 1032system.cpu.l2cache.ReadSharedReq_misses::total 749391 # number of ReadSharedReq misses 1033system.cpu.l2cache.demand_misses::cpu.inst 4164 # number of demand (read+write) misses 1034system.cpu.l2cache.demand_misses::cpu.data 751495 # number of demand (read+write) misses 1035system.cpu.l2cache.demand_misses::total 755659 # number of demand (read+write) misses 1036system.cpu.l2cache.overall_misses::cpu.inst 4164 # number of overall misses 1037system.cpu.l2cache.overall_misses::cpu.data 751495 # number of overall misses 1038system.cpu.l2cache.overall_misses::total 755659 # number of overall misses 1039system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 179065000 # number of ReadExReq miss cycles 1040system.cpu.l2cache.ReadExReq_miss_latency::total 179065000 # number of ReadExReq miss cycles 1041system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 319741500 # number of ReadCleanReq miss cycles 1042system.cpu.l2cache.ReadCleanReq_miss_latency::total 319741500 # number of ReadCleanReq miss cycles 1043system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 52681851500 # number of ReadSharedReq miss cycles 1044system.cpu.l2cache.ReadSharedReq_miss_latency::total 52681851500 # number of ReadSharedReq miss cycles 1045system.cpu.l2cache.demand_miss_latency::cpu.inst 319741500 # number of demand (read+write) miss cycles 1046system.cpu.l2cache.demand_miss_latency::cpu.data 52860916500 # number of demand (read+write) miss cycles 1047system.cpu.l2cache.demand_miss_latency::total 53180658000 # number of demand (read+write) miss cycles 1048system.cpu.l2cache.overall_miss_latency::cpu.inst 319741500 # number of overall miss cycles 1049system.cpu.l2cache.overall_miss_latency::cpu.data 52860916500 # number of overall miss cycles 1050system.cpu.l2cache.overall_miss_latency::total 53180658000 # number of overall miss cycles 1051system.cpu.l2cache.WritebackDirty_accesses::writebacks 735545 # number of WritebackDirty accesses(hits+misses) 1052system.cpu.l2cache.WritebackDirty_accesses::total 735545 # number of WritebackDirty accesses(hits+misses) 1053system.cpu.l2cache.WritebackClean_accesses::writebacks 3357840 # number of WritebackClean accesses(hits+misses) 1054system.cpu.l2cache.WritebackClean_accesses::total 3357840 # number of WritebackClean accesses(hits+misses) 1055system.cpu.l2cache.UpgradeReq_accesses::cpu.data 174 # number of UpgradeReq accesses(hits+misses) 1056system.cpu.l2cache.UpgradeReq_accesses::total 174 # number of UpgradeReq accesses(hits+misses) | 1009system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id 1010system.cpu.l2cache.tags.age_task_id_blocks_1022::3 273 # Occupied blocks per task id 1011system.cpu.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id 1012system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 1013system.cpu.l2cache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id 1014system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id 1015system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3670 # Occupied blocks per task id 1016system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10056 # Occupied blocks per task id 1017system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025879 # Percentage of cache occupancy per task id 1018system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963013 # Percentage of cache occupancy per task id 1019system.cpu.l2cache.tags.tag_accesses 145579085 # Number of tag accesses 1020system.cpu.l2cache.tags.data_accesses 145579085 # Number of data accesses 1021system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 1022system.cpu.l2cache.WritebackDirty_hits::writebacks 735952 # number of WritebackDirty hits 1023system.cpu.l2cache.WritebackDirty_hits::total 735952 # number of WritebackDirty hits 1024system.cpu.l2cache.WritebackClean_hits::writebacks 3357075 # number of WritebackClean hits 1025system.cpu.l2cache.WritebackClean_hits::total 3357075 # number of WritebackClean hits 1026system.cpu.l2cache.ReadExReq_hits::cpu.data 718660 # number of ReadExReq hits 1027system.cpu.l2cache.ReadExReq_hits::total 718660 # number of ReadExReq hits 1028system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975820 # number of ReadCleanReq hits 1029system.cpu.l2cache.ReadCleanReq_hits::total 1975820 # number of ReadCleanReq hits 1030system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1285803 # number of ReadSharedReq hits 1031system.cpu.l2cache.ReadSharedReq_hits::total 1285803 # number of ReadSharedReq hits 1032system.cpu.l2cache.demand_hits::cpu.inst 1975820 # number of demand (read+write) hits 1033system.cpu.l2cache.demand_hits::cpu.data 2004463 # number of demand (read+write) hits 1034system.cpu.l2cache.demand_hits::total 3980283 # number of demand (read+write) hits 1035system.cpu.l2cache.overall_hits::cpu.inst 1975820 # number of overall hits 1036system.cpu.l2cache.overall_hits::cpu.data 2004463 # number of overall hits 1037system.cpu.l2cache.overall_hits::total 3980283 # number of overall hits 1038system.cpu.l2cache.UpgradeReq_misses::cpu.data 190 # number of UpgradeReq misses 1039system.cpu.l2cache.UpgradeReq_misses::total 190 # number of UpgradeReq misses 1040system.cpu.l2cache.ReadExReq_misses::cpu.data 2186 # number of ReadExReq misses 1041system.cpu.l2cache.ReadExReq_misses::total 2186 # number of ReadExReq misses 1042system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4215 # number of ReadCleanReq misses 1043system.cpu.l2cache.ReadCleanReq_misses::total 4215 # number of ReadCleanReq misses 1044system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750316 # number of ReadSharedReq misses 1045system.cpu.l2cache.ReadSharedReq_misses::total 750316 # number of ReadSharedReq misses 1046system.cpu.l2cache.demand_misses::cpu.inst 4215 # number of demand (read+write) misses 1047system.cpu.l2cache.demand_misses::cpu.data 752502 # number of demand (read+write) misses 1048system.cpu.l2cache.demand_misses::total 756717 # number of demand (read+write) misses 1049system.cpu.l2cache.overall_misses::cpu.inst 4215 # number of overall misses 1050system.cpu.l2cache.overall_misses::cpu.data 752502 # number of overall misses 1051system.cpu.l2cache.overall_misses::total 756717 # number of overall misses 1052system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 197785000 # number of ReadExReq miss cycles 1053system.cpu.l2cache.ReadExReq_miss_latency::total 197785000 # number of ReadExReq miss cycles 1054system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351484000 # number of ReadCleanReq miss cycles 1055system.cpu.l2cache.ReadCleanReq_miss_latency::total 351484000 # number of ReadCleanReq miss cycles 1056system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63803558500 # number of ReadSharedReq miss cycles 1057system.cpu.l2cache.ReadSharedReq_miss_latency::total 63803558500 # number of ReadSharedReq miss cycles 1058system.cpu.l2cache.demand_miss_latency::cpu.inst 351484000 # number of demand (read+write) miss cycles 1059system.cpu.l2cache.demand_miss_latency::cpu.data 64001343500 # number of demand (read+write) miss cycles 1060system.cpu.l2cache.demand_miss_latency::total 64352827500 # number of demand (read+write) miss cycles 1061system.cpu.l2cache.overall_miss_latency::cpu.inst 351484000 # number of overall miss cycles 1062system.cpu.l2cache.overall_miss_latency::cpu.data 64001343500 # number of overall miss cycles 1063system.cpu.l2cache.overall_miss_latency::total 64352827500 # number of overall miss cycles 1064system.cpu.l2cache.WritebackDirty_accesses::writebacks 735952 # number of WritebackDirty accesses(hits+misses) 1065system.cpu.l2cache.WritebackDirty_accesses::total 735952 # number of WritebackDirty accesses(hits+misses) 1066system.cpu.l2cache.WritebackClean_accesses::writebacks 3357075 # number of WritebackClean accesses(hits+misses) 1067system.cpu.l2cache.WritebackClean_accesses::total 3357075 # number of WritebackClean accesses(hits+misses) 1068system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190 # number of UpgradeReq accesses(hits+misses) 1069system.cpu.l2cache.UpgradeReq_accesses::total 190 # number of UpgradeReq accesses(hits+misses) |
| 1057system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) 1058system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) 1059system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980035 # number of ReadCleanReq accesses(hits+misses) 1060system.cpu.l2cache.ReadCleanReq_accesses::total 1980035 # number of ReadCleanReq accesses(hits+misses) | 1070system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) 1071system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) 1072system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980035 # number of ReadCleanReq accesses(hits+misses) 1073system.cpu.l2cache.ReadCleanReq_accesses::total 1980035 # number of ReadCleanReq accesses(hits+misses) |
| 1061system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036124 # number of ReadSharedReq accesses(hits+misses) 1062system.cpu.l2cache.ReadSharedReq_accesses::total 2036124 # number of ReadSharedReq accesses(hits+misses) | 1074system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses) 1075system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses) |
| 1063system.cpu.l2cache.demand_accesses::cpu.inst 1980035 # number of demand (read+write) accesses | 1076system.cpu.l2cache.demand_accesses::cpu.inst 1980035 # number of demand (read+write) accesses |
| 1064system.cpu.l2cache.demand_accesses::cpu.data 2756970 # number of demand (read+write) accesses 1065system.cpu.l2cache.demand_accesses::total 4737005 # number of demand (read+write) accesses | 1077system.cpu.l2cache.demand_accesses::cpu.data 2756965 # number of demand (read+write) accesses 1078system.cpu.l2cache.demand_accesses::total 4737000 # number of demand (read+write) accesses |
| 1066system.cpu.l2cache.overall_accesses::cpu.inst 1980035 # number of overall (read+write) accesses | 1079system.cpu.l2cache.overall_accesses::cpu.inst 1980035 # number of overall (read+write) accesses |
| 1067system.cpu.l2cache.overall_accesses::cpu.data 2756970 # number of overall (read+write) accesses 1068system.cpu.l2cache.overall_accesses::total 4737005 # number of overall (read+write) accesses | 1080system.cpu.l2cache.overall_accesses::cpu.data 2756965 # number of overall (read+write) accesses 1081system.cpu.l2cache.overall_accesses::total 4737000 # number of overall (read+write) accesses |
| 1069system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1070system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 1082system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1083system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1071system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002919 # miss rate for ReadExReq accesses 1072system.cpu.l2cache.ReadExReq_miss_rate::total 0.002919 # miss rate for ReadExReq accesses 1073system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002103 # miss rate for ReadCleanReq accesses 1074system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002103 # miss rate for ReadCleanReq accesses 1075system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368048 # miss rate for ReadSharedReq accesses 1076system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368048 # miss rate for ReadSharedReq accesses 1077system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002103 # miss rate for demand accesses 1078system.cpu.l2cache.demand_miss_rate::cpu.data 0.272580 # miss rate for demand accesses 1079system.cpu.l2cache.demand_miss_rate::total 0.159523 # miss rate for demand accesses 1080system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002103 # miss rate for overall accesses 1081system.cpu.l2cache.overall_miss_rate::cpu.data 0.272580 # miss rate for overall accesses 1082system.cpu.l2cache.overall_miss_rate::total 0.159523 # miss rate for overall accesses 1083system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85106.939163 # average ReadExReq miss latency 1084system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85106.939163 # average ReadExReq miss latency 1085system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76787.103746 # average ReadCleanReq miss latency 1086system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76787.103746 # average ReadCleanReq miss latency 1087system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70299.551903 # average ReadSharedReq miss latency 1088system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70299.551903 # average ReadSharedReq miss latency 1089system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76787.103746 # average overall miss latency 1090system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency 1091system.cpu.l2cache.demand_avg_miss_latency::total 70376.529625 # average overall miss latency 1092system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76787.103746 # average overall miss latency 1093system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency 1094system.cpu.l2cache.overall_avg_miss_latency::total 70376.529625 # average overall miss latency | 1084system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003033 # miss rate for ReadExReq accesses 1085system.cpu.l2cache.ReadExReq_miss_rate::total 0.003033 # miss rate for ReadExReq accesses 1086system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002129 # miss rate for ReadCleanReq accesses 1087system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002129 # miss rate for ReadCleanReq accesses 1088system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368503 # miss rate for ReadSharedReq accesses 1089system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368503 # miss rate for ReadSharedReq accesses 1090system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002129 # miss rate for demand accesses 1091system.cpu.l2cache.demand_miss_rate::cpu.data 0.272946 # miss rate for demand accesses 1092system.cpu.l2cache.demand_miss_rate::total 0.159746 # miss rate for demand accesses 1093system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002129 # miss rate for overall accesses 1094system.cpu.l2cache.overall_miss_rate::cpu.data 0.272946 # miss rate for overall accesses 1095system.cpu.l2cache.overall_miss_rate::total 0.159746 # miss rate for overall accesses 1096system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90478.042086 # average ReadExReq miss latency 1097system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90478.042086 # average ReadExReq miss latency 1098system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83388.849348 # average ReadCleanReq miss latency 1099system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83388.849348 # average ReadCleanReq miss latency 1100system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85035.583008 # average ReadSharedReq miss latency 1101system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85035.583008 # average ReadSharedReq miss latency 1102system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency 1103system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency 1104system.cpu.l2cache.demand_avg_miss_latency::total 85042.132660 # average overall miss latency 1105system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency 1106system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency 1107system.cpu.l2cache.overall_avg_miss_latency::total 85042.132660 # average overall miss latency |
| 1095system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1096system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1097system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1098system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1099system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1100system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1108system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1109system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1110system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1111system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1112system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1113system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1101system.cpu.l2cache.unused_prefetches 3678 # number of HardPF blocks evicted w/o reference 1102system.cpu.l2cache.writebacks::writebacks 66314 # number of writebacks 1103system.cpu.l2cache.writebacks::total 66314 # number of writebacks 1104system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 742 # number of ReadExReq MSHR hits 1105system.cpu.l2cache.ReadExReq_mshr_hits::total 742 # number of ReadExReq MSHR hits | 1114system.cpu.l2cache.unused_prefetches 3567 # number of HardPF blocks evicted w/o reference 1115system.cpu.l2cache.writebacks::writebacks 66339 # number of writebacks 1116system.cpu.l2cache.writebacks::total 66339 # number of writebacks 1117system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 799 # number of ReadExReq MSHR hits 1118system.cpu.l2cache.ReadExReq_mshr_hits::total 799 # number of ReadExReq MSHR hits |
| 1106system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1107system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits | 1119system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1120system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits |
| 1108system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 703 # number of ReadSharedReq MSHR hits 1109system.cpu.l2cache.ReadSharedReq_mshr_hits::total 703 # number of ReadSharedReq MSHR hits | 1121system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1026 # number of ReadSharedReq MSHR hits 1122system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1026 # number of ReadSharedReq MSHR hits |
| 1110system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits | 1123system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits |
| 1111system.cpu.l2cache.demand_mshr_hits::cpu.data 1445 # number of demand (read+write) MSHR hits 1112system.cpu.l2cache.demand_mshr_hits::total 1446 # number of demand (read+write) MSHR hits | 1124system.cpu.l2cache.demand_mshr_hits::cpu.data 1825 # number of demand (read+write) MSHR hits 1125system.cpu.l2cache.demand_mshr_hits::total 1826 # number of demand (read+write) MSHR hits |
| 1113system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits | 1126system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits |
| 1114system.cpu.l2cache.overall_mshr_hits::cpu.data 1445 # number of overall MSHR hits 1115system.cpu.l2cache.overall_mshr_hits::total 1446 # number of overall MSHR hits 1116system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202914 # number of HardPFReq MSHR misses 1117system.cpu.l2cache.HardPFReq_mshr_misses::total 202914 # number of HardPFReq MSHR misses 1118system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 174 # number of UpgradeReq MSHR misses 1119system.cpu.l2cache.UpgradeReq_mshr_misses::total 174 # number of UpgradeReq MSHR misses 1120system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1362 # number of ReadExReq MSHR misses 1121system.cpu.l2cache.ReadExReq_mshr_misses::total 1362 # number of ReadExReq MSHR misses 1122system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4163 # number of ReadCleanReq MSHR misses 1123system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4163 # number of ReadCleanReq MSHR misses 1124system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748688 # number of ReadSharedReq MSHR misses 1125system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748688 # number of ReadSharedReq MSHR misses 1126system.cpu.l2cache.demand_mshr_misses::cpu.inst 4163 # number of demand (read+write) MSHR misses 1127system.cpu.l2cache.demand_mshr_misses::cpu.data 750050 # number of demand (read+write) MSHR misses 1128system.cpu.l2cache.demand_mshr_misses::total 754213 # number of demand (read+write) MSHR misses 1129system.cpu.l2cache.overall_mshr_misses::cpu.inst 4163 # number of overall MSHR misses 1130system.cpu.l2cache.overall_mshr_misses::cpu.data 750050 # number of overall MSHR misses 1131system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202914 # number of overall MSHR misses 1132system.cpu.l2cache.overall_mshr_misses::total 957127 # number of overall MSHR misses 1133system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16536801285 # number of HardPFReq MSHR miss cycles 1134system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16536801285 # number of HardPFReq MSHR miss cycles 1135system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2630000 # number of UpgradeReq MSHR miss cycles 1136system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2630000 # number of UpgradeReq MSHR miss cycles 1137system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133214500 # number of ReadExReq MSHR miss cycles 1138system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133214500 # number of ReadExReq MSHR miss cycles 1139system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 294714000 # number of ReadCleanReq MSHR miss cycles 1140system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 294714000 # number of ReadCleanReq MSHR miss cycles 1141system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 48154340500 # number of ReadSharedReq MSHR miss cycles 1142system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 48154340500 # number of ReadSharedReq MSHR miss cycles 1143system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 294714000 # number of demand (read+write) MSHR miss cycles 1144system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 48287555000 # number of demand (read+write) MSHR miss cycles 1145system.cpu.l2cache.demand_mshr_miss_latency::total 48582269000 # number of demand (read+write) MSHR miss cycles 1146system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294714000 # number of overall MSHR miss cycles 1147system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48287555000 # number of overall MSHR miss cycles 1148system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16536801285 # number of overall MSHR miss cycles 1149system.cpu.l2cache.overall_mshr_miss_latency::total 65119070285 # number of overall MSHR miss cycles | 1127system.cpu.l2cache.overall_mshr_hits::cpu.data 1825 # number of overall MSHR hits 1128system.cpu.l2cache.overall_mshr_hits::total 1826 # number of overall MSHR hits 1129system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202675 # number of HardPFReq MSHR misses 1130system.cpu.l2cache.HardPFReq_mshr_misses::total 202675 # number of HardPFReq MSHR misses 1131system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 190 # number of UpgradeReq MSHR misses 1132system.cpu.l2cache.UpgradeReq_mshr_misses::total 190 # number of UpgradeReq MSHR misses 1133system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses 1134system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses 1135system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4214 # number of ReadCleanReq MSHR misses 1136system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4214 # number of ReadCleanReq MSHR misses 1137system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 749290 # number of ReadSharedReq MSHR misses 1138system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749290 # number of ReadSharedReq MSHR misses 1139system.cpu.l2cache.demand_mshr_misses::cpu.inst 4214 # number of demand (read+write) MSHR misses 1140system.cpu.l2cache.demand_mshr_misses::cpu.data 750677 # number of demand (read+write) MSHR misses 1141system.cpu.l2cache.demand_mshr_misses::total 754891 # number of demand (read+write) MSHR misses 1142system.cpu.l2cache.overall_mshr_misses::cpu.inst 4214 # number of overall MSHR misses 1143system.cpu.l2cache.overall_mshr_misses::cpu.data 750677 # number of overall MSHR misses 1144system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202675 # number of overall MSHR misses 1145system.cpu.l2cache.overall_mshr_misses::total 957566 # number of overall MSHR misses 1146system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of HardPFReq MSHR miss cycles 1147system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20310287954 # number of HardPFReq MSHR miss cycles 1148system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2871000 # number of UpgradeReq MSHR miss cycles 1149system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2871000 # number of UpgradeReq MSHR miss cycles 1150system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 146425000 # number of ReadExReq MSHR miss cycles 1151system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 146425000 # number of ReadExReq MSHR miss cycles 1152system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 326144500 # number of ReadCleanReq MSHR miss cycles 1153system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 326144500 # number of ReadCleanReq MSHR miss cycles 1154system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59240775500 # number of ReadSharedReq MSHR miss cycles 1155system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59240775500 # number of ReadSharedReq MSHR miss cycles 1156system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 326144500 # number of demand (read+write) MSHR miss cycles 1157system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59387200500 # number of demand (read+write) MSHR miss cycles 1158system.cpu.l2cache.demand_mshr_miss_latency::total 59713345000 # number of demand (read+write) MSHR miss cycles 1159system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 326144500 # number of overall MSHR miss cycles 1160system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59387200500 # number of overall MSHR miss cycles 1161system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of overall MSHR miss cycles 1162system.cpu.l2cache.overall_mshr_miss_latency::total 80023632954 # number of overall MSHR miss cycles |
| 1150system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1151system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1152system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1153system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 1163system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1164system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1165system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1166system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1154system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses 1155system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses 1156system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for ReadCleanReq accesses 1157system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002102 # mshr miss rate for ReadCleanReq accesses 1158system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367703 # mshr miss rate for ReadSharedReq accesses 1159system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367703 # mshr miss rate for ReadSharedReq accesses 1160system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for demand accesses 1161system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for demand accesses 1162system.cpu.l2cache.demand_mshr_miss_rate::total 0.159217 # mshr miss rate for demand accesses 1163system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for overall accesses 1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for overall accesses | 1167system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses 1168system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses 1169system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for ReadCleanReq accesses 1170system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002128 # mshr miss rate for ReadCleanReq accesses 1171system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367999 # mshr miss rate for ReadSharedReq accesses 1172system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367999 # mshr miss rate for ReadSharedReq accesses 1173system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for demand accesses 1174system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for demand accesses 1175system.cpu.l2cache.demand_mshr_miss_rate::total 0.159361 # mshr miss rate for demand accesses 1176system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for overall accesses 1177system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for overall accesses |
| 1165system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1178system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1166system.cpu.l2cache.overall_mshr_miss_rate::total 0.202053 # mshr miss rate for overall accesses 1167system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average HardPFReq mshr miss latency 1168system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 81496.600949 # average HardPFReq mshr miss latency 1169system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15114.942529 # average UpgradeReq mshr miss latency 1170system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15114.942529 # average UpgradeReq mshr miss latency 1171system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97808.002937 # average ReadExReq mshr miss latency 1172system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97808.002937 # average ReadExReq mshr miss latency 1173system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70793.658419 # average ReadCleanReq mshr miss latency 1174system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70793.658419 # average ReadCleanReq mshr miss latency 1175system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64318.301482 # average ReadSharedReq mshr miss latency 1176system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64318.301482 # average ReadSharedReq mshr miss latency 1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency 1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency 1179system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64414.520832 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency 1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency 1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average overall mshr miss latency 1183system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68035.976715 # average overall mshr miss latency 1184system.cpu.toL2Bus.snoop_filter.tot_requests 9473332 # Total number of requests made to the snoop filter. 1185system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736180 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1186system.cpu.toL2Bus.snoop_filter.hit_multi_requests 642769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1187system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. 1188system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1179system.cpu.l2cache.overall_mshr_miss_rate::total 0.202146 # mshr miss rate for overall accesses 1180system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average HardPFReq mshr miss latency 1181system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100211.116092 # average HardPFReq mshr miss latency 1182system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15110.526316 # average UpgradeReq mshr miss latency 1183system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15110.526316 # average UpgradeReq mshr miss latency 1184system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 105569.574621 # average ReadExReq mshr miss latency 1185system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 105569.574621 # average ReadExReq mshr miss latency 1186system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77395.467489 # average ReadCleanReq mshr miss latency 1187system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77395.467489 # average ReadCleanReq mshr miss latency 1188system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79062.546544 # average ReadSharedReq mshr miss latency 1189system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79062.546544 # average ReadSharedReq mshr miss latency 1190system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency 1191system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency 1192system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79101.943194 # average overall mshr miss latency 1193system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency 1194system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency 1195system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average overall mshr miss latency 1196system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83569.835347 # average overall mshr miss latency 1197system.cpu.toL2Bus.snoop_filter.tot_requests 9473354 # Total number of requests made to the snoop filter. 1198system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736191 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1199system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1200system.cpu.toL2Bus.snoop_filter.tot_snoops 89 # Total number of snoops made to the snoop filter. 1201system.cpu.toL2Bus.snoop_filter.hit_single_snoops 88 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1189system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1202system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1190system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 1191system.cpu.toL2Bus.trans_dist::ReadResp 4016330 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::WritebackDirty 801859 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::WritebackClean 4000435 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::CleanEvict 230920 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::HardPFReq 258553 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution | 1203system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 1204system.cpu.toL2Bus.trans_dist::ReadResp 4016341 # Transaction distribution 1205system.cpu.toL2Bus.trans_dist::WritebackDirty 802291 # Transaction distribution 1206system.cpu.toL2Bus.trans_dist::WritebackClean 4000023 # Transaction distribution 1207system.cpu.toL2Bus.trans_dist::CleanEvict 230984 # Transaction distribution 1208system.cpu.toL2Bus.trans_dist::HardPFReq 255300 # Transaction distribution 1209system.cpu.toL2Bus.trans_dist::UpgradeReq 190 # Transaction distribution 1210system.cpu.toL2Bus.trans_dist::UpgradeResp 190 # Transaction distribution |
| 1198system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution | 1211system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution 1212system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution |
| 1200system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980208 # Transaction distribution 1201system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036124 # Transaction distribution 1202system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939763 # Packet count per connected master and slave (bytes) 1203system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270746 # Packet count per connected master and slave (bytes) 1204system.cpu.toL2Bus.pkt_count::total 14210509 # Packet count per connected master and slave (bytes) | 1213system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980224 # Transaction distribution 1214system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution 1215system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939779 # Packet count per connected master and slave (bytes) 1216system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270763 # Packet count per connected master and slave (bytes) 1217system.cpu.toL2Bus.pkt_count::total 14210542 # Packet count per connected master and slave (bytes) |
| 1205system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) | 1218system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) |
| 1206system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859392 # Cumulative packet size per connected master and slave (bytes) 1207system.cpu.toL2Bus.pkt_size::total 606270912 # Cumulative packet size per connected master and slave (bytes) 1208system.cpu.toL2Bus.snoops 555960 # Total snoops (count) 1209system.cpu.toL2Bus.snoopTraffic 4255168 # Total snoop traffic (bytes) 1210system.cpu.toL2Bus.snoop_fanout::samples 5293139 # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::mean 0.121491 # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::stdev 0.326697 # Request fanout histogram | 1219system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858752 # Cumulative packet size per connected master and slave (bytes) 1220system.cpu.toL2Bus.pkt_size::total 606270272 # Cumulative packet size per connected master and slave (bytes) 1221system.cpu.toL2Bus.snoops 552812 # Total snoops (count) 1222system.cpu.toL2Bus.snoopTraffic 4257792 # Total snoop traffic (bytes) 1223system.cpu.toL2Bus.snoop_fanout::samples 5290002 # Request fanout histogram 1224system.cpu.toL2Bus.snoop_fanout::mean 0.121634 # Request fanout histogram 1225system.cpu.toL2Bus.snoop_fanout::stdev 0.326863 # Request fanout histogram |
| 1213system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1226system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1214system.cpu.toL2Bus.snoop_fanout::0 4650072 87.85% 87.85% # Request fanout histogram 1215system.cpu.toL2Bus.snoop_fanout::1 643066 12.15% 100.00% # Request fanout histogram | 1227system.cpu.toL2Bus.snoop_fanout::0 4646559 87.84% 87.84% # Request fanout histogram 1228system.cpu.toL2Bus.snoop_fanout::1 643442 12.16% 100.00% # Request fanout histogram |
| 1216system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1217system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1218system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1219system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1229system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1230system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1231system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1232system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1220system.cpu.toL2Bus.snoop_fanout::total 5293139 # Request fanout histogram 1221system.cpu.toL2Bus.reqLayer0.occupancy 9472646000 # Layer occupancy (ticks) 1222system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) 1223system.cpu.toL2Bus.respLayer0.occupancy 2970310996 # Layer occupancy (ticks) | 1233system.cpu.toL2Bus.snoop_fanout::total 5290002 # Request fanout histogram 1234system.cpu.toL2Bus.reqLayer0.occupancy 9472652000 # Layer occupancy (ticks) 1235system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) 1236system.cpu.toL2Bus.respLayer0.occupancy 2970335495 # Layer occupancy (ticks) |
| 1224system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) | 1237system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) |
| 1225system.cpu.toL2Bus.respLayer1.occupancy 4135552978 # Layer occupancy (ticks) 1226system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 1227system.membus.snoop_filter.tot_requests 1254437 # Total number of requests made to the snoop filter. 1228system.membus.snoop_filter.hit_single_requests 940010 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1238system.cpu.toL2Bus.respLayer1.occupancy 4135554975 # Layer occupancy (ticks) 1239system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 1240system.membus.snoop_filter.tot_requests 1254990 # Total number of requests made to the snoop filter. 1241system.membus.snoop_filter.hit_single_requests 940467 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1229system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1230system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1231system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1232system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1242system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1243system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1244system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1245system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1233system.membus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states 1234system.membus.trans_dist::ReadResp 955666 # Transaction distribution 1235system.membus.trans_dist::WritebackDirty 66314 # Transaction distribution 1236system.membus.trans_dist::CleanEvict 230920 # Transaction distribution 1237system.membus.trans_dist::UpgradeReq 174 # Transaction distribution 1238system.membus.trans_dist::ReadExReq 1362 # Transaction distribution 1239system.membus.trans_dist::ReadExResp 1362 # Transaction distribution 1240system.membus.trans_dist::ReadSharedReq 955667 # Transaction distribution 1241system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211465 # Packet count per connected master and slave (bytes) 1242system.membus.pkt_count::total 2211465 # Packet count per connected master and slave (bytes) 1243system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65493888 # Cumulative packet size per connected master and slave (bytes) 1244system.membus.pkt_size::total 65493888 # Cumulative packet size per connected master and slave (bytes) | 1246system.membus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states 1247system.membus.trans_dist::ReadResp 956088 # Transaction distribution 1248system.membus.trans_dist::WritebackDirty 66339 # Transaction distribution 1249system.membus.trans_dist::CleanEvict 230984 # Transaction distribution 1250system.membus.trans_dist::UpgradeReq 190 # Transaction distribution 1251system.membus.trans_dist::ReadExReq 1387 # Transaction distribution 1252system.membus.trans_dist::ReadExResp 1387 # Transaction distribution 1253system.membus.trans_dist::ReadSharedReq 956090 # Transaction distribution 1254system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2212465 # Packet count per connected master and slave (bytes) 1255system.membus.pkt_count::total 2212465 # Packet count per connected master and slave (bytes) 1256system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65524096 # Cumulative packet size per connected master and slave (bytes) 1257system.membus.pkt_size::total 65524096 # Cumulative packet size per connected master and slave (bytes) |
| 1245system.membus.snoops 0 # Total snoops (count) 1246system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1258system.membus.snoops 0 # Total snoops (count) 1259system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1247system.membus.snoop_fanout::samples 957203 # Request fanout histogram | 1260system.membus.snoop_fanout::samples 957667 # Request fanout histogram |
| 1248system.membus.snoop_fanout::mean 0 # Request fanout histogram 1249system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1250system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1261system.membus.snoop_fanout::mean 0 # Request fanout histogram 1262system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1263system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1251system.membus.snoop_fanout::0 957203 100.00% 100.00% # Request fanout histogram | 1264system.membus.snoop_fanout::0 957667 100.00% 100.00% # Request fanout histogram |
| 1252system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1253system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1254system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1255system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1265system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1266system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1267system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1268system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1256system.membus.snoop_fanout::total 957203 # Request fanout histogram 1257system.membus.reqLayer0.occupancy 1755655982 # Layer occupancy (ticks) | 1269system.membus.snoop_fanout::total 957667 # Request fanout histogram 1270system.membus.reqLayer0.occupancy 1758860478 # Layer occupancy (ticks) |
| 1258system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) | 1271system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) |
| 1259system.membus.respLayer1.occupancy 5035261795 # Layer occupancy (ticks) | 1272system.membus.respLayer1.occupancy 5031633569 # Layer occupancy (ticks) |
| 1260system.membus.respLayer1.utilization 1.5 # Layer utilization (%) 1261 1262---------- End Simulation Statistics ---------- | 1273system.membus.respLayer1.utilization 1.5 # Layer utilization (%) 1274 1275---------- End Simulation Statistics ---------- |