Cross Reference: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11456:c0fb4435b80f ) new ( 11502:e273e86a873d )

full compact

stats.txt (11456:c0fb4435b80f)	stats.txt (11502:e273e86a873d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.326731 # Number of seconds simulated 4sim_ticks 326731324000 # Number of ticks simulated 5final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 138534 # Simulator instruction rate (inst/s) 8host_op_rate 170554 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 70652444 # Simulator tick rate (ticks/s) 10host_mem_usage 277336 # Number of bytes of host memory used 11host_seconds 4624.49 # Real time elapsed on the host 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory 19system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 953240 # Number of read requests accepted 44system.physmem.writeReqs 66334 # Number of write requests accepted 45system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue 49system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 19685 # Per bank write bursts 56system.physmem.perBankRdBursts::1 19287 # Per bank write bursts 57system.physmem.perBankRdBursts::2 657567 # Per bank write bursts 58system.physmem.perBankRdBursts::3 20052 # Per bank write bursts 59system.physmem.perBankRdBursts::4 19480 # Per bank write bursts 60system.physmem.perBankRdBursts::5 20770 # Per bank write bursts 61system.physmem.perBankRdBursts::6 19386 # Per bank write bursts 62system.physmem.perBankRdBursts::7 19760 # Per bank write bursts 63system.physmem.perBankRdBursts::8 19321 # Per bank write bursts 64system.physmem.perBankRdBursts::9 19768 # Per bank write bursts 65system.physmem.perBankRdBursts::10 19303 # Per bank write bursts 66system.physmem.perBankRdBursts::11 19444 # Per bank write bursts 67system.physmem.perBankRdBursts::12 19433 # Per bank write bursts 68system.physmem.perBankRdBursts::13 20871 # Per bank write bursts 69system.physmem.perBankRdBursts::14 19269 # Per bank write bursts 70system.physmem.perBankRdBursts::15 19527 # Per bank write bursts 71system.physmem.perBankWrBursts::0 4288 # Per bank write bursts 72system.physmem.perBankWrBursts::1 4110 # Per bank write bursts 73system.physmem.perBankWrBursts::2 4140 # Per bank write bursts 74system.physmem.perBankWrBursts::3 4154 # Per bank write bursts 75system.physmem.perBankWrBursts::4 4242 # Per bank write bursts 76system.physmem.perBankWrBursts::5 4232 # Per bank write bursts 77system.physmem.perBankWrBursts::6 4174 # Per bank write bursts 78system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::8 4095 # Per bank write bursts 80system.physmem.perBankWrBursts::9 4095 # Per bank write bursts 81system.physmem.perBankWrBursts::10 4095 # Per bank write bursts 82system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 83system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 84system.physmem.perBankWrBursts::13 4095 # Per bank write bursts 85system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 86system.physmem.perBankWrBursts::15 4146 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 326731313500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 953240 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 66334 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes 229system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads 248system.physmem.totQLat 12733277648 # Total ticks spent queuing 249system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM 250system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers 251system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst 252system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 253system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst 254system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s 255system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s 256system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s 257system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s 258system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 259system.physmem.busUtil 1.56 # Data bus utilization in percentage 260system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads 261system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes 262system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing 263system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing 264system.physmem.readRowHits 805882 # Number of row buffer hits during reads 265system.physmem.writeRowHits 26140 # Number of row buffer hits during writes 266system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads 267system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes 268system.physmem.avgGap 320458.66 # Average gap between requests 269system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined 270system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ) 271system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ) 272system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ) 273system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ) 274system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) 275system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ) 276system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ) 277system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ) 278system.physmem_0.averagePower 771.975754 # Core power per rank (mW) 279system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states 280system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states 281system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 282system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states 283system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 284system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ) 285system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ) 286system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ) 287system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ) 288system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) 289system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ) 290system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ) 291system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ) 292system.physmem_1.averagePower 704.579541 # Core power per rank (mW) 293system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states 294system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states 295system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 296system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states 297system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 298system.cpu.branchPred.lookups 174663372 # Number of BP lookups 299system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted 300system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect 301system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups 302system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits 303system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 304system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage 305system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target. 306system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. 307system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups. 308system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits. 309system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. 310system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. 311system.cpu_clk_domain.clock 500 # Clock period in ticks 312system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 321system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 322system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 323system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 324system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 325system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 327system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 328system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 329system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 330system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 331system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 332system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 333system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 334system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 335system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 336system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 337system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 338system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 339system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 340system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 341system.cpu.dtb.walker.walks 0 # Table walker walks requested 342system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.inst_hits 0 # ITB inst hits 350system.cpu.dtb.inst_misses 0 # ITB inst misses 351system.cpu.dtb.read_hits 0 # DTB read hits 352system.cpu.dtb.read_misses 0 # DTB read misses 353system.cpu.dtb.write_hits 0 # DTB write hits 354system.cpu.dtb.write_misses 0 # DTB write misses 355system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 356system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 357system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 358system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 359system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 360system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 361system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 362system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 363system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 364system.cpu.dtb.read_accesses 0 # DTB read accesses 365system.cpu.dtb.write_accesses 0 # DTB write accesses 366system.cpu.dtb.inst_accesses 0 # ITB inst accesses 367system.cpu.dtb.hits 0 # DTB hits 368system.cpu.dtb.misses 0 # DTB misses 369system.cpu.dtb.accesses 0 # DTB accesses 370system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 379system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 380system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 381system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 382system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 383system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 384system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 385system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 386system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 387system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 388system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 389system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 390system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 391system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 392system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 394system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 395system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 396system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 397system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 398system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 399system.cpu.itb.walker.walks 0 # Table walker walks requested 400system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.inst_hits 0 # ITB inst hits 408system.cpu.itb.inst_misses 0 # ITB inst misses 409system.cpu.itb.read_hits 0 # DTB read hits 410system.cpu.itb.read_misses 0 # DTB read misses 411system.cpu.itb.write_hits 0 # DTB write hits 412system.cpu.itb.write_misses 0 # DTB write misses 413system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 414system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 415system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 416system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 417system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 418system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 419system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 420system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 421system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 422system.cpu.itb.read_accesses 0 # DTB read accesses 423system.cpu.itb.write_accesses 0 # DTB write accesses 424system.cpu.itb.inst_accesses 0 # ITB inst accesses 425system.cpu.itb.hits 0 # DTB hits 426system.cpu.itb.misses 0 # DTB misses 427system.cpu.itb.accesses 0 # DTB accesses 428system.cpu.workload.num_syscalls 673 # Number of system calls 429system.cpu.numCycles 653462649 # number of cpu cycles simulated 430system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 431system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 432system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss 433system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed 434system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered 435system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken 436system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked 437system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing 438system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 439system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps 440system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR 441system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched 442system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed 443system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle 456system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle 457system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle 458system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked 459system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running 460system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking 461system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing 462system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch 463system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction 464system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode 465system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode 466system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing 467system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle 468system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking 469system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst 470system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running 471system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking 472system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename 473system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename 474system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full 475system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full 476system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full 477system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full 478system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed 479system.cpu.rename.RenameLookups 4376071754 # Number of register rename lookups that rename has made 480system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups 481system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups 482system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed 483system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing 484system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed 485system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed 486system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer 487system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit. 488system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit. 489system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads. 490system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores. 491system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec) 492system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ 493system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued 494system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued 495system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling 496system.cpu.iq.iqSquashedOperandsExamined 248251839 # Number of squashed operands that are examined and possibly removed from graph 497system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed 498system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle 515system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 516system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available 517system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available 518system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.63% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.63% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.63% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.63% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.63% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.63% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdMult 0 0.00% 24.63% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.63% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdShift 0 0.00% 24.63% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.63% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.63% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.63% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available 545system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available 546system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available 547system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 548system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 549system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 550system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued 551system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued 552system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued 579system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued 580system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued 581system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 582system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 583system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued 584system.cpu.iq.rate 1.316105 # Inst issue rate 585system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested 586system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) 587system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads 588system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes 589system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses 590system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads 591system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes 592system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses 593system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses 594system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses 595system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores 596system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 597system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed 598system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed 599system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations 600system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed 601system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 602system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 603system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled 604system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked 605system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 606system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing 607system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking 608system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking 609system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ 610system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 611system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions 612system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions 613system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions 614system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall 615system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall 616system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations 617system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly 618system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly 619system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute 620system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions 621system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed 622system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute 623system.cpu.iew.exec_swp 0 # number of swp insts executed 624system.cpu.iew.exec_nop 10252 # number of nop insts executed 625system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed 626system.cpu.iew.exec_branches 143379422 # Number of branches executed 627system.cpu.iew.exec_stores 152688943 # Number of stores executed 628system.cpu.iew.exec_rate 1.301023 # Inst execution rate 629system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit 630system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back 631system.cpu.iew.wb_producers 487338276 # num instructions producing a value 632system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value 633system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle 634system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back 635system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit 636system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards 637system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted 638system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle 655system.cpu.commit.committedInsts 640654411 # Number of instructions committed 656system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed 657system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 658system.cpu.commit.refs 381221434 # Number of memory references committed 659system.cpu.commit.loads 252240938 # Number of loads committed 660system.cpu.commit.membars 5740 # Number of memory barriers committed 661system.cpu.commit.branches 137364860 # Number of branches committed 662system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. 663system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. 664system.cpu.commit.function_calls 19275340 # Number of function calls committed. 665system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 666system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction 667system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 668system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 669system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 670system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 671system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 695system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 696system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 697system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 698system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 699system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction 700system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached 701system.cpu.rob.rob_reads 1500478116 # The number of ROB reads 702system.cpu.rob.rob_writes 1798380886 # The number of ROB writes 703system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself 704system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling 705system.cpu.committedInsts 640649299 # Number of Instructions Simulated 706system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated 707system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction 708system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads 709system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle 710system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads 711system.cpu.int_regfile_reads 868460109 # number of integer regfile reads 712system.cpu.int_regfile_writes 500697086 # number of integer regfile writes 713system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads 714system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes 715system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads 716system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes 717system.cpu.misc_regfile_reads 632347857 # number of misc regfile reads 718system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes 719system.cpu.dcache.tags.replacements 2756452 # number of replacements 720system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use 721system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. 722system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks. 723system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks. 724system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit. 725system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor 726system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy 727system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy 728system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 729system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 730system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id 731system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id 732system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 733system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 734system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses 735system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses 736system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits 737system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits 738system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits 739system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits 740system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits 741system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits 742system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits 743system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits 744system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 745system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 746system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits 747system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits 748system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits 749system.cpu.dcache.overall_hits::total 371035352 # number of overall hits 750system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses 751system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses 752system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses 753system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses 754system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses 755system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses 756system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 757system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 758system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses 759system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses 760system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses 761system.cpu.dcache.overall_misses::total 3447085 # number of overall misses 762system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles 763system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles 764system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles 765system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles 766system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles 767system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles 768system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles 769system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles 770system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles 771system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles 772system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses) 773system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses) 774system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 775system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 776system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) 777system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) 778system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) 779system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) 780system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 781system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 782system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses 783system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses 784system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses 785system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses 786system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses 787system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses 788system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses 789system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses 790system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses 791system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses 792system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 793system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses 794system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses 795system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses 796system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses 797system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses 798system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency 799system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency 800system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency 801system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency 802system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency 803system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency 804system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency 805system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency 806system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency 807system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency 808system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 809system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked 810system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 811system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked 812system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 813system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked 814system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks 815system.cpu.dcache.writebacks::total 2756452 # number of writebacks 816system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits 817system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits 818system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits 819system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits 820system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 821system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 822system.cpu.dcache.demand_mshr_hits::cpu.data 689931 # number of demand (read+write) MSHR hits 823system.cpu.dcache.demand_mshr_hits::total 689931 # number of demand (read+write) MSHR hits 824system.cpu.dcache.overall_mshr_hits::cpu.data 689931 # number of overall MSHR hits 825system.cpu.dcache.overall_mshr_hits::total 689931 # number of overall MSHR hits 826system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035475 # number of ReadReq MSHR misses 827system.cpu.dcache.ReadReq_mshr_misses::total 2035475 # number of ReadReq MSHR misses 828system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721032 # number of WriteReq MSHR misses 829system.cpu.dcache.WriteReq_mshr_misses::total 721032 # number of WriteReq MSHR misses 830system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses 831system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses 832system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses 833system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses 834system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses 835system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses 836system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63009195000 # number of ReadReq MSHR miss cycles 837system.cpu.dcache.ReadReq_mshr_miss_latency::total 63009195000 # number of ReadReq MSHR miss cycles 838system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5955069850 # number of WriteReq MSHR miss cycles 839system.cpu.dcache.WriteReq_mshr_miss_latency::total 5955069850 # number of WriteReq MSHR miss cycles 840system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5660000 # number of SoftPFReq MSHR miss cycles 841system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5660000 # number of SoftPFReq MSHR miss cycles 842system.cpu.dcache.demand_mshr_miss_latency::cpu.data 68964264850 # number of demand (read+write) MSHR miss cycles 843system.cpu.dcache.demand_mshr_miss_latency::total 68964264850 # number of demand (read+write) MSHR miss cycles 844system.cpu.dcache.overall_mshr_miss_latency::cpu.data 68969924850 # number of overall MSHR miss cycles 845system.cpu.dcache.overall_mshr_miss_latency::total 68969924850 # number of overall MSHR miss cycles 846system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses 847system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses 848system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses 849system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses 850system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses 851system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses 852system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses 853system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses 854system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses 855system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses 856system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895 # average ReadReq mshr miss latency 857system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895 # average ReadReq mshr miss latency 858system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency 859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency 860system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency 861system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency 862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency 863system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency 864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency 865system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency 866system.cpu.icache.tags.replacements 1979880 # number of replacements 867system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use 868system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. 869system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks. 870system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks. 871system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit. 872system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor 873system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy 874system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy 875system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 876system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 877system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id 878system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 879system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id 880system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 881system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses 882system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses 883system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits 884system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits 885system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits 886system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits 887system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits 888system.cpu.icache.overall_hits::total 245759426 # number of overall hits 889system.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses 890system.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses 891system.cpu.icache.demand_misses::cpu.inst 1983591 # number of demand (read+write) misses 892system.cpu.icache.demand_misses::total 1983591 # number of demand (read+write) misses 893system.cpu.icache.overall_misses::cpu.inst 1983591 # number of overall misses 894system.cpu.icache.overall_misses::total 1983591 # number of overall misses 895system.cpu.icache.ReadReq_miss_latency::cpu.inst 16128682925 # number of ReadReq miss cycles 896system.cpu.icache.ReadReq_miss_latency::total 16128682925 # number of ReadReq miss cycles 897system.cpu.icache.demand_miss_latency::cpu.inst 16128682925 # number of demand (read+write) miss cycles 898system.cpu.icache.demand_miss_latency::total 16128682925 # number of demand (read+write) miss cycles 899system.cpu.icache.overall_miss_latency::cpu.inst 16128682925 # number of overall miss cycles 900system.cpu.icache.overall_miss_latency::total 16128682925 # number of overall miss cycles 901system.cpu.icache.ReadReq_accesses::cpu.inst 247743017 # number of ReadReq accesses(hits+misses) 902system.cpu.icache.ReadReq_accesses::total 247743017 # number of ReadReq accesses(hits+misses) 903system.cpu.icache.demand_accesses::cpu.inst 247743017 # number of demand (read+write) accesses 904system.cpu.icache.demand_accesses::total 247743017 # number of demand (read+write) accesses 905system.cpu.icache.overall_accesses::cpu.inst 247743017 # number of overall (read+write) accesses 906system.cpu.icache.overall_accesses::total 247743017 # number of overall (read+write) accesses 907system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008007 # miss rate for ReadReq accesses 908system.cpu.icache.ReadReq_miss_rate::total 0.008007 # miss rate for ReadReq accesses 909system.cpu.icache.demand_miss_rate::cpu.inst 0.008007 # miss rate for demand accesses 910system.cpu.icache.demand_miss_rate::total 0.008007 # miss rate for demand accesses 911system.cpu.icache.overall_miss_rate::cpu.inst 0.008007 # miss rate for overall accesses 912system.cpu.icache.overall_miss_rate::total 0.008007 # miss rate for overall accesses 913system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8131.052684 # average ReadReq miss latency 914system.cpu.icache.ReadReq_avg_miss_latency::total 8131.052684 # average ReadReq miss latency 915system.cpu.icache.demand_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency 916system.cpu.icache.demand_avg_miss_latency::total 8131.052684 # average overall miss latency 917system.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency 918system.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency 919system.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked 920system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked 921system.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked 922system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 923system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked 924system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked 925system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks 926system.cpu.icache.writebacks::total 1979880 # number of writebacks 927system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits 928system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits 929system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits 930system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits 931system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits 932system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits 933system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980577 # number of ReadReq MSHR misses 934system.cpu.icache.ReadReq_mshr_misses::total 1980577 # number of ReadReq MSHR misses 935system.cpu.icache.demand_mshr_misses::cpu.inst 1980577 # number of demand (read+write) MSHR misses 936system.cpu.icache.demand_mshr_misses::total 1980577 # number of demand (read+write) MSHR misses 937system.cpu.icache.overall_mshr_misses::cpu.inst 1980577 # number of overall MSHR misses 938system.cpu.icache.overall_mshr_misses::total 1980577 # number of overall MSHR misses 939system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15098139938 # number of ReadReq MSHR miss cycles 940system.cpu.icache.ReadReq_mshr_miss_latency::total 15098139938 # number of ReadReq MSHR miss cycles 941system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15098139938 # number of demand (read+write) MSHR miss cycles 942system.cpu.icache.demand_mshr_miss_latency::total 15098139938 # number of demand (read+write) MSHR miss cycles 943system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15098139938 # number of overall MSHR miss cycles 944system.cpu.icache.overall_mshr_miss_latency::total 15098139938 # number of overall MSHR miss cycles 945system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for ReadReq accesses 946system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007994 # mshr miss rate for ReadReq accesses 947system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for demand accesses 948system.cpu.icache.demand_mshr_miss_rate::total 0.007994 # mshr miss rate for demand accesses 949system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses 950system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses 951system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency 952system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency 953system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency 954system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency 955system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency 956system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency 957system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued 958system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified 959system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue 960system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 961system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 962system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing 963system.cpu.l2cache.tags.replacements 301370 # number of replacements 964system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use 965system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks. 966system.cpu.l2cache.tags.sampled_refs 317734 # Sample count of references to valid blocks. 967system.cpu.l2cache.tags.avg_refs 22.730041 # Average number of references to valid blocks. 968system.cpu.l2cache.tags.warmup_cycle 44242160500 # Cycle when the warmup percentage was hit. 969system.cpu.l2cache.tags.occ_blocks::writebacks 9843.702780 # Average occupied blocks per requestor 970system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6506.729901 # Average occupied blocks per requestor 971system.cpu.l2cache.tags.occ_percent::writebacks 0.600812 # Average percentage of cache occupancy 972system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397139 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_percent::total 0.997951 # Average percentage of cache occupancy 974system.cpu.l2cache.tags.occ_task_id_blocks::1022 6334 # Occupied blocks per task id 975system.cpu.l2cache.tags.occ_task_id_blocks::1024 10030 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1704 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4420 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id 983system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id 984system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id 985system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id 986system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id 987system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses 988system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses 989system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits 990system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits 991system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits 992system.cpu.l2cache.WritebackClean_hits::total 3356496 # number of WritebackClean hits 993system.cpu.l2cache.ReadExReq_hits::cpu.data 718501 # number of ReadExReq hits 994system.cpu.l2cache.ReadExReq_hits::total 718501 # number of ReadExReq hits 995system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976843 # number of ReadCleanReq hits 996system.cpu.l2cache.ReadCleanReq_hits::total 1976843 # number of ReadCleanReq hits 997system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1287256 # number of ReadSharedReq hits 998system.cpu.l2cache.ReadSharedReq_hits::total 1287256 # number of ReadSharedReq hits 999system.cpu.l2cache.demand_hits::cpu.inst 1976843 # number of demand (read+write) hits 1000system.cpu.l2cache.demand_hits::cpu.data 2005757 # number of demand (read+write) hits 1001system.cpu.l2cache.demand_hits::total 3982600 # number of demand (read+write) hits 1002system.cpu.l2cache.overall_hits::cpu.inst 1976843 # number of overall hits 1003system.cpu.l2cache.overall_hits::cpu.data 2005757 # number of overall hits 1004system.cpu.l2cache.overall_hits::total 3982600 # number of overall hits 1005system.cpu.l2cache.UpgradeReq_misses::cpu.data 185 # number of UpgradeReq misses 1006system.cpu.l2cache.UpgradeReq_misses::total 185 # number of UpgradeReq misses 1007system.cpu.l2cache.ReadExReq_misses::cpu.data 2346 # number of ReadExReq misses 1008system.cpu.l2cache.ReadExReq_misses::total 2346 # number of ReadExReq misses 1009system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3550 # number of ReadCleanReq misses 1010system.cpu.l2cache.ReadCleanReq_misses::total 3550 # number of ReadCleanReq misses 1011system.cpu.l2cache.ReadSharedReq_misses::cpu.data 748861 # number of ReadSharedReq misses 1012system.cpu.l2cache.ReadSharedReq_misses::total 748861 # number of ReadSharedReq misses 1013system.cpu.l2cache.demand_misses::cpu.inst 3550 # number of demand (read+write) misses 1014system.cpu.l2cache.demand_misses::cpu.data 751207 # number of demand (read+write) misses 1015system.cpu.l2cache.demand_misses::total 754757 # number of demand (read+write) misses 1016system.cpu.l2cache.overall_misses::cpu.inst 3550 # number of overall misses 1017system.cpu.l2cache.overall_misses::cpu.data 751207 # number of overall misses 1018system.cpu.l2cache.overall_misses::total 754757 # number of overall misses 1019system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195074000 # number of ReadExReq miss cycles 1020system.cpu.l2cache.ReadExReq_miss_latency::total 195074000 # number of ReadExReq miss cycles 1021system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261372000 # number of ReadCleanReq miss cycles 1022system.cpu.l2cache.ReadCleanReq_miss_latency::total 261372000 # number of ReadCleanReq miss cycles 1023system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 51585571000 # number of ReadSharedReq miss cycles 1024system.cpu.l2cache.ReadSharedReq_miss_latency::total 51585571000 # number of ReadSharedReq miss cycles 1025system.cpu.l2cache.demand_miss_latency::cpu.inst 261372000 # number of demand (read+write) miss cycles 1026system.cpu.l2cache.demand_miss_latency::cpu.data 51780645000 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.demand_miss_latency::total 52042017000 # number of demand (read+write) miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.inst 261372000 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.data 51780645000 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::total 52042017000 # number of overall miss cycles 1031system.cpu.l2cache.WritebackDirty_accesses::writebacks 736314 # number of WritebackDirty accesses(hits+misses) 1032system.cpu.l2cache.WritebackDirty_accesses::total 736314 # number of WritebackDirty accesses(hits+misses) 1033system.cpu.l2cache.WritebackClean_accesses::writebacks 3356496 # number of WritebackClean accesses(hits+misses) 1034system.cpu.l2cache.WritebackClean_accesses::total 3356496 # number of WritebackClean accesses(hits+misses) 1035system.cpu.l2cache.UpgradeReq_accesses::cpu.data 185 # number of UpgradeReq accesses(hits+misses) 1036system.cpu.l2cache.UpgradeReq_accesses::total 185 # number of UpgradeReq accesses(hits+misses) 1037system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) 1038system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) 1039system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980393 # number of ReadCleanReq accesses(hits+misses) 1040system.cpu.l2cache.ReadCleanReq_accesses::total 1980393 # number of ReadCleanReq accesses(hits+misses) 1041system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036117 # number of ReadSharedReq accesses(hits+misses) 1042system.cpu.l2cache.ReadSharedReq_accesses::total 2036117 # number of ReadSharedReq accesses(hits+misses) 1043system.cpu.l2cache.demand_accesses::cpu.inst 1980393 # number of demand (read+write) accesses 1044system.cpu.l2cache.demand_accesses::cpu.data 2756964 # number of demand (read+write) accesses 1045system.cpu.l2cache.demand_accesses::total 4737357 # number of demand (read+write) accesses 1046system.cpu.l2cache.overall_accesses::cpu.inst 1980393 # number of overall (read+write) accesses 1047system.cpu.l2cache.overall_accesses::cpu.data 2756964 # number of overall (read+write) accesses 1048system.cpu.l2cache.overall_accesses::total 4737357 # number of overall (read+write) accesses 1049system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1050system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1051system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003255 # miss rate for ReadExReq accesses 1052system.cpu.l2cache.ReadExReq_miss_rate::total 0.003255 # miss rate for ReadExReq accesses 1053system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.001793 # miss rate for ReadCleanReq accesses 1054system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.001793 # miss rate for ReadCleanReq accesses 1055system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.367789 # miss rate for ReadSharedReq accesses 1056system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.367789 # miss rate for ReadSharedReq accesses 1057system.cpu.l2cache.demand_miss_rate::cpu.inst 0.001793 # miss rate for demand accesses 1058system.cpu.l2cache.demand_miss_rate::cpu.data 0.272476 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::total 0.159320 # miss rate for demand accesses 1060system.cpu.l2cache.overall_miss_rate::cpu.inst 0.001793 # miss rate for overall accesses 1061system.cpu.l2cache.overall_miss_rate::cpu.data 0.272476 # miss rate for overall accesses 1062system.cpu.l2cache.overall_miss_rate::total 0.159320 # miss rate for overall accesses 1063system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83151.747656 # average ReadExReq miss latency 1064system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83151.747656 # average ReadExReq miss latency 1065system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73625.915493 # average ReadCleanReq miss latency 1066system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73625.915493 # average ReadCleanReq miss latency 1067system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68885.375257 # average ReadSharedReq miss latency 1068system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68885.375257 # average ReadSharedReq miss latency 1069system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency 1070system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency 1071system.cpu.l2cache.demand_avg_miss_latency::total 68952.016344 # average overall miss latency 1072system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency 1073system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency 1074system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344 # average overall miss latency 1075system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1076system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1077system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1078system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1079system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1080system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1081system.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference 1082system.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks 1083system.cpu.l2cache.writebacks::total 66334 # number of writebacks 1084system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 963 # number of ReadExReq MSHR hits 1085system.cpu.l2cache.ReadExReq_mshr_hits::total 963 # number of ReadExReq MSHR hits 1086system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1087system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1088system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 903 # number of ReadSharedReq MSHR hits 1089system.cpu.l2cache.ReadSharedReq_mshr_hits::total 903 # number of ReadSharedReq MSHR hits 1090system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1091system.cpu.l2cache.demand_mshr_hits::cpu.data 1866 # number of demand (read+write) MSHR hits 1092system.cpu.l2cache.demand_mshr_hits::total 1867 # number of demand (read+write) MSHR hits 1093system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1094system.cpu.l2cache.overall_mshr_hits::cpu.data 1866 # number of overall MSHR hits 1095system.cpu.l2cache.overall_mshr_hits::total 1867 # number of overall MSHR hits 1096system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200438 # number of HardPFReq MSHR misses 1097system.cpu.l2cache.HardPFReq_mshr_misses::total 200438 # number of HardPFReq MSHR misses 1098system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 185 # number of UpgradeReq MSHR misses 1099system.cpu.l2cache.UpgradeReq_mshr_misses::total 185 # number of UpgradeReq MSHR misses 1100system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1383 # number of ReadExReq MSHR misses 1101system.cpu.l2cache.ReadExReq_mshr_misses::total 1383 # number of ReadExReq MSHR misses 1102system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3549 # number of ReadCleanReq MSHR misses 1103system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3549 # number of ReadCleanReq MSHR misses 1104system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 747958 # number of ReadSharedReq MSHR misses 1105system.cpu.l2cache.ReadSharedReq_mshr_misses::total 747958 # number of ReadSharedReq MSHR misses 1106system.cpu.l2cache.demand_mshr_misses::cpu.inst 3549 # number of demand (read+write) MSHR misses 1107system.cpu.l2cache.demand_mshr_misses::cpu.data 749341 # number of demand (read+write) MSHR misses 1108system.cpu.l2cache.demand_mshr_misses::total 752890 # number of demand (read+write) MSHR misses 1109system.cpu.l2cache.overall_mshr_misses::cpu.inst 3549 # number of overall MSHR misses 1110system.cpu.l2cache.overall_mshr_misses::cpu.data 749341 # number of overall MSHR misses 1111system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200438 # number of overall MSHR misses 1112system.cpu.l2cache.overall_mshr_misses::total 953328 # number of overall MSHR misses 1113system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of HardPFReq MSHR miss cycles 1114system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16667426112 # number of HardPFReq MSHR miss cycles 1115system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2605000 # number of UpgradeReq MSHR miss cycles 1116system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2605000 # number of UpgradeReq MSHR miss cycles 1117system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 137246500 # number of ReadExReq MSHR miss cycles 1118system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 137246500 # number of ReadExReq MSHR miss cycles 1119system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240029500 # number of ReadCleanReq MSHR miss cycles 1120system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240029500 # number of ReadCleanReq MSHR miss cycles 1121system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 47054888500 # number of ReadSharedReq MSHR miss cycles 1122system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 47054888500 # number of ReadSharedReq MSHR miss cycles 1123system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240029500 # number of demand (read+write) MSHR miss cycles 1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47192135000 # number of demand (read+write) MSHR miss cycles 1125system.cpu.l2cache.demand_mshr_miss_latency::total 47432164500 # number of demand (read+write) MSHR miss cycles 1126system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240029500 # number of overall MSHR miss cycles 1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47192135000 # number of overall MSHR miss cycles 1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of overall MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::total 64099590612 # number of overall MSHR miss cycles 1130system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1131system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1132system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1133system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses 1135system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses 1136system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses 1137system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses 1138system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses 1139system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses 1140system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses 1141system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses 1143system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses 1144system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses 1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses 1147system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency 1148system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency 1149system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency 1150system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency 1151system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency 1152system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency 1153system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency 1154system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency 1155system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency 1156system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency 1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency 1160system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency 1161system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency 1164system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. 1165system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1166system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1167system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. 1168system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1169system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1170system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution 1172system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution 1181system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes) 1182system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes) 1183system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes) 1184system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes) 1185system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes) 1186system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes) 1187system.cpu.toL2Bus.snoops 1296784 # Total snoops (count) 1188system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram 1189system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram 1190system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram 1191system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1192system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram 1193system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram 1195system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1196system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1198system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram 1199system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks) 1200system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) 1201system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks) 1202system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) 1203system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) 1204system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 1205system.membus.trans_dist::ReadResp 951856 # Transaction distribution 1206system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution 1207system.membus.trans_dist::CleanEvict 227102 # Transaction distribution 1208system.membus.trans_dist::UpgradeReq 185 # Transaction distribution 1209system.membus.trans_dist::ReadExReq 1383 # Transaction distribution 1210system.membus.trans_dist::ReadExResp 1383 # Transaction distribution 1211system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution 1212system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes) 1213system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes) 1214system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes) 1215system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes) 1216system.membus.snoops 0 # Total snoops (count) 1217system.membus.snoop_fanout::samples 1246861 # Request fanout histogram 1218system.membus.snoop_fanout::mean 0 # Request fanout histogram 1219system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1220system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1221system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram 1222system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1223system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1224system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1225system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1226system.membus.snoop_fanout::total 1246861 # Request fanout histogram 1227system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks) 1228system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 1229system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks) 1230system.membus.respLayer1.utilization 1.5 # Layer utilization (%) 1231 1232---------- End Simulation Statistics ----------

stats.txt (11456:c0fb4435b80f)

stats.txt (11502:e273e86a873d)

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.326731 # Number of seconds simulated
4sim_ticks 326731324000 # Number of ticks simulated
5final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 138534 # Simulator instruction rate (inst/s)
8host_op_rate 170554 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 70652444 # Simulator tick rate (ticks/s)
10host_mem_usage 277336 # Number of bytes of host memory used
11host_seconds 4624.49 # Real time elapsed on the host
12sim_insts 640649299 # Number of instructions simulated
13sim_ops 788724958 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory
19system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory
23system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 953240 # Number of read requests accepted
44system.physmem.writeReqs 66334 # Number of write requests accepted
45system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue
49system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 19685 # Per bank write bursts
56system.physmem.perBankRdBursts::1 19287 # Per bank write bursts
57system.physmem.perBankRdBursts::2 657567 # Per bank write bursts
58system.physmem.perBankRdBursts::3 20052 # Per bank write bursts
59system.physmem.perBankRdBursts::4 19480 # Per bank write bursts
60system.physmem.perBankRdBursts::5 20770 # Per bank write bursts
61system.physmem.perBankRdBursts::6 19386 # Per bank write bursts
62system.physmem.perBankRdBursts::7 19760 # Per bank write bursts
63system.physmem.perBankRdBursts::8 19321 # Per bank write bursts
64system.physmem.perBankRdBursts::9 19768 # Per bank write bursts
65system.physmem.perBankRdBursts::10 19303 # Per bank write bursts
66system.physmem.perBankRdBursts::11 19444 # Per bank write bursts
67system.physmem.perBankRdBursts::12 19433 # Per bank write bursts
68system.physmem.perBankRdBursts::13 20871 # Per bank write bursts
69system.physmem.perBankRdBursts::14 19269 # Per bank write bursts
70system.physmem.perBankRdBursts::15 19527 # Per bank write bursts
71system.physmem.perBankWrBursts::0 4288 # Per bank write bursts
72system.physmem.perBankWrBursts::1 4110 # Per bank write bursts
73system.physmem.perBankWrBursts::2 4140 # Per bank write bursts
74system.physmem.perBankWrBursts::3 4154 # Per bank write bursts
75system.physmem.perBankWrBursts::4 4242 # Per bank write bursts
76system.physmem.perBankWrBursts::5 4232 # Per bank write bursts
77system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
78system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
79system.physmem.perBankWrBursts::8 4095 # Per bank write bursts
80system.physmem.perBankWrBursts::9 4095 # Per bank write bursts
81system.physmem.perBankWrBursts::10 4095 # Per bank write bursts
82system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
83system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
84system.physmem.perBankWrBursts::13 4095 # Per bank write bursts
85system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
86system.physmem.perBankWrBursts::15 4146 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89system.physmem.totGap 326731313500 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 953240 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 66334 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes
222system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes
229system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads
248system.physmem.totQLat 12733277648 # Total ticks spent queuing
249system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM
250system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers
251system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst
252system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
253system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst
254system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s
255system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s
256system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s
257system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s
258system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
259system.physmem.busUtil 1.56 # Data bus utilization in percentage
260system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads
261system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes
262system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
263system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing
264system.physmem.readRowHits 805882 # Number of row buffer hits during reads
265system.physmem.writeRowHits 26140 # Number of row buffer hits during writes
266system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads
267system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes
268system.physmem.avgGap 320458.66 # Average gap between requests
269system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined
270system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ)
271system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ)
272system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ)
273system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ)
274system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ)
275system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ)
276system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ)
277system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ)
278system.physmem_0.averagePower 771.975754 # Core power per rank (mW)
279system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states
280system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states
281system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
282system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states
283system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
284system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ)
285system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ)
286system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ)
287system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ)
288system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ)
289system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ)
290system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ)
291system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ)
292system.physmem_1.averagePower 704.579541 # Core power per rank (mW)
293system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states
294system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states
295system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
296system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states
297system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
298system.cpu.branchPred.lookups 174663372 # Number of BP lookups
299system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted
300system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect
301system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups
302system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits
303system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
304system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage
305system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target.
306system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions.
307system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups.
308system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits.
309system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses.
310system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches.
311system.cpu_clk_domain.clock 500 # Clock period in ticks
312system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
320system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
321system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
322system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
323system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
324system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
325system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
327system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
328system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
329system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
330system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
331system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
332system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
333system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
334system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
335system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
336system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
337system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
338system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
339system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
340system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
341system.cpu.dtb.walker.walks 0 # Table walker walks requested
342system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
343system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
344system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
345system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
346system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
347system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
348system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
349system.cpu.dtb.inst_hits 0 # ITB inst hits
350system.cpu.dtb.inst_misses 0 # ITB inst misses
351system.cpu.dtb.read_hits 0 # DTB read hits
352system.cpu.dtb.read_misses 0 # DTB read misses
353system.cpu.dtb.write_hits 0 # DTB write hits
354system.cpu.dtb.write_misses 0 # DTB write misses
355system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
356system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
357system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
358system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
359system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
360system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
361system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
362system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
363system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
364system.cpu.dtb.read_accesses 0 # DTB read accesses
365system.cpu.dtb.write_accesses 0 # DTB write accesses
366system.cpu.dtb.inst_accesses 0 # ITB inst accesses
367system.cpu.dtb.hits 0 # DTB hits
368system.cpu.dtb.misses 0 # DTB misses
369system.cpu.dtb.accesses 0 # DTB accesses
370system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
378system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
379system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
380system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
381system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
382system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
383system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
384system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
385system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
386system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
387system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
388system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
389system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
390system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
391system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
392system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
393system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
394system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
395system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
396system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
397system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
398system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
399system.cpu.itb.walker.walks 0 # Table walker walks requested
400system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
401system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
402system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
403system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
404system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
405system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
406system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
407system.cpu.itb.inst_hits 0 # ITB inst hits
408system.cpu.itb.inst_misses 0 # ITB inst misses
409system.cpu.itb.read_hits 0 # DTB read hits
410system.cpu.itb.read_misses 0 # DTB read misses
411system.cpu.itb.write_hits 0 # DTB write hits
412system.cpu.itb.write_misses 0 # DTB write misses
413system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
414system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
415system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
416system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
417system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
418system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
419system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
420system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
421system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
422system.cpu.itb.read_accesses 0 # DTB read accesses
423system.cpu.itb.write_accesses 0 # DTB write accesses
424system.cpu.itb.inst_accesses 0 # ITB inst accesses
425system.cpu.itb.hits 0 # DTB hits
426system.cpu.itb.misses 0 # DTB misses
427system.cpu.itb.accesses 0 # DTB accesses
428system.cpu.workload.num_syscalls 673 # Number of system calls
429system.cpu.numCycles 653462649 # number of cpu cycles simulated
430system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
431system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
432system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss
433system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed
434system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered
435system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken
436system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked
437system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing
438system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
439system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps
440system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR
441system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched
442system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed
443system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total)
444system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total)
445system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total)
446system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
447system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total)
448system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total)
449system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total)
450system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total)
451system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
452system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
453system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
454system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total)
455system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle
456system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle
457system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle
458system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked
459system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running
460system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking
461system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing
462system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch
463system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction
464system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode
465system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode
466system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing
467system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle
468system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking
469system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst
470system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running
471system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking
472system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename
473system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename
474system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full
475system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full
476system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full
477system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full
478system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed
479system.cpu.rename.RenameLookups 4376071754 # Number of register rename lookups that rename has made
480system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups
481system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups
482system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
483system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing
484system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed
485system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed
486system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer
487system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit.
488system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit.
489system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads.
490system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores.
491system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec)
492system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ
493system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued
494system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued
495system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling
496system.cpu.iq.iqSquashedOperandsExamined 248251839 # Number of squashed operands that are examined and possibly removed from graph
497system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed
498system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle
499system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle
500system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle
501system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
502system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle
503system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle
504system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle
505system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle
506system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle
507system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle
508system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
509system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
510system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
511system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
512system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
513system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
514system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle
515system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
516system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available
517system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available
518system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available
519system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available
520system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available
521system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available
522system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available
523system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available
524system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available
525system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.63% # attempts to use FU when none available
526system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.63% # attempts to use FU when none available
527system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.63% # attempts to use FU when none available
528system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.63% # attempts to use FU when none available
529system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.63% # attempts to use FU when none available
530system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.63% # attempts to use FU when none available
531system.cpu.iq.fu_full::SimdMult 0 0.00% 24.63% # attempts to use FU when none available
532system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.63% # attempts to use FU when none available
533system.cpu.iq.fu_full::SimdShift 0 0.00% 24.63% # attempts to use FU when none available
534system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.63% # attempts to use FU when none available
535system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.63% # attempts to use FU when none available
536system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.63% # attempts to use FU when none available
537system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available
538system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available
539system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available
540system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available
541system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available
542system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available
543system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available
544system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available
545system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available
546system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available
547system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
548system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
549system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
550system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued
551system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued
552system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued
553system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued
554system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued
555system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued
556system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued
557system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued
558system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued
559system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued
560system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued
561system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued
562system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued
563system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued
564system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued
565system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued
566system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued
567system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued
568system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued
569system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued
570system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued
571system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
572system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued
573system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued
574system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued
575system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued
576system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued
577system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued
578system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued
579system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued
580system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued
581system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
582system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
583system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued
584system.cpu.iq.rate 1.316105 # Inst issue rate
585system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested
586system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst)
587system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads
588system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes
589system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses
590system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads
591system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes
592system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses
593system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses
594system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses
595system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores
596system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
597system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed
598system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed
599system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations
600system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed
601system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
602system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
603system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled
604system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked
605system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
606system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing
607system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking
608system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking
609system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ
610system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
611system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions
612system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions
613system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions
614system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall
615system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall
616system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations
617system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly
618system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly
619system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute
620system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions
621system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed
622system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute
623system.cpu.iew.exec_swp 0 # number of swp insts executed
624system.cpu.iew.exec_nop 10252 # number of nop insts executed
625system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed
626system.cpu.iew.exec_branches 143379422 # Number of branches executed
627system.cpu.iew.exec_stores 152688943 # Number of stores executed
628system.cpu.iew.exec_rate 1.301023 # Inst execution rate
629system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit
630system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back
631system.cpu.iew.wb_producers 487338276 # num instructions producing a value
632system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value
633system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle
634system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back
635system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit
636system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
637system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted
638system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle
639system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle
640system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle
641system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
642system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle
643system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle
644system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle
645system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle
646system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle
647system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle
648system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle
649system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle
650system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle
651system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
652system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
653system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
654system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle
655system.cpu.commit.committedInsts 640654411 # Number of instructions committed
656system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed
657system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
658system.cpu.commit.refs 381221434 # Number of memory references committed
659system.cpu.commit.loads 252240938 # Number of loads committed
660system.cpu.commit.membars 5740 # Number of memory barriers committed
661system.cpu.commit.branches 137364860 # Number of branches committed
662system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions.
663system.cpu.commit.int_insts 682251399 # Number of committed integer instructions.
664system.cpu.commit.function_calls 19275340 # Number of function calls committed.
665system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
666system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction
667system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
668system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
669system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
670system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
671system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
672system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
673system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
674system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
675system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
676system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
677system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
678system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
679system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
680system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
681system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
682system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
683system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
684system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
685system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
686system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
687system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
688system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
689system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
690system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
691system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
692system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
693system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
694system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
695system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction
696system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction
697system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
698system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
699system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction
700system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached
701system.cpu.rob.rob_reads 1500478116 # The number of ROB reads
702system.cpu.rob.rob_writes 1798380886 # The number of ROB writes
703system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself
704system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling
705system.cpu.committedInsts 640649299 # Number of Instructions Simulated
706system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated
707system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction
708system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads
709system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle
710system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads
711system.cpu.int_regfile_reads 868460109 # number of integer regfile reads
712system.cpu.int_regfile_writes 500697086 # number of integer regfile writes
713system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads
714system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes
715system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads
716system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes
717system.cpu.misc_regfile_reads 632347857 # number of misc regfile reads
718system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
719system.cpu.dcache.tags.replacements 2756452 # number of replacements
720system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use
721system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks.
722system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks.
723system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks.
724system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit.
725system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor
726system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy
727system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy
728system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
729system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
730system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
731system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id
732system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
733system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
734system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses
735system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses
736system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits
737system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits
738system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits
739system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits
740system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits
741system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits
742system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits
743system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits
744system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
745system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
746system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits
747system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits
748system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits
749system.cpu.dcache.overall_hits::total 371035352 # number of overall hits
750system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses
751system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses
752system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses
753system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses
754system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses
755system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses
756system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
757system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
758system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses
759system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses
760system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses
761system.cpu.dcache.overall_misses::total 3447085 # number of overall misses
762system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles
763system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles
764system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles
765system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles
766system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles
767system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles
768system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles
769system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles
770system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles
771system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles
772system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses)
773system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses)
774system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
775system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
776system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses)
777system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses)
778system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses)
779system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses)
780system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
781system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
782system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses
783system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses
784system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses
785system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses
786system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses
787system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses
788system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses
789system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses
790system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses
791system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses
792system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses
793system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses
794system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses
795system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses
796system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses
797system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses
798system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency
799system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency
800system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency
801system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency
802system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency
803system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency
804system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency
805system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency
806system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency
807system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency
808system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
809system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked
810system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
811system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked
812system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
813system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked
814system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks
815system.cpu.dcache.writebacks::total 2756452 # number of writebacks
816system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits
817system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits
818system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits
819system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits
820system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
821system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
822system.cpu.dcache.demand_mshr_hits::cpu.data 689931 # number of demand (read+write) MSHR hits
823system.cpu.dcache.demand_mshr_hits::total 689931 # number of demand (read+write) MSHR hits
824system.cpu.dcache.overall_mshr_hits::cpu.data 689931 # number of overall MSHR hits
825system.cpu.dcache.overall_mshr_hits::total 689931 # number of overall MSHR hits
826system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035475 # number of ReadReq MSHR misses
827system.cpu.dcache.ReadReq_mshr_misses::total 2035475 # number of ReadReq MSHR misses
828system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721032 # number of WriteReq MSHR misses
829system.cpu.dcache.WriteReq_mshr_misses::total 721032 # number of WriteReq MSHR misses
830system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses
831system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses
832system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses
833system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses
834system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses
835system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses
836system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63009195000 # number of ReadReq MSHR miss cycles
837system.cpu.dcache.ReadReq_mshr_miss_latency::total 63009195000 # number of ReadReq MSHR miss cycles
838system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5955069850 # number of WriteReq MSHR miss cycles
839system.cpu.dcache.WriteReq_mshr_miss_latency::total 5955069850 # number of WriteReq MSHR miss cycles
840system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5660000 # number of SoftPFReq MSHR miss cycles
841system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5660000 # number of SoftPFReq MSHR miss cycles
842system.cpu.dcache.demand_mshr_miss_latency::cpu.data 68964264850 # number of demand (read+write) MSHR miss cycles
843system.cpu.dcache.demand_mshr_miss_latency::total 68964264850 # number of demand (read+write) MSHR miss cycles
844system.cpu.dcache.overall_mshr_miss_latency::cpu.data 68969924850 # number of overall MSHR miss cycles
845system.cpu.dcache.overall_mshr_miss_latency::total 68969924850 # number of overall MSHR miss cycles
846system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses
847system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses
848system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses
849system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses
850system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses
851system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses
852system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses
853system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses
854system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses
855system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses
856system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895 # average ReadReq mshr miss latency
857system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895 # average ReadReq mshr miss latency
858system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency
859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency
860system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency
861system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency
862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency
863system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency
864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency
865system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency
866system.cpu.icache.tags.replacements 1979880 # number of replacements
867system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use
868system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks.
869system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks.
870system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks.
871system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit.
872system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor
873system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy
874system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy
875system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
876system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
877system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
878system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
879system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id
880system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
881system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses
882system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses
883system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits
884system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits
885system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits
886system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits
887system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits
888system.cpu.icache.overall_hits::total 245759426 # number of overall hits
889system.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses
890system.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses
891system.cpu.icache.demand_misses::cpu.inst 1983591 # number of demand (read+write) misses
892system.cpu.icache.demand_misses::total 1983591 # number of demand (read+write) misses
893system.cpu.icache.overall_misses::cpu.inst 1983591 # number of overall misses
894system.cpu.icache.overall_misses::total 1983591 # number of overall misses
895system.cpu.icache.ReadReq_miss_latency::cpu.inst 16128682925 # number of ReadReq miss cycles
896system.cpu.icache.ReadReq_miss_latency::total 16128682925 # number of ReadReq miss cycles
897system.cpu.icache.demand_miss_latency::cpu.inst 16128682925 # number of demand (read+write) miss cycles
898system.cpu.icache.demand_miss_latency::total 16128682925 # number of demand (read+write) miss cycles
899system.cpu.icache.overall_miss_latency::cpu.inst 16128682925 # number of overall miss cycles
900system.cpu.icache.overall_miss_latency::total 16128682925 # number of overall miss cycles
901system.cpu.icache.ReadReq_accesses::cpu.inst 247743017 # number of ReadReq accesses(hits+misses)
902system.cpu.icache.ReadReq_accesses::total 247743017 # number of ReadReq accesses(hits+misses)
903system.cpu.icache.demand_accesses::cpu.inst 247743017 # number of demand (read+write) accesses
904system.cpu.icache.demand_accesses::total 247743017 # number of demand (read+write) accesses
905system.cpu.icache.overall_accesses::cpu.inst 247743017 # number of overall (read+write) accesses
906system.cpu.icache.overall_accesses::total 247743017 # number of overall (read+write) accesses
907system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008007 # miss rate for ReadReq accesses
908system.cpu.icache.ReadReq_miss_rate::total 0.008007 # miss rate for ReadReq accesses
909system.cpu.icache.demand_miss_rate::cpu.inst 0.008007 # miss rate for demand accesses
910system.cpu.icache.demand_miss_rate::total 0.008007 # miss rate for demand accesses
911system.cpu.icache.overall_miss_rate::cpu.inst 0.008007 # miss rate for overall accesses
912system.cpu.icache.overall_miss_rate::total 0.008007 # miss rate for overall accesses
913system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8131.052684 # average ReadReq miss latency
914system.cpu.icache.ReadReq_avg_miss_latency::total 8131.052684 # average ReadReq miss latency
915system.cpu.icache.demand_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency
916system.cpu.icache.demand_avg_miss_latency::total 8131.052684 # average overall miss latency
917system.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency
918system.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency
919system.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked
920system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked
921system.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked
922system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
923system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked
924system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked
925system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks
926system.cpu.icache.writebacks::total 1979880 # number of writebacks
927system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits
928system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits
929system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits
930system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits
931system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits
932system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits
933system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980577 # number of ReadReq MSHR misses
934system.cpu.icache.ReadReq_mshr_misses::total 1980577 # number of ReadReq MSHR misses
935system.cpu.icache.demand_mshr_misses::cpu.inst 1980577 # number of demand (read+write) MSHR misses
936system.cpu.icache.demand_mshr_misses::total 1980577 # number of demand (read+write) MSHR misses
937system.cpu.icache.overall_mshr_misses::cpu.inst 1980577 # number of overall MSHR misses
938system.cpu.icache.overall_mshr_misses::total 1980577 # number of overall MSHR misses
939system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15098139938 # number of ReadReq MSHR miss cycles
940system.cpu.icache.ReadReq_mshr_miss_latency::total 15098139938 # number of ReadReq MSHR miss cycles
941system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15098139938 # number of demand (read+write) MSHR miss cycles
942system.cpu.icache.demand_mshr_miss_latency::total 15098139938 # number of demand (read+write) MSHR miss cycles
943system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15098139938 # number of overall MSHR miss cycles
944system.cpu.icache.overall_mshr_miss_latency::total 15098139938 # number of overall MSHR miss cycles
945system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for ReadReq accesses
946system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007994 # mshr miss rate for ReadReq accesses
947system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for demand accesses
948system.cpu.icache.demand_mshr_miss_rate::total 0.007994 # mshr miss rate for demand accesses
949system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses
950system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses
951system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency
952system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency
953system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
954system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
955system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
956system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
957system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued
958system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified
959system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue
960system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
961system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
962system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing
963system.cpu.l2cache.tags.replacements 301370 # number of replacements
964system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use
965system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks.
966system.cpu.l2cache.tags.sampled_refs 317734 # Sample count of references to valid blocks.
967system.cpu.l2cache.tags.avg_refs 22.730041 # Average number of references to valid blocks.
968system.cpu.l2cache.tags.warmup_cycle 44242160500 # Cycle when the warmup percentage was hit.
969system.cpu.l2cache.tags.occ_blocks::writebacks 9843.702780 # Average occupied blocks per requestor
970system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6506.729901 # Average occupied blocks per requestor
971system.cpu.l2cache.tags.occ_percent::writebacks 0.600812 # Average percentage of cache occupancy
972system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397139 # Average percentage of cache occupancy
973system.cpu.l2cache.tags.occ_percent::total 0.997951 # Average percentage of cache occupancy
974system.cpu.l2cache.tags.occ_task_id_blocks::1022 6334 # Occupied blocks per task id
975system.cpu.l2cache.tags.occ_task_id_blocks::1024 10030 # Occupied blocks per task id
976system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id
977system.cpu.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id
978system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1704 # Occupied blocks per task id
979system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4420 # Occupied blocks per task id
980system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
981system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
982system.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
983system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id
984system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id
985system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id
986system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id
987system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses
988system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses
989system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits
990system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits
991system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits
992system.cpu.l2cache.WritebackClean_hits::total 3356496 # number of WritebackClean hits
993system.cpu.l2cache.ReadExReq_hits::cpu.data 718501 # number of ReadExReq hits
994system.cpu.l2cache.ReadExReq_hits::total 718501 # number of ReadExReq hits
995system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976843 # number of ReadCleanReq hits
996system.cpu.l2cache.ReadCleanReq_hits::total 1976843 # number of ReadCleanReq hits
997system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1287256 # number of ReadSharedReq hits
998system.cpu.l2cache.ReadSharedReq_hits::total 1287256 # number of ReadSharedReq hits
999system.cpu.l2cache.demand_hits::cpu.inst 1976843 # number of demand (read+write) hits
1000system.cpu.l2cache.demand_hits::cpu.data 2005757 # number of demand (read+write) hits
1001system.cpu.l2cache.demand_hits::total 3982600 # number of demand (read+write) hits
1002system.cpu.l2cache.overall_hits::cpu.inst 1976843 # number of overall hits
1003system.cpu.l2cache.overall_hits::cpu.data 2005757 # number of overall hits
1004system.cpu.l2cache.overall_hits::total 3982600 # number of overall hits
1005system.cpu.l2cache.UpgradeReq_misses::cpu.data 185 # number of UpgradeReq misses
1006system.cpu.l2cache.UpgradeReq_misses::total 185 # number of UpgradeReq misses
1007system.cpu.l2cache.ReadExReq_misses::cpu.data 2346 # number of ReadExReq misses
1008system.cpu.l2cache.ReadExReq_misses::total 2346 # number of ReadExReq misses
1009system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3550 # number of ReadCleanReq misses
1010system.cpu.l2cache.ReadCleanReq_misses::total 3550 # number of ReadCleanReq misses
1011system.cpu.l2cache.ReadSharedReq_misses::cpu.data 748861 # number of ReadSharedReq misses
1012system.cpu.l2cache.ReadSharedReq_misses::total 748861 # number of ReadSharedReq misses
1013system.cpu.l2cache.demand_misses::cpu.inst 3550 # number of demand (read+write) misses
1014system.cpu.l2cache.demand_misses::cpu.data 751207 # number of demand (read+write) misses
1015system.cpu.l2cache.demand_misses::total 754757 # number of demand (read+write) misses
1016system.cpu.l2cache.overall_misses::cpu.inst 3550 # number of overall misses
1017system.cpu.l2cache.overall_misses::cpu.data 751207 # number of overall misses
1018system.cpu.l2cache.overall_misses::total 754757 # number of overall misses
1019system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195074000 # number of ReadExReq miss cycles
1020system.cpu.l2cache.ReadExReq_miss_latency::total 195074000 # number of ReadExReq miss cycles
1021system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261372000 # number of ReadCleanReq miss cycles
1022system.cpu.l2cache.ReadCleanReq_miss_latency::total 261372000 # number of ReadCleanReq miss cycles
1023system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 51585571000 # number of ReadSharedReq miss cycles
1024system.cpu.l2cache.ReadSharedReq_miss_latency::total 51585571000 # number of ReadSharedReq miss cycles
1025system.cpu.l2cache.demand_miss_latency::cpu.inst 261372000 # number of demand (read+write) miss cycles
1026system.cpu.l2cache.demand_miss_latency::cpu.data 51780645000 # number of demand (read+write) miss cycles
1027system.cpu.l2cache.demand_miss_latency::total 52042017000 # number of demand (read+write) miss cycles
1028system.cpu.l2cache.overall_miss_latency::cpu.inst 261372000 # number of overall miss cycles
1029system.cpu.l2cache.overall_miss_latency::cpu.data 51780645000 # number of overall miss cycles
1030system.cpu.l2cache.overall_miss_latency::total 52042017000 # number of overall miss cycles
1031system.cpu.l2cache.WritebackDirty_accesses::writebacks 736314 # number of WritebackDirty accesses(hits+misses)
1032system.cpu.l2cache.WritebackDirty_accesses::total 736314 # number of WritebackDirty accesses(hits+misses)
1033system.cpu.l2cache.WritebackClean_accesses::writebacks 3356496 # number of WritebackClean accesses(hits+misses)
1034system.cpu.l2cache.WritebackClean_accesses::total 3356496 # number of WritebackClean accesses(hits+misses)
1035system.cpu.l2cache.UpgradeReq_accesses::cpu.data 185 # number of UpgradeReq accesses(hits+misses)
1036system.cpu.l2cache.UpgradeReq_accesses::total 185 # number of UpgradeReq accesses(hits+misses)
1037system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses)
1038system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses)
1039system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980393 # number of ReadCleanReq accesses(hits+misses)
1040system.cpu.l2cache.ReadCleanReq_accesses::total 1980393 # number of ReadCleanReq accesses(hits+misses)
1041system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036117 # number of ReadSharedReq accesses(hits+misses)
1042system.cpu.l2cache.ReadSharedReq_accesses::total 2036117 # number of ReadSharedReq accesses(hits+misses)
1043system.cpu.l2cache.demand_accesses::cpu.inst 1980393 # number of demand (read+write) accesses
1044system.cpu.l2cache.demand_accesses::cpu.data 2756964 # number of demand (read+write) accesses
1045system.cpu.l2cache.demand_accesses::total 4737357 # number of demand (read+write) accesses
1046system.cpu.l2cache.overall_accesses::cpu.inst 1980393 # number of overall (read+write) accesses
1047system.cpu.l2cache.overall_accesses::cpu.data 2756964 # number of overall (read+write) accesses
1048system.cpu.l2cache.overall_accesses::total 4737357 # number of overall (read+write) accesses
1049system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1050system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1051system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003255 # miss rate for ReadExReq accesses
1052system.cpu.l2cache.ReadExReq_miss_rate::total 0.003255 # miss rate for ReadExReq accesses
1053system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.001793 # miss rate for ReadCleanReq accesses
1054system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.001793 # miss rate for ReadCleanReq accesses
1055system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.367789 # miss rate for ReadSharedReq accesses
1056system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.367789 # miss rate for ReadSharedReq accesses
1057system.cpu.l2cache.demand_miss_rate::cpu.inst 0.001793 # miss rate for demand accesses
1058system.cpu.l2cache.demand_miss_rate::cpu.data 0.272476 # miss rate for demand accesses
1059system.cpu.l2cache.demand_miss_rate::total 0.159320 # miss rate for demand accesses
1060system.cpu.l2cache.overall_miss_rate::cpu.inst 0.001793 # miss rate for overall accesses
1061system.cpu.l2cache.overall_miss_rate::cpu.data 0.272476 # miss rate for overall accesses
1062system.cpu.l2cache.overall_miss_rate::total 0.159320 # miss rate for overall accesses
1063system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83151.747656 # average ReadExReq miss latency
1064system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83151.747656 # average ReadExReq miss latency
1065system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73625.915493 # average ReadCleanReq miss latency
1066system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73625.915493 # average ReadCleanReq miss latency
1067system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68885.375257 # average ReadSharedReq miss latency
1068system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68885.375257 # average ReadSharedReq miss latency
1069system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency
1070system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency
1071system.cpu.l2cache.demand_avg_miss_latency::total 68952.016344 # average overall miss latency
1072system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency
1073system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency
1074system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344 # average overall miss latency
1075system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1076system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1077system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1078system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1079system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1080system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1081system.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference
1082system.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks
1083system.cpu.l2cache.writebacks::total 66334 # number of writebacks
1084system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 963 # number of ReadExReq MSHR hits
1085system.cpu.l2cache.ReadExReq_mshr_hits::total 963 # number of ReadExReq MSHR hits
1086system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
1087system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
1088system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 903 # number of ReadSharedReq MSHR hits
1089system.cpu.l2cache.ReadSharedReq_mshr_hits::total 903 # number of ReadSharedReq MSHR hits
1090system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1091system.cpu.l2cache.demand_mshr_hits::cpu.data 1866 # number of demand (read+write) MSHR hits
1092system.cpu.l2cache.demand_mshr_hits::total 1867 # number of demand (read+write) MSHR hits
1093system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1094system.cpu.l2cache.overall_mshr_hits::cpu.data 1866 # number of overall MSHR hits
1095system.cpu.l2cache.overall_mshr_hits::total 1867 # number of overall MSHR hits
1096system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200438 # number of HardPFReq MSHR misses
1097system.cpu.l2cache.HardPFReq_mshr_misses::total 200438 # number of HardPFReq MSHR misses
1098system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 185 # number of UpgradeReq MSHR misses
1099system.cpu.l2cache.UpgradeReq_mshr_misses::total 185 # number of UpgradeReq MSHR misses
1100system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1383 # number of ReadExReq MSHR misses
1101system.cpu.l2cache.ReadExReq_mshr_misses::total 1383 # number of ReadExReq MSHR misses
1102system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3549 # number of ReadCleanReq MSHR misses
1103system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3549 # number of ReadCleanReq MSHR misses
1104system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 747958 # number of ReadSharedReq MSHR misses
1105system.cpu.l2cache.ReadSharedReq_mshr_misses::total 747958 # number of ReadSharedReq MSHR misses
1106system.cpu.l2cache.demand_mshr_misses::cpu.inst 3549 # number of demand (read+write) MSHR misses
1107system.cpu.l2cache.demand_mshr_misses::cpu.data 749341 # number of demand (read+write) MSHR misses
1108system.cpu.l2cache.demand_mshr_misses::total 752890 # number of demand (read+write) MSHR misses
1109system.cpu.l2cache.overall_mshr_misses::cpu.inst 3549 # number of overall MSHR misses
1110system.cpu.l2cache.overall_mshr_misses::cpu.data 749341 # number of overall MSHR misses
1111system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200438 # number of overall MSHR misses
1112system.cpu.l2cache.overall_mshr_misses::total 953328 # number of overall MSHR misses
1113system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of HardPFReq MSHR miss cycles
1114system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16667426112 # number of HardPFReq MSHR miss cycles
1115system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2605000 # number of UpgradeReq MSHR miss cycles
1116system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2605000 # number of UpgradeReq MSHR miss cycles
1117system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 137246500 # number of ReadExReq MSHR miss cycles
1118system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 137246500 # number of ReadExReq MSHR miss cycles
1119system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240029500 # number of ReadCleanReq MSHR miss cycles
1120system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240029500 # number of ReadCleanReq MSHR miss cycles
1121system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 47054888500 # number of ReadSharedReq MSHR miss cycles
1122system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 47054888500 # number of ReadSharedReq MSHR miss cycles
1123system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240029500 # number of demand (read+write) MSHR miss cycles
1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47192135000 # number of demand (read+write) MSHR miss cycles
1125system.cpu.l2cache.demand_mshr_miss_latency::total 47432164500 # number of demand (read+write) MSHR miss cycles
1126system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240029500 # number of overall MSHR miss cycles
1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47192135000 # number of overall MSHR miss cycles
1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of overall MSHR miss cycles
1129system.cpu.l2cache.overall_mshr_miss_latency::total 64099590612 # number of overall MSHR miss cycles
1130system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1131system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1132system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1133system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses
1135system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses
1136system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses
1137system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses
1138system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses
1139system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses
1140system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses
1141system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses
1142system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses
1143system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses
1144system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses
1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1146system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses
1147system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency
1148system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency
1149system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency
1150system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency
1151system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency
1152system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency
1153system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency
1154system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency
1155system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency
1156system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency
1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency
1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency
1159system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency
1160system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency
1161system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency
1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency
1163system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency
1164system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter.
1165system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1166system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1167system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter.
1168system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1169system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1170system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution
1171system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution
1172system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution
1173system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution
1174system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution
1175system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution
1176system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution
1177system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution
1178system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution
1179system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution
1180system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution
1181system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes)
1182system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes)
1183system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes)
1184system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes)
1185system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes)
1186system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes)
1187system.cpu.toL2Bus.snoops 1296784 # Total snoops (count)
1188system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram
1189system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram
1190system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram
1191system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1192system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram
1193system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram
1194system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram
1195system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1196system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1197system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1198system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram
1199system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks)
1200system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%)
1201system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks)
1202system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
1203system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks)
1204system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
1205system.membus.trans_dist::ReadResp 951856 # Transaction distribution
1206system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution
1207system.membus.trans_dist::CleanEvict 227102 # Transaction distribution
1208system.membus.trans_dist::UpgradeReq 185 # Transaction distribution
1209system.membus.trans_dist::ReadExReq 1383 # Transaction distribution
1210system.membus.trans_dist::ReadExResp 1383 # Transaction distribution
1211system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution
1212system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes)
1213system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes)
1214system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes)
1215system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes)
1216system.membus.snoops 0 # Total snoops (count)
1217system.membus.snoop_fanout::samples 1246861 # Request fanout histogram
1218system.membus.snoop_fanout::mean 0 # Request fanout histogram
1219system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1220system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1221system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram
1222system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1223system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1224system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1225system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1226system.membus.snoop_fanout::total 1246861 # Request fanout histogram
1227system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks)
1228system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
1229system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks)
1230system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
1231
1232---------- End Simulation Statistics ----------