| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.326731 # Number of seconds simulated 4sim_ticks 326731324000 # Number of ticks simulated 5final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.326731 # Number of seconds simulated 4sim_ticks 326731324000 # Number of ticks simulated 5final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 133673 # Simulator instruction rate (inst/s) 8host_op_rate 164569 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 68173047 # Simulator tick rate (ticks/s) 10host_mem_usage 277340 # Number of bytes of host memory used 11host_seconds 4792.68 # Real time elapsed on the host | 7host_inst_rate 138534 # Simulator instruction rate (inst/s) 8host_op_rate 170554 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 70652444 # Simulator tick rate (ticks/s) 10host_mem_usage 277336 # Number of bytes of host memory used 11host_seconds 4624.49 # Real time elapsed on the host |
| 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory 19system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory --- 786 unchanged lines hidden (view full) --- 806system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency 807system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency 808system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 809system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked 810system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 811system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked 812system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 813system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked | 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory 19system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory --- 786 unchanged lines hidden (view full) --- 806system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency 807system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency 808system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 809system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked 810system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 811system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked 812system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 813system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked |
| 814system.cpu.dcache.fast_writes 0 # number of fast writes performed 815system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 816system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks 817system.cpu.dcache.writebacks::total 2756452 # number of writebacks 818system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits 819system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits 820system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits 821system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits 822system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 823system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency 861system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency 862system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency 863system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency 864system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency 865system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency 866system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency 867system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency | 814system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks 815system.cpu.dcache.writebacks::total 2756452 # number of writebacks 816system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits 817system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits 818system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits 819system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits 820system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 821system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 858system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency 859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency 860system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency 861system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency 862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency 863system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency 864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency 865system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency |
| 868system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 869system.cpu.icache.tags.replacements 1979880 # number of replacements 870system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use 871system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. 872system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks. 873system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks. 874system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit. 875system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor 876system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 920system.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency 921system.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency 922system.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked 923system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked 924system.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked 925system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 926system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked 927system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked | 866system.cpu.icache.tags.replacements 1979880 # number of replacements 867system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use 868system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. 869system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks. 870system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks. 871system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit. 872system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor 873system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 917system.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency 918system.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency 919system.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked 920system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked 921system.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked 922system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 923system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked 924system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked |
| 928system.cpu.icache.fast_writes 0 # number of fast writes performed 929system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 930system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks 931system.cpu.icache.writebacks::total 1979880 # number of writebacks 932system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits 933system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits 934system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits 935system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits 936system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits 937system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 954system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses 955system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses 956system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency 957system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency 958system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency 959system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency 960system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency 961system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency | 925system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks 926system.cpu.icache.writebacks::total 1979880 # number of writebacks 927system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits 928system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits 929system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits 930system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits 931system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits 932system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 949system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses 950system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses 951system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency 952system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency 953system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency 954system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency 955system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency 956system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency |
| 962system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 963system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued 964system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified 965system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue 966system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 967system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 968system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing 969system.cpu.l2cache.tags.replacements 301370 # number of replacements 970system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use --- 108 unchanged lines hidden (view full) --- 1079system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency 1080system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344 # average overall miss latency 1081system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1082system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1083system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1084system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1085system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1086system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 957system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued 958system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified 959system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue 960system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 961system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 962system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing 963system.cpu.l2cache.tags.replacements 301370 # number of replacements 964system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use --- 108 unchanged lines hidden (view full) --- 1073system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency 1074system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344 # average overall miss latency 1075system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1076system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1077system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1078system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1079system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1080system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1087system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1088system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1089system.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference 1090system.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks 1091system.cpu.l2cache.writebacks::total 66334 # number of writebacks 1092system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 963 # number of ReadExReq MSHR hits 1093system.cpu.l2cache.ReadExReq_mshr_hits::total 963 # number of ReadExReq MSHR hits 1094system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1095system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1096system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 903 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1164system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency 1165system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency 1166system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency 1167system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency 1168system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency 1169system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency 1170system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency 1171system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency | 1081system.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference 1082system.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks 1083system.cpu.l2cache.writebacks::total 66334 # number of writebacks 1084system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 963 # number of ReadExReq MSHR hits 1085system.cpu.l2cache.ReadExReq_mshr_hits::total 963 # number of ReadExReq MSHR hits 1086system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1087system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1088system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 903 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1156system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency 1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency 1160system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency 1161system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency |
| 1172system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1173system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. 1174system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1175system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1176system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. 1177system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1178system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1179system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution --- 61 unchanged lines hidden --- | 1164system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. 1165system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1166system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1167system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. 1168system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1169system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1170system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution --- 61 unchanged lines hidden --- |