| stats.txt (10513:ca4438b6e39a) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.407884 # Number of seconds simulated 4sim_ticks 407883784500 # Number of ticks simulated 5final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.408037 # Number of seconds simulated 4sim_ticks 408037199500 # Number of ticks simulated 5final_tick 408037199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 91246 # Simulator instruction rate (inst/s) 8host_op_rate 112336 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58093586 # Simulator tick rate (ticks/s) 10host_mem_usage 2566152 # Number of bytes of host memory used 11host_seconds 7021.15 # Real time elapsed on the host | 7host_inst_rate 90640 # Simulator instruction rate (inst/s) 8host_op_rate 111590 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57729920 # Simulator tick rate (ticks/s) 10host_mem_usage 318440 # Number of bytes of host memory used 11host_seconds 7068.04 # Real time elapsed on the host |
| 12sim_insts 640649298 # Number of instructions simulated 13sim_ops 788724957 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 640649298 # Number of instructions simulated 13sim_ops 788724957 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 63360 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6867584 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 13490752 # Number of bytes read from this memory 19system.physmem.bytes_read::total 20421696 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 63360 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 63360 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4243968 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4243968 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 990 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 107306 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 210793 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 319089 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 66312 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 66312 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 155338 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 16837110 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 33074990 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 50067438 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 155338 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 155338 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 10404846 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 10404846 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 10404846 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 155338 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 16837110 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 33074990 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 60472284 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 319089 # Number of read requests accepted 44system.physmem.writeReqs 66312 # Number of write requests accepted 45system.physmem.readBursts 319089 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 66312 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 20403200 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue 49system.physmem.bytesWritten 4238016 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 20421696 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 4243968 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 20089 # Per bank write bursts 56system.physmem.perBankRdBursts::1 19545 # Per bank write bursts 57system.physmem.perBankRdBursts::2 20086 # Per bank write bursts 58system.physmem.perBankRdBursts::3 20646 # Per bank write bursts 59system.physmem.perBankRdBursts::4 19933 # Per bank write bursts 60system.physmem.perBankRdBursts::5 20704 # Per bank write bursts 61system.physmem.perBankRdBursts::6 19571 # Per bank write bursts 62system.physmem.perBankRdBursts::7 19471 # Per bank write bursts 63system.physmem.perBankRdBursts::8 19556 # Per bank write bursts 64system.physmem.perBankRdBursts::9 19505 # Per bank write bursts 65system.physmem.perBankRdBursts::10 19502 # Per bank write bursts 66system.physmem.perBankRdBursts::11 20173 # Per bank write bursts 67system.physmem.perBankRdBursts::12 19634 # Per bank write bursts 68system.physmem.perBankRdBursts::13 20280 # Per bank write bursts 69system.physmem.perBankRdBursts::14 19577 # Per bank write bursts 70system.physmem.perBankRdBursts::15 20528 # Per bank write bursts 71system.physmem.perBankWrBursts::0 4247 # Per bank write bursts | 16system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7008448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 12940608 # Number of bytes read from this memory 19system.physmem.bytes_read::total 20176256 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4244736 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4244736 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 109507 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 202197 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 315254 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 66324 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 66324 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 556812 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 17176003 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 31714285 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 49447099 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 556812 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 556812 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 10402816 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 10402816 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 10402816 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 556812 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 17176003 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 31714285 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 59849916 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 315254 # Number of read requests accepted 44system.physmem.writeReqs 66324 # Number of write requests accepted 45system.physmem.readBursts 315254 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 66324 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 20157248 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 19008 # Total number of bytes read from write queue 49system.physmem.bytesWritten 4240064 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 20176256 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 4244736 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 297 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 51 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 14 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 19893 # Per bank write bursts 56system.physmem.perBankRdBursts::1 19507 # Per bank write bursts 57system.physmem.perBankRdBursts::2 19696 # Per bank write bursts 58system.physmem.perBankRdBursts::3 19811 # Per bank write bursts 59system.physmem.perBankRdBursts::4 19755 # Per bank write bursts 60system.physmem.perBankRdBursts::5 20266 # Per bank write bursts 61system.physmem.perBankRdBursts::6 19606 # Per bank write bursts 62system.physmem.perBankRdBursts::7 19431 # Per bank write bursts 63system.physmem.perBankRdBursts::8 19468 # Per bank write bursts 64system.physmem.perBankRdBursts::9 19384 # Per bank write bursts 65system.physmem.perBankRdBursts::10 19414 # Per bank write bursts 66system.physmem.perBankRdBursts::11 19672 # Per bank write bursts 67system.physmem.perBankRdBursts::12 19624 # Per bank write bursts 68system.physmem.perBankRdBursts::13 19992 # Per bank write bursts 69system.physmem.perBankRdBursts::14 19481 # Per bank write bursts 70system.physmem.perBankRdBursts::15 19957 # Per bank write bursts 71system.physmem.perBankWrBursts::0 4278 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::1 4105 # Per bank write bursts | 72system.physmem.perBankWrBursts::1 4105 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::2 4143 # Per bank write bursts 74system.physmem.perBankWrBursts::3 4151 # Per bank write bursts 75system.physmem.perBankWrBursts::4 4245 # Per bank write bursts | 73system.physmem.perBankWrBursts::2 4141 # Per bank write bursts 74system.physmem.perBankWrBursts::3 4152 # Per bank write bursts 75system.physmem.perBankWrBursts::4 4250 # Per bank write bursts |
| 76system.physmem.perBankWrBursts::5 4232 # Per bank write bursts | 76system.physmem.perBankWrBursts::5 4232 # Per bank write bursts |
| 77system.physmem.perBankWrBursts::6 4173 # Per bank write bursts | 77system.physmem.perBankWrBursts::6 4174 # Per bank write bursts |
| 78system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::8 4096 # Per bank write bursts | 78system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::8 4096 # Per bank write bursts |
| 80system.physmem.perBankWrBursts::9 4095 # Per bank write bursts 81system.physmem.perBankWrBursts::10 4096 # Per bank write bursts | 80system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::10 4095 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::11 4097 # Per bank write bursts | 82system.physmem.perBankWrBursts::11 4097 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::12 4098 # Per bank write bursts | 83system.physmem.perBankWrBursts::12 4096 # Per bank write bursts |
| 84system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 85system.physmem.perBankWrBursts::14 4096 # Per bank write bursts | 84system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 85system.physmem.perBankWrBursts::14 4096 # Per bank write bursts |
| 86system.physmem.perBankWrBursts::15 4153 # Per bank write bursts | 86system.physmem.perBankWrBursts::15 4151 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 89system.physmem.totGap 407883730500 # Total gap between requests | 89system.physmem.totGap 408037145000 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 319089 # Read request sizes (log2) | 96system.physmem.readPktSize::6 315254 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 66312 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 124916 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 114317 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 15700 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 7222 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6886 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 7870 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 9271 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 8234 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 7181 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 4414 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 4114 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2941 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 2294 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1703 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1093 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 644 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 66324 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 128804 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 111420 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 14471 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 6711 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6396 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 7547 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 8690 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 8601 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 7182 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 6341 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 3273 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2426 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1825 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1270 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 958 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 1673 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2329 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 2929 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 3407 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 3873 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4352 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4840 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5216 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5606 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5620 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5402 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 4546 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 4208 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 4070 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 4033 # What write queue length does an incoming req see | 151system.physmem.wrQLenPdf::15 590 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 607 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 986 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 1667 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2405 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 2934 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 3403 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 3865 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4344 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4750 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5220 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5565 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5589 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5488 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 4554 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 4251 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see |
| 170system.physmem.wrQLenPdf::34 155 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 115 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 77 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 79 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 79 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 70 # What write queue length does an incoming req see | 170system.physmem.wrQLenPdf::34 147 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 93 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 93 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 90 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 84 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 94 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 85 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 86 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 82 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see |
| 183system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see | 183system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see |
| 184system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 10 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see | 184system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see |
| 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 200system.physmem.bytesPerActivate::samples 138324 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 178.138053 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 128.082938 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 199.804046 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 55124 39.85% 39.85% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 58239 42.10% 81.95% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 14671 10.61% 92.56% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 966 0.70% 93.26% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1420 1.03% 94.29% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1368 0.99% 95.27% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1462 1.06% 96.33% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1224 0.88% 97.22% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 3850 2.78% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 138324 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 67.829475 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 35.454654 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 482.917109 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 3981 99.10% 99.10% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.48% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::1024-1535 5 0.12% 99.60% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.70% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::2048-2559 3 0.07% 99.78% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::2560-3071 2 0.05% 99.83% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.85% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.90% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::12288-12799 1 0.02% 99.93% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::13824-14335 2 0.05% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 16.484690 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 16.435555 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 1.421529 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16 3367 83.82% 83.82% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::17 9 0.22% 84.04% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::18 437 10.88% 94.92% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::19 79 1.97% 96.89% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20 37 0.92% 97.81% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::21 18 0.45% 98.26% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::22 15 0.37% 98.63% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::23 22 0.55% 99.18% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::24 13 0.32% 99.50% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::25 3 0.07% 99.58% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::26 6 0.15% 99.73% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::27 2 0.05% 99.78% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::28 3 0.07% 99.85% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::29 2 0.05% 99.90% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::30 1 0.02% 99.93% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::34 2 0.05% 99.98% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads 253system.physmem.totQLat 9958454882 # Total ticks spent queuing 254system.physmem.totMemAccLat 15935954882 # Total ticks spent from burst creation until serviced by the DRAM 255system.physmem.totBusLat 1594000000 # Total ticks spent in databus transfers 256system.physmem.avgQLat 31237.31 # Average queueing delay per DRAM burst | 200system.physmem.bytesPerActivate::samples 136345 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 178.922586 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 128.860330 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 198.953379 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 53850 39.50% 39.50% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 57322 42.04% 81.54% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 14832 10.88% 92.42% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1348 0.99% 93.40% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1343 0.99% 94.39% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1322 0.97% 95.36% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1347 0.99% 96.35% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1288 0.94% 97.29% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 3693 2.71% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 136345 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4024 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 74.490060 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 34.867874 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 683.746449 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-1023 4004 99.50% 99.50% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::1024-2047 7 0.17% 99.68% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::2048-3071 3 0.07% 99.75% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.80% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::4096-5119 1 0.02% 99.83% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::7168-8191 2 0.05% 99.88% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::8192-9215 2 0.05% 99.93% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::total 4024 # Reads before turning the bus around for writes 229system.physmem.wrPerTurnAround::samples 4024 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::mean 16.463966 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::gmean 16.422591 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::stdev 1.272940 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::16 3359 83.47% 83.47% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::17 14 0.35% 83.82% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::18 449 11.16% 94.98% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::19 91 2.26% 97.24% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20 36 0.89% 98.14% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::21 19 0.47% 98.61% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::22 14 0.35% 98.96% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::23 17 0.42% 99.38% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::24 8 0.20% 99.58% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::25 6 0.15% 99.73% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::26 4 0.10% 99.83% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::27 5 0.12% 99.95% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::total 4024 # Writes before turning the bus around for reads 248system.physmem.totQLat 9384520258 # Total ticks spent queuing 249system.physmem.totMemAccLat 15289964008 # Total ticks spent from burst creation until serviced by the DRAM 250system.physmem.totBusLat 1574785000 # Total ticks spent in databus transfers 251system.physmem.avgQLat 29796.20 # Average queueing delay per DRAM burst |
| 257system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 252system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 258system.physmem.avgMemAccLat 49987.31 # Average memory access latency per DRAM burst 259system.physmem.avgRdBW 50.02 # Average DRAM read bandwidth in MiByte/s | 253system.physmem.avgMemAccLat 48546.20 # Average memory access latency per DRAM burst 254system.physmem.avgRdBW 49.40 # Average DRAM read bandwidth in MiByte/s |
| 260system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s | 255system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s |
| 261system.physmem.avgRdBWSys 50.07 # Average system read bandwidth in MiByte/s | 256system.physmem.avgRdBWSys 49.45 # Average system read bandwidth in MiByte/s |
| 262system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s 263system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 264system.physmem.busUtil 0.47 # Data bus utilization in percentage 265system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads 266system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes | 257system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s 258system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 259system.physmem.busUtil 0.47 # Data bus utilization in percentage 260system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads 261system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes |
| 267system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing 268system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing 269system.physmem.readRowHits 219908 # Number of row buffer hits during reads 270system.physmem.writeRowHits 26785 # Number of row buffer hits during writes 271system.physmem.readRowHitRate 68.98 # Row buffer hit rate for reads 272system.physmem.writeRowHitRate 40.43 # Row buffer hit rate for writes 273system.physmem.avgGap 1058335.94 # Average gap between requests 274system.physmem.pageHitRate 64.07 # Row buffer hit rate, read and write combined 275system.physmem.memoryStateTime::IDLE 155274651966 # Time in different power states 276system.physmem.memoryStateTime::REF 13620100000 # Time in different power states 277system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 278system.physmem.memoryStateTime::ACT 238988228034 # Time in different power states 279system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 280system.physmem.actEnergy::0 524928600 # Energy for activate commands per rank (pJ) 281system.physmem.actEnergy::1 520778160 # Energy for activate commands per rank (pJ) 282system.physmem.preEnergy::0 286419375 # Energy for precharge commands per rank (pJ) 283system.physmem.preEnergy::1 284154750 # Energy for precharge commands per rank (pJ) 284system.physmem.readEnergy::0 1248351000 # Energy for read commands per rank (pJ) 285system.physmem.readEnergy::1 1238000400 # Energy for read commands per rank (pJ) 286system.physmem.writeEnergy::0 216380160 # Energy for write commands per rank (pJ) 287system.physmem.writeEnergy::1 212718960 # Energy for write commands per rank (pJ) 288system.physmem.refreshEnergy::0 26640915600 # Energy for refresh commands per rank (pJ) 289system.physmem.refreshEnergy::1 26640915600 # Energy for refresh commands per rank (pJ) 290system.physmem.actBackEnergy::0 97043660235 # Energy for active background per rank (pJ) 291system.physmem.actBackEnergy::1 97028348895 # Energy for active background per rank (pJ) 292system.physmem.preBackEnergy::0 159603762000 # Energy for precharge background per rank (pJ) 293system.physmem.preBackEnergy::1 159617193000 # Energy for precharge background per rank (pJ) 294system.physmem.totalEnergy::0 285564416970 # Total energy per rank (pJ) 295system.physmem.totalEnergy::1 285542109765 # Total energy per rank (pJ) 296system.physmem.averagePower::0 700.113612 # Core power per rank (mW) 297system.physmem.averagePower::1 700.058922 # Core power per rank (mW) 298system.membus.trans_dist::ReadReq 317731 # Transaction distribution 299system.membus.trans_dist::ReadResp 317731 # Transaction distribution 300system.membus.trans_dist::Writeback 66312 # Transaction distribution 301system.membus.trans_dist::UpgradeReq 19 # Transaction distribution 302system.membus.trans_dist::UpgradeResp 19 # Transaction distribution 303system.membus.trans_dist::ReadExReq 1358 # Transaction distribution 304system.membus.trans_dist::ReadExResp 1358 # Transaction distribution 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 704528 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count::total 704528 # Packet count per connected master and slave (bytes) 307system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24665664 # Cumulative packet size per connected master and slave (bytes) 308system.membus.pkt_size::total 24665664 # Cumulative packet size per connected master and slave (bytes) 309system.membus.snoops 0 # Total snoops (count) 310system.membus.snoop_fanout::samples 385420 # Request fanout histogram 311system.membus.snoop_fanout::mean 0 # Request fanout histogram 312system.membus.snoop_fanout::stdev 0 # Request fanout histogram 313system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 314system.membus.snoop_fanout::0 385420 100.00% 100.00% # Request fanout histogram 315system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 316system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 317system.membus.snoop_fanout::min_value 0 # Request fanout histogram 318system.membus.snoop_fanout::max_value 0 # Request fanout histogram 319system.membus.snoop_fanout::total 385420 # Request fanout histogram 320system.membus.reqLayer0.occupancy 968060850 # Layer occupancy (ticks) 321system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 322system.membus.respLayer1.occupancy 2930140600 # Layer occupancy (ticks) 323system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 324system.cpu_clk_domain.clock 500 # Clock period in ticks 325system.cpu.branchPred.lookups 233961455 # Number of BP lookups 326system.cpu.branchPred.condPredicted 161822903 # Number of conditional branches predicted 327system.cpu.branchPred.condIncorrect 15515021 # Number of conditional branches incorrect 328system.cpu.branchPred.BTBLookups 121571694 # Number of BTB lookups 329system.cpu.branchPred.BTBHits 108258179 # Number of BTB hits | 262system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing 263system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing 264system.physmem.readRowHits 218395 # Number of row buffer hits during reads 265system.physmem.writeRowHits 26455 # Number of row buffer hits during writes 266system.physmem.readRowHitRate 69.34 # Row buffer hit rate for reads 267system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes 268system.physmem.avgGap 1069341.38 # Average gap between requests 269system.physmem.pageHitRate 64.23 # Row buffer hit rate, read and write combined 270system.physmem_0.actEnergy 517708800 # Energy for activate commands per rank (pJ) 271system.physmem_0.preEnergy 282480000 # Energy for precharge commands per rank (pJ) 272system.physmem_0.readEnergy 1231869600 # Energy for read commands per rank (pJ) 273system.physmem_0.writeEnergy 216613440 # Energy for write commands per rank (pJ) 274system.physmem_0.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) 275system.physmem_0.actBackEnergy 96151044510 # Energy for active background per rank (pJ) 276system.physmem_0.preBackEnergy 160475521500 # Energy for precharge background per rank (pJ) 277system.physmem_0.totalEnergy 285525816090 # Total energy per rank (pJ) 278system.physmem_0.averagePower 699.765171 # Core power per rank (mW) 279system.physmem_0.memoryStateTime::IDLE 266332221673 # Time in different power states 280system.physmem_0.memoryStateTime::REF 13625040000 # Time in different power states 281system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 282system.physmem_0.memoryStateTime::ACT 128074629327 # Time in different power states 283system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 284system.physmem_1.actEnergy 512870400 # Energy for activate commands per rank (pJ) 285system.physmem_1.preEnergy 279840000 # Energy for precharge commands per rank (pJ) 286system.physmem_1.readEnergy 1224147600 # Energy for read commands per rank (pJ) 287system.physmem_1.writeEnergy 212693040 # Energy for write commands per rank (pJ) 288system.physmem_1.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) 289system.physmem_1.actBackEnergy 96078218175 # Energy for active background per rank (pJ) 290system.physmem_1.preBackEnergy 160539404250 # Energy for precharge background per rank (pJ) 291system.physmem_1.totalEnergy 285497751705 # Total energy per rank (pJ) 292system.physmem_1.averagePower 699.696391 # Core power per rank (mW) 293system.physmem_1.memoryStateTime::IDLE 266439995679 # Time in different power states 294system.physmem_1.memoryStateTime::REF 13625040000 # Time in different power states 295system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 296system.physmem_1.memoryStateTime::ACT 127966985321 # Time in different power states 297system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 298system.cpu.branchPred.lookups 233958621 # Number of BP lookups 299system.cpu.branchPred.condPredicted 161821709 # Number of conditional branches predicted 300system.cpu.branchPred.condIncorrect 15514987 # Number of conditional branches incorrect 301system.cpu.branchPred.BTBLookups 121572023 # Number of BTB lookups 302system.cpu.branchPred.BTBHits 108258061 # Number of BTB hits |
| 330system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 303system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 331system.cpu.branchPred.BTBHitPct 89.048836 # BTB Hit Percentage 332system.cpu.branchPred.usedRAS 25034450 # Number of times the RAS was used to get a target. 333system.cpu.branchPred.RASInCorrect 1300530 # Number of incorrect RAS predictions. | 304system.cpu.branchPred.BTBHitPct 89.048498 # BTB Hit Percentage 305system.cpu.branchPred.usedRAS 25035636 # Number of times the RAS was used to get a target. 306system.cpu.branchPred.RASInCorrect 1300514 # Number of incorrect RAS predictions. 307system.cpu_clk_domain.clock 500 # Clock period in ticks 308system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| 334system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 335system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 336system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 337system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 338system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 339system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 340system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 341system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 347system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 348system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 349system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 350system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 351system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 352system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 353system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 354system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 316system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 317system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 318system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 319system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 320system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 321system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 322system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 323system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 329system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 330system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 331system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 332system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 333system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 334system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 335system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 336system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 337system.cpu.dtb.walker.walks 0 # Table walker walks requested 338system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 355system.cpu.dtb.inst_hits 0 # ITB inst hits 356system.cpu.dtb.inst_misses 0 # ITB inst misses 357system.cpu.dtb.read_hits 0 # DTB read hits 358system.cpu.dtb.read_misses 0 # DTB read misses 359system.cpu.dtb.write_hits 0 # DTB write hits 360system.cpu.dtb.write_misses 0 # DTB write misses 361system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 362system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 368system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 369system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 370system.cpu.dtb.read_accesses 0 # DTB read accesses 371system.cpu.dtb.write_accesses 0 # DTB write accesses 372system.cpu.dtb.inst_accesses 0 # ITB inst accesses 373system.cpu.dtb.hits 0 # DTB hits 374system.cpu.dtb.misses 0 # DTB misses 375system.cpu.dtb.accesses 0 # DTB accesses | 345system.cpu.dtb.inst_hits 0 # ITB inst hits 346system.cpu.dtb.inst_misses 0 # ITB inst misses 347system.cpu.dtb.read_hits 0 # DTB read hits 348system.cpu.dtb.read_misses 0 # DTB read misses 349system.cpu.dtb.write_hits 0 # DTB write hits 350system.cpu.dtb.write_misses 0 # DTB write misses 351system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 352system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 358system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 359system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 360system.cpu.dtb.read_accesses 0 # DTB read accesses 361system.cpu.dtb.write_accesses 0 # DTB write accesses 362system.cpu.dtb.inst_accesses 0 # ITB inst accesses 363system.cpu.dtb.hits 0 # DTB hits 364system.cpu.dtb.misses 0 # DTB misses 365system.cpu.dtb.accesses 0 # DTB accesses |
| 366system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 376system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 377system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 378system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 379system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 380system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 381system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 382system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 383system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 389system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 390system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 391system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 392system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 393system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 394system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 395system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 396system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 374system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 375system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 376system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 377system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 378system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 379system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 380system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 381system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 387system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 388system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 389system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 390system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 391system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 392system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 393system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 394system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 395system.cpu.itb.walker.walks 0 # Table walker walks requested 396system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 397system.cpu.itb.inst_hits 0 # ITB inst hits 398system.cpu.itb.inst_misses 0 # ITB inst misses 399system.cpu.itb.read_hits 0 # DTB read hits 400system.cpu.itb.read_misses 0 # DTB read misses 401system.cpu.itb.write_hits 0 # DTB write hits 402system.cpu.itb.write_misses 0 # DTB write misses 403system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 404system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 411system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 412system.cpu.itb.read_accesses 0 # DTB read accesses 413system.cpu.itb.write_accesses 0 # DTB write accesses 414system.cpu.itb.inst_accesses 0 # ITB inst accesses 415system.cpu.itb.hits 0 # DTB hits 416system.cpu.itb.misses 0 # DTB misses 417system.cpu.itb.accesses 0 # DTB accesses 418system.cpu.workload.num_syscalls 673 # Number of system calls | 403system.cpu.itb.inst_hits 0 # ITB inst hits 404system.cpu.itb.inst_misses 0 # ITB inst misses 405system.cpu.itb.read_hits 0 # DTB read hits 406system.cpu.itb.read_misses 0 # DTB read misses 407system.cpu.itb.write_hits 0 # DTB write hits 408system.cpu.itb.write_misses 0 # DTB write misses 409system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 410system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 417system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 418system.cpu.itb.read_accesses 0 # DTB read accesses 419system.cpu.itb.write_accesses 0 # DTB write accesses 420system.cpu.itb.inst_accesses 0 # ITB inst accesses 421system.cpu.itb.hits 0 # DTB hits 422system.cpu.itb.misses 0 # DTB misses 423system.cpu.itb.accesses 0 # DTB accesses 424system.cpu.workload.num_syscalls 673 # Number of system calls |
| 419system.cpu.numCycles 815767570 # number of cpu cycles simulated | 425system.cpu.numCycles 816074400 # number of cpu cycles simulated |
| 420system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 421system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 426system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 427system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 422system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss 423system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed 424system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered 425system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken 426system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked 427system.cpu.fetch.SquashCycles 31064711 # Number of cycles fetch has spent squashing 428system.cpu.fetch.MiscStallCycles 216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 428system.cpu.fetch.icacheStallCycles 84077011 # Number of cycles fetch is stalled on an Icache miss 429system.cpu.fetch.Insts 1200073954 # Number of instructions fetch has processed 430system.cpu.fetch.Branches 233958621 # Number of branches that fetch encountered 431system.cpu.fetch.predictedBranches 133293697 # Number of branches that fetch has predicted taken 432system.cpu.fetch.Cycles 716167787 # Number of cycles fetch has run and was not squashing or blocked 433system.cpu.fetch.SquashCycles 31064641 # Number of cycles fetch has spent squashing 434system.cpu.fetch.MiscStallCycles 2347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 429system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps | 435system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps |
| 430system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR 431system.cpu.fetch.CacheLines 370072724 # Number of cache lines fetched 432system.cpu.fetch.IcacheSquashes 652087 # Number of outstanding Icache misses that were squashed 433system.cpu.fetch.rateDist::samples 815611997 # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::mean 1.839157 # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) | 436system.cpu.fetch.IcacheWaitRetryStallCycles 2996 # Number of stall cycles due to full MSHR 437system.cpu.fetch.CacheLines 370071850 # Number of cache lines fetched 438system.cpu.fetch.IcacheSquashes 652472 # Number of outstanding Icache misses that were squashed 439system.cpu.fetch.rateDist::samples 815782492 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::mean 1.838759 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::stdev 1.161594 # Number of instructions fetched each cycle (Total) |
| 436system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 442system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 437system.cpu.fetch.rateDist::0 134572174 16.50% 16.50% # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::1 222502254 27.28% 43.78% # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::2 98076609 12.02% 55.80% # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::3 360460960 44.20% 100.00% # Number of instructions fetched each cycle (Total) | 443system.cpu.fetch.rateDist::0 134746116 16.52% 16.52% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::1 222503118 27.27% 43.79% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::2 98075778 12.02% 55.81% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::3 360457480 44.19% 100.00% # Number of instructions fetched each cycle (Total) |
| 441system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 447system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 444system.cpu.fetch.rateDist::total 815611997 # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.branchRate 0.286799 # Number of branch fetches per cycle 446system.cpu.fetch.rate 1.471100 # Number of inst fetches per cycle 447system.cpu.decode.IdleCycles 119967047 # Number of cycles decode is idle 448system.cpu.decode.BlockedCycles 156830594 # Number of cycles decode is blocked 449system.cpu.decode.RunCycles 484662032 # Number of cycles decode is running 450system.cpu.decode.UnblockCycles 38633655 # Number of cycles decode is unblocking 451system.cpu.decode.SquashCycles 15518669 # Number of cycles decode is squashing 452system.cpu.decode.BranchResolved 25180757 # Number of times decode resolved a branch 453system.cpu.decode.BranchMispred 13832 # Number of times decode detected a branch misprediction 454system.cpu.decode.DecodedInsts 1248142745 # Number of instructions handled by decode 455system.cpu.decode.SquashedInsts 39968083 # Number of squashed instructions handled by decode 456system.cpu.rename.SquashCycles 15518669 # Number of cycles rename is squashing 457system.cpu.rename.IdleCycles 176978211 # Number of cycles rename is idle 458system.cpu.rename.BlockCycles 77349013 # Number of cycles rename is blocking 459system.cpu.rename.serializeStallCycles 209115 # count of cycles rename stalled for serializing inst 460system.cpu.rename.RunCycles 464956606 # Number of cycles rename is running 461system.cpu.rename.UnblockCycles 80600383 # Number of cycles rename is unblocking 462system.cpu.rename.RenamedInsts 1190653187 # Number of instructions processed by rename 463system.cpu.rename.SquashedInsts 25546667 # Number of squashed instructions processed by rename 464system.cpu.rename.ROBFullEvents 24946830 # Number of times rename has blocked due to ROB full 465system.cpu.rename.IQFullEvents 2267986 # Number of times rename has blocked due to IQ full 466system.cpu.rename.LQFullEvents 40254462 # Number of times rename has blocked due to LQ full 467system.cpu.rename.SQFullEvents 1692453 # Number of times rename has blocked due to SQ full 468system.cpu.rename.RenamedOperands 1225396135 # Number of destination operands rename has renamed 469system.cpu.rename.RenameLookups 5812466885 # Number of register rename lookups that rename has made 470system.cpu.rename.int_rename_lookups 1358185264 # Number of integer rename lookups 471system.cpu.rename.fp_rename_lookups 40876472 # Number of floating rename lookups | 450system.cpu.fetch.rateDist::total 815782492 # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.branchRate 0.286688 # Number of branch fetches per cycle 452system.cpu.fetch.rate 1.470545 # Number of inst fetches per cycle 453system.cpu.decode.IdleCycles 119982553 # Number of cycles decode is idle 454system.cpu.decode.BlockedCycles 156985722 # Number of cycles decode is blocked 455system.cpu.decode.RunCycles 484662665 # Number of cycles decode is running 456system.cpu.decode.UnblockCycles 38632910 # Number of cycles decode is unblocking 457system.cpu.decode.SquashCycles 15518642 # Number of cycles decode is squashing 458system.cpu.decode.BranchResolved 25180928 # Number of times decode resolved a branch 459system.cpu.decode.BranchMispred 13826 # Number of times decode detected a branch misprediction 460system.cpu.decode.DecodedInsts 1248143840 # Number of instructions handled by decode 461system.cpu.decode.SquashedInsts 39966741 # Number of squashed instructions handled by decode 462system.cpu.rename.SquashCycles 15518642 # Number of cycles rename is squashing 463system.cpu.rename.IdleCycles 176992343 # Number of cycles rename is idle 464system.cpu.rename.BlockCycles 77462427 # Number of cycles rename is blocking 465system.cpu.rename.serializeStallCycles 207446 # count of cycles rename stalled for serializing inst 466system.cpu.rename.RunCycles 464957580 # Number of cycles rename is running 467system.cpu.rename.UnblockCycles 80644054 # Number of cycles rename is unblocking 468system.cpu.rename.RenamedInsts 1190653894 # Number of instructions processed by rename 469system.cpu.rename.SquashedInsts 25546220 # Number of squashed instructions processed by rename 470system.cpu.rename.ROBFullEvents 24993767 # Number of times rename has blocked due to ROB full 471system.cpu.rename.IQFullEvents 2267123 # Number of times rename has blocked due to IQ full 472system.cpu.rename.LQFullEvents 40253162 # Number of times rename has blocked due to LQ full 473system.cpu.rename.SQFullEvents 1738390 # Number of times rename has blocked due to SQ full 474system.cpu.rename.RenamedOperands 1225396904 # Number of destination operands rename has renamed 475system.cpu.rename.RenameLookups 5812470532 # Number of register rename lookups that rename has made 476system.cpu.rename.int_rename_lookups 1358186197 # Number of integer rename lookups 477system.cpu.rename.fp_rename_lookups 40876541 # Number of floating rename lookups |
| 472system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed | 478system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed |
| 473system.cpu.rename.UndoneMaps 350617905 # Number of HB maps that are undone due to squashing 474system.cpu.rename.serializingInsts 7272 # count of serializing insts renamed 475system.cpu.rename.tempSerializingInsts 7264 # count of temporary serializing insts renamed 476system.cpu.rename.skidInsts 108149104 # count of insts added to the skid buffer 477system.cpu.memDep0.insertedLoads 366119032 # Number of loads inserted to the mem dependence unit. 478system.cpu.memDep0.insertedStores 236098756 # Number of stores inserted to the mem dependence unit. 479system.cpu.memDep0.conflictingLoads 1753479 # Number of conflicting loads. 480system.cpu.memDep0.conflictingStores 5371728 # Number of conflicting stores. 481system.cpu.iq.iqInstsAdded 1168565166 # Number of instructions added to the IQ (excludes non-spec) | 479system.cpu.rename.UndoneMaps 350618674 # Number of HB maps that are undone due to squashing 480system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed 481system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed 482system.cpu.rename.skidInsts 108147318 # count of insts added to the skid buffer 483system.cpu.memDep0.insertedLoads 366118935 # Number of loads inserted to the mem dependence unit. 484system.cpu.memDep0.insertedStores 236099157 # Number of stores inserted to the mem dependence unit. 485system.cpu.memDep0.conflictingLoads 1781337 # Number of conflicting loads. 486system.cpu.memDep0.conflictingStores 5349105 # Number of conflicting stores. 487system.cpu.iq.iqInstsAdded 1168566408 # Number of instructions added to the IQ (excludes non-spec) |
| 482system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ | 488system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ |
| 483system.cpu.iq.iqInstsIssued 1017100859 # Number of instructions issued 484system.cpu.iq.iqSquashedInstsIssued 18396242 # Number of squashed instructions issued 485system.cpu.iq.iqSquashedInstsExamined 379746204 # Number of squashed instructions iterated over during squash; mainly for profiling 486system.cpu.iq.iqSquashedOperandsExamined 1032205063 # Number of squashed operands that are examined and possibly removed from graph | 489system.cpu.iq.iqInstsIssued 1017104063 # Number of instructions issued 490system.cpu.iq.iqSquashedInstsIssued 18374377 # Number of squashed instructions issued 491system.cpu.iq.iqSquashedInstsExamined 379747029 # Number of squashed instructions iterated over during squash; mainly for profiling 492system.cpu.iq.iqSquashedOperandsExamined 1032159170 # Number of squashed operands that are examined and possibly removed from graph |
| 487system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed | 493system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed |
| 488system.cpu.iq.issued_per_cycle::samples 815611997 # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::mean 1.247040 # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::stdev 1.084974 # Number of insts issued each cycle | 494system.cpu.iq.issued_per_cycle::samples 815782492 # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::mean 1.246783 # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle |
| 491system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 497system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 492system.cpu.iq.issued_per_cycle::0 257903097 31.62% 31.62% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::1 228438073 28.01% 59.63% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::2 215325690 26.40% 86.03% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::3 97769150 11.99% 98.02% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::4 16175979 1.98% 100.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle | 498system.cpu.iq.issued_per_cycle::0 258071655 31.63% 31.63% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::1 228431382 28.00% 59.64% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::2 215339964 26.40% 86.03% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::3 97765220 11.98% 98.02% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::4 16174262 1.98% 100.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle |
| 498system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 504system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 504system.cpu.iq.issued_per_cycle::total 815611997 # Number of insts issued each cycle | 510system.cpu.iq.issued_per_cycle::total 815782492 # Number of insts issued each cycle |
| 505system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 511system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 506system.cpu.iq.fu_full::IntAlu 64512923 19.13% 19.13% # attempts to use FU when none available 507system.cpu.iq.fu_full::IntMult 18147 0.01% 19.13% # attempts to use FU when none available | 512system.cpu.iq.fu_full::IntAlu 64513595 19.12% 19.12% # attempts to use FU when none available 513system.cpu.iq.fu_full::IntMult 18145 0.01% 19.13% # attempts to use FU when none available |
| 508system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available 509system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available 510system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available 511system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available 512system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available 513system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available 514system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 527system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available | 514system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available 515system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available 517system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 533system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available |
| 535system.cpu.iq.fu_full::MemRead 155504488 46.10% 65.42% # attempts to use FU when none available 536system.cpu.iq.fu_full::MemWrite 116641749 34.58% 100.00% # attempts to use FU when none available | 541system.cpu.iq.fu_full::MemRead 155496772 46.10% 65.41% # attempts to use FU when none available 542system.cpu.iq.fu_full::MemWrite 116668709 34.59% 100.00% # attempts to use FU when none available |
| 537system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 538system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 539system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 543system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 544system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 545system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 540system.cpu.iq.FU_type_0::IntAlu 456383765 44.87% 44.87% # Type of FU issued 541system.cpu.iq.FU_type_0::IntMult 5195693 0.51% 45.38% # Type of FU issued | 546system.cpu.iq.FU_type_0::IntAlu 456384260 44.87% 44.87% # Type of FU issued 547system.cpu.iq.FU_type_0::IntMult 5195827 0.51% 45.38% # Type of FU issued |
| 542system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued 543system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued 544system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued 545system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued 546system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued 547system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued 548system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 555system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued | 548system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued 549system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued 550system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued 551system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued 552system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 561system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued |
| 563system.cpu.iq.FU_type_0::SimdFloatCvt 2550151 0.25% 46.01% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.01% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdFloatMisc 11478998 1.13% 47.14% # Type of FU issued | 569system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued |
| 566system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued | 572system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued |
| 569system.cpu.iq.FU_type_0::MemRead 322094029 31.67% 78.81% # Type of FU issued 570system.cpu.iq.FU_type_0::MemWrite 215573019 21.19% 100.00% # Type of FU issued | 575system.cpu.iq.FU_type_0::MemRead 322085949 31.67% 78.80% # Type of FU issued 576system.cpu.iq.FU_type_0::MemWrite 215583681 21.20% 100.00% # Type of FU issued |
| 571system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 572system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 577system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 578system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 573system.cpu.iq.FU_type_0::total 1017100859 # Type of FU issued 574system.cpu.iq.rate 1.246802 # Inst issue rate 575system.cpu.iq.fu_busy_cnt 337314196 # FU busy when requested 576system.cpu.iq.fu_busy_rate 0.331643 # FU busy rate (busy events/executed inst) 577system.cpu.iq.int_inst_queue_reads 3143647062 # Number of integer instruction queue reads 578system.cpu.iq.int_inst_queue_writes 1504776491 # Number of integer instruction queue writes 579system.cpu.iq.int_inst_queue_wakeup_accesses 934274751 # Number of integer instruction queue wakeup accesses 580system.cpu.iq.fp_inst_queue_reads 61877091 # Number of floating instruction queue reads 581system.cpu.iq.fp_inst_queue_writes 43565761 # Number of floating instruction queue writes 582system.cpu.iq.fp_inst_queue_wakeup_accesses 26152451 # Number of floating instruction queue wakeup accesses 583system.cpu.iq.int_alu_accesses 1320604680 # Number of integer alu accesses 584system.cpu.iq.fp_alu_accesses 33810375 # Number of floating point alu accesses 585system.cpu.iew.lsq.thread0.forwLoads 9960281 # Number of loads that had data forwarded from stores | 579system.cpu.iq.FU_type_0::total 1017104063 # Type of FU issued 580system.cpu.iq.rate 1.246337 # Inst issue rate 581system.cpu.iq.fu_busy_cnt 337334110 # FU busy when requested 582system.cpu.iq.fu_busy_rate 0.331661 # FU busy rate (busy events/executed inst) 583system.cpu.iq.int_inst_queue_reads 3143822052 # Number of integer instruction queue reads 584system.cpu.iq.int_inst_queue_writes 1504778489 # Number of integer instruction queue writes 585system.cpu.iq.int_inst_queue_wakeup_accesses 934283929 # Number of integer instruction queue wakeup accesses 586system.cpu.iq.fp_inst_queue_reads 61877053 # Number of floating instruction queue reads 587system.cpu.iq.fp_inst_queue_writes 43565817 # Number of floating instruction queue writes 588system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses 589system.cpu.iq.int_alu_accesses 1320627818 # Number of integer alu accesses 590system.cpu.iq.fp_alu_accesses 33810355 # Number of floating point alu accesses 591system.cpu.iew.lsq.thread0.forwLoads 9960647 # Number of loads that had data forwarded from stores |
| 586system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 592system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 587system.cpu.iew.lsq.thread0.squashedLoads 113878094 # Number of loads squashed 588system.cpu.iew.lsq.thread0.ignoredResponses 1252 # Number of memory responses ignored because the instruction is squashed 589system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations 590system.cpu.iew.lsq.thread0.squashedStores 107118260 # Number of stores squashed | 593system.cpu.iew.lsq.thread0.squashedLoads 113877997 # Number of loads squashed 594system.cpu.iew.lsq.thread0.ignoredResponses 1254 # Number of memory responses ignored because the instruction is squashed 595system.cpu.iew.lsq.thread0.memOrderViolation 18512 # Number of memory ordering violations 596system.cpu.iew.lsq.thread0.squashedStores 107118661 # Number of stores squashed |
| 591system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 592system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 597system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 598system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 593system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled 594system.cpu.iew.lsq.thread0.cacheBlocked 23979 # Number of times an access to memory failed due to the cache being blocked | 599system.cpu.iew.lsq.thread0.rescheduledLoads 2065827 # Number of loads that were rescheduled 600system.cpu.iew.lsq.thread0.cacheBlocked 22129 # Number of times an access to memory failed due to the cache being blocked |
| 595system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 601system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 596system.cpu.iew.iewSquashCycles 15518669 # Number of cycles IEW is squashing 597system.cpu.iew.iewBlockCycles 35328826 # Number of cycles IEW is blocking 598system.cpu.iew.iewUnblockCycles 675397 # Number of cycles IEW is unblocking 599system.cpu.iew.iewDispatchedInsts 1168583078 # Number of instructions dispatched to IQ | 602system.cpu.iew.iewSquashCycles 15518642 # Number of cycles IEW is squashing 603system.cpu.iew.iewBlockCycles 35326933 # Number of cycles IEW is blocking 604system.cpu.iew.iewUnblockCycles 672265 # Number of cycles IEW is unblocking 605system.cpu.iew.iewDispatchedInsts 1168584324 # Number of instructions dispatched to IQ |
| 600system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 606system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 601system.cpu.iew.iewDispLoadInsts 366119032 # Number of dispatched load instructions 602system.cpu.iew.iewDispStoreInsts 236098756 # Number of dispatched store instructions | 607system.cpu.iew.iewDispLoadInsts 366118935 # Number of dispatched load instructions 608system.cpu.iew.iewDispStoreInsts 236099157 # Number of dispatched store instructions |
| 603system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions | 609system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions |
| 604system.cpu.iew.iewIQFullEvents 121 # Number of times the IQ has become full, causing a stall 605system.cpu.iew.iewLSQFullEvents 678981 # Number of times the LSQ has become full, causing a stall 606system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations 607system.cpu.iew.predictedTakenIncorrect 15437712 # Number of branches that were predicted taken incorrectly 608system.cpu.iew.predictedNotTakenIncorrect 3784771 # Number of branches that were predicted not taken incorrectly 609system.cpu.iew.branchMispredicts 19222483 # Number of branch mispredicts detected at execute 610system.cpu.iew.iewExecutedInsts 974757504 # Number of executed instructions 611system.cpu.iew.iewExecLoadInsts 303300667 # Number of load instructions executed 612system.cpu.iew.iewExecSquashedInsts 42343355 # Number of squashed instructions skipped in execute | 610system.cpu.iew.iewIQFullEvents 110 # Number of times the IQ has become full, causing a stall 611system.cpu.iew.iewLSQFullEvents 675878 # Number of times the LSQ has become full, causing a stall 612system.cpu.iew.memOrderViolationEvents 18512 # Number of memory order violations 613system.cpu.iew.predictedTakenIncorrect 15437821 # Number of branches that were predicted taken incorrectly 614system.cpu.iew.predictedNotTakenIncorrect 3784778 # Number of branches that were predicted not taken incorrectly 615system.cpu.iew.branchMispredicts 19222599 # Number of branch mispredicts detected at execute 616system.cpu.iew.iewExecutedInsts 974764839 # Number of executed instructions 617system.cpu.iew.iewExecLoadInsts 303299768 # Number of load instructions executed 618system.cpu.iew.iewExecSquashedInsts 42339224 # Number of squashed instructions skipped in execute |
| 613system.cpu.iew.exec_swp 0 # number of swp insts executed | 619system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 614system.cpu.iew.exec_nop 5552 # number of nop insts executed 615system.cpu.iew.exec_refs 497757295 # number of memory reference insts executed 616system.cpu.iew.exec_branches 150614518 # Number of branches executed 617system.cpu.iew.exec_stores 194456628 # Number of stores executed 618system.cpu.iew.exec_rate 1.194896 # Inst execution rate 619system.cpu.iew.wb_sent 963726633 # cumulative count of insts sent to commit 620system.cpu.iew.wb_count 960427202 # cumulative count of insts written-back 621system.cpu.iew.wb_producers 536683301 # num instructions producing a value 622system.cpu.iew.wb_consumers 893293358 # num instructions consuming a value | 620system.cpu.iew.exec_nop 5556 # number of nop insts executed 621system.cpu.iew.exec_refs 497763810 # number of memory reference insts executed 622system.cpu.iew.exec_branches 150614661 # Number of branches executed 623system.cpu.iew.exec_stores 194464042 # Number of stores executed 624system.cpu.iew.exec_rate 1.194456 # Inst execution rate 625system.cpu.iew.wb_sent 963735760 # cumulative count of insts sent to commit 626system.cpu.iew.wb_count 960436373 # cumulative count of insts written-back 627system.cpu.iew.wb_producers 536684839 # num instructions producing a value 628system.cpu.iew.wb_consumers 893296754 # num instructions consuming a value |
| 623system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 629system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 624system.cpu.iew.wb_rate 1.177329 # insts written-back per cycle 625system.cpu.iew.wb_fanout 0.600792 # average fanout of values written-back | 630system.cpu.iew.wb_rate 1.176898 # insts written-back per cycle 631system.cpu.iew.wb_fanout 0.600791 # average fanout of values written-back |
| 626system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 632system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 627system.cpu.commit.commitSquashedInsts 357423726 # The number of squashed insts skipped by commit | 633system.cpu.commit.commitSquashedInsts 357425480 # The number of squashed insts skipped by commit |
| 628system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards | 634system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards |
| 629system.cpu.commit.branchMispredicts 15501335 # The number of times a branch was mispredicted 630system.cpu.commit.committed_per_cycle::samples 764789514 # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::mean 1.031303 # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::stdev 1.790973 # Number of insts commited each cycle | 635system.cpu.commit.branchMispredicts 15501309 # The number of times a branch was mispredicted 636system.cpu.commit.committed_per_cycle::samples 764959828 # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::mean 1.031074 # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::stdev 1.790810 # Number of insts commited each cycle |
| 633system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 639system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 634system.cpu.commit.committed_per_cycle::0 428726988 56.06% 56.06% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::1 171833427 22.47% 78.53% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::2 73566428 9.62% 88.15% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::3 31619643 4.13% 92.28% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::4 7902471 1.03% 93.31% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::5 14889027 1.95% 95.26% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::6 7271717 0.95% 96.21% # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::7 6618968 0.87% 97.08% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::8 22360845 2.92% 100.00% # Number of insts commited each cycle | 640system.cpu.commit.committed_per_cycle::0 428887379 56.07% 56.07% # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::1 171843268 22.46% 78.53% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::2 73566556 9.62% 88.15% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::3 31622898 4.13% 92.28% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::4 7902308 1.03% 93.32% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::5 14889162 1.95% 95.26% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::6 7268582 0.95% 96.21% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::7 6618939 0.87% 97.08% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::8 22360736 2.92% 100.00% # Number of insts commited each cycle |
| 643system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 649system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 646system.cpu.commit.committed_per_cycle::total 764789514 # Number of insts commited each cycle | 652system.cpu.commit.committed_per_cycle::total 764959828 # Number of insts commited each cycle |
| 647system.cpu.commit.committedInsts 640654410 # Number of instructions committed 648system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed 649system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 650system.cpu.commit.refs 381221434 # Number of memory references committed 651system.cpu.commit.loads 252240938 # Number of loads committed 652system.cpu.commit.membars 5740 # Number of memory barriers committed 653system.cpu.commit.branches 137364859 # Number of branches committed 654system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 684system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 687system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 688system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 689system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 690system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 691system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction | 653system.cpu.commit.committedInsts 640654410 # Number of instructions committed 654system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed 655system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 656system.cpu.commit.refs 381221434 # Number of memory references committed 657system.cpu.commit.loads 252240938 # Number of loads committed 658system.cpu.commit.membars 5740 # Number of memory barriers committed 659system.cpu.commit.branches 137364859 # Number of branches committed 660system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 690system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 693system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 694system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 695system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 696system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 697system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction |
| 692system.cpu.commit.bw_lim_events 22360845 # number cycles where commit BW limit reached | 698system.cpu.commit.bw_lim_events 22360736 # number cycles where commit BW limit reached |
| 693system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 699system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 694system.cpu.rob.rob_reads 1888573713 # The number of ROB reads 695system.cpu.rob.rob_writes 2343133826 # The number of ROB writes 696system.cpu.timesIdled 646395 # Number of times that the entire CPU went into an idle state and unscheduled itself 697system.cpu.idleCycles 155573 # Total number of cycles that the CPU has spent unscheduled due to idling | 700system.cpu.rob.rob_reads 1888745890 # The number of ROB reads 701system.cpu.rob.rob_writes 2343137518 # The number of ROB writes 702system.cpu.timesIdled 647360 # Number of times that the entire CPU went into an idle state and unscheduled itself 703system.cpu.idleCycles 291908 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 698system.cpu.committedInsts 640649298 # Number of Instructions Simulated 699system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated | 704system.cpu.committedInsts 640649298 # Number of Instructions Simulated 705system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated |
| 700system.cpu.cpi 1.273345 # CPI: Cycles Per Instruction 701system.cpu.cpi_total 1.273345 # CPI: Total CPI of All Threads 702system.cpu.ipc 0.785333 # IPC: Instructions Per Cycle 703system.cpu.ipc_total 0.785333 # IPC: Total IPC of All Threads 704system.cpu.int_regfile_reads 995802642 # number of integer regfile reads 705system.cpu.int_regfile_writes 567917186 # number of integer regfile writes 706system.cpu.fp_regfile_reads 31889847 # number of floating regfile reads 707system.cpu.fp_regfile_writes 22959506 # number of floating regfile writes 708system.cpu.cc_regfile_reads 3794452598 # number of cc regfile reads 709system.cpu.cc_regfile_writes 384905504 # number of cc regfile writes 710system.cpu.misc_regfile_reads 715806131 # number of misc regfile reads | 706system.cpu.cpi 1.273824 # CPI: Cycles Per Instruction 707system.cpu.cpi_total 1.273824 # CPI: Total CPI of All Threads 708system.cpu.ipc 0.785038 # IPC: Instructions Per Cycle 709system.cpu.ipc_total 0.785038 # IPC: Total IPC of All Threads 710system.cpu.int_regfile_reads 995816176 # number of integer regfile reads 711system.cpu.int_regfile_writes 567918829 # number of integer regfile writes 712system.cpu.fp_regfile_reads 31889844 # number of floating regfile reads 713system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes 714system.cpu.cc_regfile_reads 3794477294 # number of cc regfile reads 715system.cpu.cc_regfile_writes 384905750 # number of cc regfile writes 716system.cpu.misc_regfile_reads 715814324 # number of misc regfile reads |
| 711system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes | 717system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes |
| 712system.cpu.toL2Bus.trans_dist::ReadReq 7205652 # Transaction distribution 713system.cpu.toL2Bus.trans_dist::ReadResp 7205652 # Transaction distribution 714system.cpu.toL2Bus.trans_dist::Writeback 735005 # Transaction distribution 715system.cpu.toL2Bus.trans_dist::HardPFReq 9840757 # Transaction distribution 716system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution 717system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution 718system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution 719system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution 720system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339627 # Packet count per connected master and slave (bytes) 721system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248397 # Packet count per connected master and slave (bytes) 722system.cpu.toL2Bus.pkt_count::total 16588024 # Packet count per connected master and slave (bytes) 723system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330867456 # Cumulative packet size per connected master and slave (bytes) 724system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223467584 # Cumulative packet size per connected master and slave (bytes) 725system.cpu.toL2Bus.pkt_size::total 554335040 # Cumulative packet size per connected master and slave (bytes) 726system.cpu.toL2Bus.snoops 9840776 # Total snoops (count) 727system.cpu.toL2Bus.snoop_fanout::samples 18503299 # Request fanout histogram 728system.cpu.toL2Bus.snoop_fanout::mean 5.531838 # Request fanout histogram 729system.cpu.toL2Bus.snoop_fanout::stdev 0.498985 # Request fanout histogram 730system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 731system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 732system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 733system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 734system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 735system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 736system.cpu.toL2Bus.snoop_fanout::5 8662542 46.82% 46.82% # Request fanout histogram 737system.cpu.toL2Bus.snoop_fanout::6 9840757 53.18% 100.00% # Request fanout histogram 738system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 739system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 740system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 741system.cpu.toL2Bus.snoop_fanout::total 18503299 # Request fanout histogram 742system.cpu.toL2Bus.reqLayer0.occupancy 5066671498 # Layer occupancy (ticks) 743system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 744system.cpu.toL2Bus.respLayer0.occupancy 7754858551 # Layer occupancy (ticks) 745system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 746system.cpu.toL2Bus.respLayer1.occupancy 4142472532 # Layer occupancy (ticks) 747system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 748system.cpu.icache.tags.replacements 5169293 # number of replacements 749system.cpu.icache.tags.tagsinuse 510.870067 # Cycle average of tags in use 750system.cpu.icache.tags.total_refs 364901080 # Total number of references to valid blocks. 751system.cpu.icache.tags.sampled_refs 5169803 # Sample count of references to valid blocks. 752system.cpu.icache.tags.avg_refs 70.583169 # Average number of references to valid blocks. 753system.cpu.icache.tags.warmup_cycle 199337500 # Cycle when the warmup percentage was hit. 754system.cpu.icache.tags.occ_blocks::cpu.inst 510.870067 # Average occupied blocks per requestor 755system.cpu.icache.tags.occ_percent::cpu.inst 0.997793 # Average percentage of cache occupancy 756system.cpu.icache.tags.occ_percent::total 0.997793 # Average percentage of cache occupancy 757system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 758system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 759system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id 760system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 761system.cpu.icache.tags.age_task_id_blocks_1024::4 325 # Occupied blocks per task id 762system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 763system.cpu.icache.tags.tag_accesses 745315243 # Number of tag accesses 764system.cpu.icache.tags.data_accesses 745315243 # Number of data accesses 765system.cpu.icache.ReadReq_hits::cpu.inst 364901109 # number of ReadReq hits 766system.cpu.icache.ReadReq_hits::total 364901109 # number of ReadReq hits 767system.cpu.icache.demand_hits::cpu.inst 364901109 # number of demand (read+write) hits 768system.cpu.icache.demand_hits::total 364901109 # number of demand (read+write) hits 769system.cpu.icache.overall_hits::cpu.inst 364901109 # number of overall hits 770system.cpu.icache.overall_hits::total 364901109 # number of overall hits 771system.cpu.icache.ReadReq_misses::cpu.inst 5171601 # number of ReadReq misses 772system.cpu.icache.ReadReq_misses::total 5171601 # number of ReadReq misses 773system.cpu.icache.demand_misses::cpu.inst 5171601 # number of demand (read+write) misses 774system.cpu.icache.demand_misses::total 5171601 # number of demand (read+write) misses 775system.cpu.icache.overall_misses::cpu.inst 5171601 # number of overall misses 776system.cpu.icache.overall_misses::total 5171601 # number of overall misses 777system.cpu.icache.ReadReq_miss_latency::cpu.inst 41478755019 # number of ReadReq miss cycles 778system.cpu.icache.ReadReq_miss_latency::total 41478755019 # number of ReadReq miss cycles 779system.cpu.icache.demand_miss_latency::cpu.inst 41478755019 # number of demand (read+write) miss cycles 780system.cpu.icache.demand_miss_latency::total 41478755019 # number of demand (read+write) miss cycles 781system.cpu.icache.overall_miss_latency::cpu.inst 41478755019 # number of overall miss cycles 782system.cpu.icache.overall_miss_latency::total 41478755019 # number of overall miss cycles 783system.cpu.icache.ReadReq_accesses::cpu.inst 370072710 # number of ReadReq accesses(hits+misses) 784system.cpu.icache.ReadReq_accesses::total 370072710 # number of ReadReq accesses(hits+misses) 785system.cpu.icache.demand_accesses::cpu.inst 370072710 # number of demand (read+write) accesses 786system.cpu.icache.demand_accesses::total 370072710 # number of demand (read+write) accesses 787system.cpu.icache.overall_accesses::cpu.inst 370072710 # number of overall (read+write) accesses 788system.cpu.icache.overall_accesses::total 370072710 # number of overall (read+write) accesses 789system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses 790system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses 791system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses 792system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses 793system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses 794system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses 795system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8020.486310 # average ReadReq miss latency 796system.cpu.icache.ReadReq_avg_miss_latency::total 8020.486310 # average ReadReq miss latency 797system.cpu.icache.demand_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency 798system.cpu.icache.demand_avg_miss_latency::total 8020.486310 # average overall miss latency 799system.cpu.icache.overall_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency 800system.cpu.icache.overall_avg_miss_latency::total 8020.486310 # average overall miss latency 801system.cpu.icache.blocked_cycles::no_mshrs 17792 # number of cycles access was blocked 802system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 803system.cpu.icache.blocked::no_mshrs 1782 # number of cycles access was blocked 804system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 805system.cpu.icache.avg_blocked_cycles::no_mshrs 9.984287 # average number of cycles each access was blocked 806system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 807system.cpu.icache.fast_writes 0 # number of fast writes performed 808system.cpu.icache.cache_copies 0 # number of cache copies performed 809system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1778 # number of ReadReq MSHR hits 810system.cpu.icache.ReadReq_mshr_hits::total 1778 # number of ReadReq MSHR hits 811system.cpu.icache.demand_mshr_hits::cpu.inst 1778 # number of demand (read+write) MSHR hits 812system.cpu.icache.demand_mshr_hits::total 1778 # number of demand (read+write) MSHR hits 813system.cpu.icache.overall_mshr_hits::cpu.inst 1778 # number of overall MSHR hits 814system.cpu.icache.overall_mshr_hits::total 1778 # number of overall MSHR hits 815system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169823 # number of ReadReq MSHR misses 816system.cpu.icache.ReadReq_mshr_misses::total 5169823 # number of ReadReq MSHR misses 817system.cpu.icache.demand_mshr_misses::cpu.inst 5169823 # number of demand (read+write) MSHR misses 818system.cpu.icache.demand_mshr_misses::total 5169823 # number of demand (read+write) MSHR misses 819system.cpu.icache.overall_mshr_misses::cpu.inst 5169823 # number of overall MSHR misses 820system.cpu.icache.overall_mshr_misses::total 5169823 # number of overall MSHR misses 821system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33703861415 # number of ReadReq MSHR miss cycles 822system.cpu.icache.ReadReq_mshr_miss_latency::total 33703861415 # number of ReadReq MSHR miss cycles 823system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33703861415 # number of demand (read+write) MSHR miss cycles 824system.cpu.icache.demand_mshr_miss_latency::total 33703861415 # number of demand (read+write) MSHR miss cycles 825system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33703861415 # number of overall MSHR miss cycles 826system.cpu.icache.overall_mshr_miss_latency::total 33703861415 # number of overall MSHR miss cycles 827system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses 828system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses 829system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses 830system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses 831system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses 832system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses 833system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6519.345327 # average ReadReq mshr miss latency 834system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6519.345327 # average ReadReq mshr miss latency 835system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6519.345327 # average overall mshr miss latency 836system.cpu.icache.demand_avg_mshr_miss_latency::total 6519.345327 # average overall mshr miss latency 837system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6519.345327 # average overall mshr miss latency 838system.cpu.icache.overall_avg_mshr_miss_latency::total 6519.345327 # average overall mshr miss latency 839system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 840system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 42714534 # number of hwpf identified 841system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 332916 # number of hwpf that were already in mshr 842system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 32636070 # number of hwpf that were already in the cache 843system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 18709 # number of hwpf that were already in the prefetch queue 844system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 845system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3827 # number of hwpf removed because MSHR allocated 846system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 9723012 # number of hwpf issued 847system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4810754 # number of hwpf spanning a virtual page 848system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 849system.cpu.l2cache.tags.replacements 302773 # number of replacements 850system.cpu.l2cache.tags.tagsinuse 16364.911497 # Cycle average of tags in use 851system.cpu.l2cache.tags.total_refs 7827990 # Total number of references to valid blocks. 852system.cpu.l2cache.tags.sampled_refs 319143 # Sample count of references to valid blocks. 853system.cpu.l2cache.tags.avg_refs 24.528158 # Average number of references to valid blocks. 854system.cpu.l2cache.tags.warmup_cycle 12938833000 # Cycle when the warmup percentage was hit. 855system.cpu.l2cache.tags.occ_blocks::writebacks 727.090986 # Average occupied blocks per requestor 856system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.045333 # Average occupied blocks per requestor 857system.cpu.l2cache.tags.occ_blocks::cpu.data 8487.644412 # Average occupied blocks per requestor 858system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 7101.130766 # Average occupied blocks per requestor 859system.cpu.l2cache.tags.occ_percent::writebacks 0.044378 # Average percentage of cache occupancy 860system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002993 # Average percentage of cache occupancy 861system.cpu.l2cache.tags.occ_percent::cpu.data 0.518045 # Average percentage of cache occupancy 862system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.433419 # Average percentage of cache occupancy 863system.cpu.l2cache.tags.occ_percent::total 0.998835 # Average percentage of cache occupancy 864system.cpu.l2cache.tags.occ_task_id_blocks::1022 7180 # Occupied blocks per task id 865system.cpu.l2cache.tags.occ_task_id_blocks::1024 9190 # Occupied blocks per task id 866system.cpu.l2cache.tags.age_task_id_blocks_1022::0 155 # Occupied blocks per task id 867system.cpu.l2cache.tags.age_task_id_blocks_1022::1 246 # Occupied blocks per task id 868system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id 869system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1499 # Occupied blocks per task id 870system.cpu.l2cache.tags.age_task_id_blocks_1022::4 5110 # Occupied blocks per task id 871system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 872system.cpu.l2cache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 873system.cpu.l2cache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 874system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2000 # Occupied blocks per task id 875system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6801 # Occupied blocks per task id 876system.cpu.l2cache.tags.occ_task_id_percent::1022 0.438232 # Percentage of cache occupancy per task id 877system.cpu.l2cache.tags.occ_task_id_percent::1024 0.560913 # Percentage of cache occupancy per task id 878system.cpu.l2cache.tags.tag_accesses 139624071 # Number of tag accesses 879system.cpu.l2cache.tags.data_accesses 139624071 # Number of data accesses 880system.cpu.l2cache.ReadReq_hits::cpu.inst 5168280 # number of ReadReq hits 881system.cpu.l2cache.ReadReq_hits::cpu.data 1928699 # number of ReadReq hits 882system.cpu.l2cache.ReadReq_hits::total 7096979 # number of ReadReq hits 883system.cpu.l2cache.Writeback_hits::writebacks 735005 # number of Writeback hits 884system.cpu.l2cache.Writeback_hits::total 735005 # number of Writeback hits 885system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 886system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 887system.cpu.l2cache.ReadExReq_hits::cpu.data 718110 # number of ReadExReq hits 888system.cpu.l2cache.ReadExReq_hits::total 718110 # number of ReadExReq hits 889system.cpu.l2cache.demand_hits::cpu.inst 5168280 # number of demand (read+write) hits 890system.cpu.l2cache.demand_hits::cpu.data 2646809 # number of demand (read+write) hits 891system.cpu.l2cache.demand_hits::total 7815089 # number of demand (read+write) hits 892system.cpu.l2cache.overall_hits::cpu.inst 5168280 # number of overall hits 893system.cpu.l2cache.overall_hits::cpu.data 2646809 # number of overall hits 894system.cpu.l2cache.overall_hits::total 7815089 # number of overall hits 895system.cpu.l2cache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses 896system.cpu.l2cache.ReadReq_misses::cpu.data 107130 # number of ReadReq misses 897system.cpu.l2cache.ReadReq_misses::total 108654 # number of ReadReq misses 898system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses 899system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses 900system.cpu.l2cache.ReadExReq_misses::cpu.data 2737 # number of ReadExReq misses 901system.cpu.l2cache.ReadExReq_misses::total 2737 # number of ReadExReq misses 902system.cpu.l2cache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses 903system.cpu.l2cache.demand_misses::cpu.data 109867 # number of demand (read+write) misses 904system.cpu.l2cache.demand_misses::total 111391 # number of demand (read+write) misses 905system.cpu.l2cache.overall_misses::cpu.inst 1524 # number of overall misses 906system.cpu.l2cache.overall_misses::cpu.data 109867 # number of overall misses 907system.cpu.l2cache.overall_misses::total 111391 # number of overall misses 908system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 107432161 # number of ReadReq miss cycles 909system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7354763933 # number of ReadReq miss cycles 910system.cpu.l2cache.ReadReq_miss_latency::total 7462196094 # number of ReadReq miss cycles 911system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 174400348 # number of ReadExReq miss cycles 912system.cpu.l2cache.ReadExReq_miss_latency::total 174400348 # number of ReadExReq miss cycles 913system.cpu.l2cache.demand_miss_latency::cpu.inst 107432161 # number of demand (read+write) miss cycles 914system.cpu.l2cache.demand_miss_latency::cpu.data 7529164281 # number of demand (read+write) miss cycles 915system.cpu.l2cache.demand_miss_latency::total 7636596442 # number of demand (read+write) miss cycles 916system.cpu.l2cache.overall_miss_latency::cpu.inst 107432161 # number of overall miss cycles 917system.cpu.l2cache.overall_miss_latency::cpu.data 7529164281 # number of overall miss cycles 918system.cpu.l2cache.overall_miss_latency::total 7636596442 # number of overall miss cycles 919system.cpu.l2cache.ReadReq_accesses::cpu.inst 5169804 # number of ReadReq accesses(hits+misses) 920system.cpu.l2cache.ReadReq_accesses::cpu.data 2035829 # number of ReadReq accesses(hits+misses) 921system.cpu.l2cache.ReadReq_accesses::total 7205633 # number of ReadReq accesses(hits+misses) 922system.cpu.l2cache.Writeback_accesses::writebacks 735005 # number of Writeback accesses(hits+misses) 923system.cpu.l2cache.Writeback_accesses::total 735005 # number of Writeback accesses(hits+misses) 924system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses) 925system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses) 926system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) 927system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) 928system.cpu.l2cache.demand_accesses::cpu.inst 5169804 # number of demand (read+write) accesses 929system.cpu.l2cache.demand_accesses::cpu.data 2756676 # number of demand (read+write) accesses 930system.cpu.l2cache.demand_accesses::total 7926480 # number of demand (read+write) accesses 931system.cpu.l2cache.overall_accesses::cpu.inst 5169804 # number of overall (read+write) accesses 932system.cpu.l2cache.overall_accesses::cpu.data 2756676 # number of overall (read+write) accesses 933system.cpu.l2cache.overall_accesses::total 7926480 # number of overall (read+write) accesses 934system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000295 # miss rate for ReadReq accesses 935system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.052622 # miss rate for ReadReq accesses 936system.cpu.l2cache.ReadReq_miss_rate::total 0.015079 # miss rate for ReadReq accesses 937system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.950000 # miss rate for UpgradeReq accesses 938system.cpu.l2cache.UpgradeReq_miss_rate::total 0.950000 # miss rate for UpgradeReq accesses 939system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003797 # miss rate for ReadExReq accesses 940system.cpu.l2cache.ReadExReq_miss_rate::total 0.003797 # miss rate for ReadExReq accesses 941system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000295 # miss rate for demand accesses 942system.cpu.l2cache.demand_miss_rate::cpu.data 0.039855 # miss rate for demand accesses 943system.cpu.l2cache.demand_miss_rate::total 0.014053 # miss rate for demand accesses 944system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000295 # miss rate for overall accesses 945system.cpu.l2cache.overall_miss_rate::cpu.data 0.039855 # miss rate for overall accesses 946system.cpu.l2cache.overall_miss_rate::total 0.014053 # miss rate for overall accesses 947system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70493.543963 # average ReadReq miss latency 948system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68652.701699 # average ReadReq miss latency 949system.cpu.l2cache.ReadReq_avg_miss_latency::total 68678.521674 # average ReadReq miss latency 950system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63719.527950 # average ReadExReq miss latency 951system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63719.527950 # average ReadExReq miss latency 952system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70493.543963 # average overall miss latency 953system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68529.806775 # average overall miss latency 954system.cpu.l2cache.demand_avg_miss_latency::total 68556.673717 # average overall miss latency 955system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70493.543963 # average overall miss latency 956system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68529.806775 # average overall miss latency 957system.cpu.l2cache.overall_avg_miss_latency::total 68556.673717 # average overall miss latency 958system.cpu.l2cache.blocked_cycles::no_mshrs 126545 # number of cycles access was blocked 959system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 960system.cpu.l2cache.blocked::no_mshrs 2364 # number of cycles access was blocked 961system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 962system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53.530034 # average number of cycles each access was blocked 963system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 964system.cpu.l2cache.fast_writes 0 # number of fast writes performed 965system.cpu.l2cache.cache_copies 0 # number of cache copies performed 966system.cpu.l2cache.writebacks::writebacks 66312 # number of writebacks 967system.cpu.l2cache.writebacks::total 66312 # number of writebacks 968system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 534 # number of ReadReq MSHR hits 969system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1182 # number of ReadReq MSHR hits 970system.cpu.l2cache.ReadReq_mshr_hits::total 1716 # number of ReadReq MSHR hits 971system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1379 # number of ReadExReq MSHR hits 972system.cpu.l2cache.ReadExReq_mshr_hits::total 1379 # number of ReadExReq MSHR hits 973system.cpu.l2cache.demand_mshr_hits::cpu.inst 534 # number of demand (read+write) MSHR hits 974system.cpu.l2cache.demand_mshr_hits::cpu.data 2561 # number of demand (read+write) MSHR hits 975system.cpu.l2cache.demand_mshr_hits::total 3095 # number of demand (read+write) MSHR hits 976system.cpu.l2cache.overall_mshr_hits::cpu.inst 534 # number of overall MSHR hits 977system.cpu.l2cache.overall_mshr_hits::cpu.data 2561 # number of overall MSHR hits 978system.cpu.l2cache.overall_mshr_hits::total 3095 # number of overall MSHR hits 979system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 990 # number of ReadReq MSHR misses 980system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 105948 # number of ReadReq MSHR misses 981system.cpu.l2cache.ReadReq_mshr_misses::total 106938 # number of ReadReq MSHR misses 982system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 9723012 # number of HardPFReq MSHR misses 983system.cpu.l2cache.HardPFReq_mshr_misses::total 9723012 # number of HardPFReq MSHR misses 984system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses 985system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses 986system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1358 # number of ReadExReq MSHR misses 987system.cpu.l2cache.ReadExReq_mshr_misses::total 1358 # number of ReadExReq MSHR misses 988system.cpu.l2cache.demand_mshr_misses::cpu.inst 990 # number of demand (read+write) MSHR misses 989system.cpu.l2cache.demand_mshr_misses::cpu.data 107306 # number of demand (read+write) MSHR misses 990system.cpu.l2cache.demand_mshr_misses::total 108296 # number of demand (read+write) MSHR misses 991system.cpu.l2cache.overall_mshr_misses::cpu.inst 990 # number of overall MSHR misses 992system.cpu.l2cache.overall_mshr_misses::cpu.data 107306 # number of overall MSHR misses 993system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 9723012 # number of overall MSHR misses 994system.cpu.l2cache.overall_mshr_misses::total 9831308 # number of overall MSHR misses 995system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71873499 # number of ReadReq MSHR miss cycles 996system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6404181248 # number of ReadReq MSHR miss cycles 997system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6476054747 # number of ReadReq MSHR miss cycles 998system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19431970184 # number of HardPFReq MSHR miss cycles 999system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19431970184 # number of HardPFReq MSHR miss cycles 1000system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 143518 # number of UpgradeReq MSHR miss cycles 1001system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 143518 # number of UpgradeReq MSHR miss cycles 1002system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92793756 # number of ReadExReq MSHR miss cycles 1003system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92793756 # number of ReadExReq MSHR miss cycles 1004system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71873499 # number of demand (read+write) MSHR miss cycles 1005system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6496975004 # number of demand (read+write) MSHR miss cycles 1006system.cpu.l2cache.demand_mshr_miss_latency::total 6568848503 # number of demand (read+write) MSHR miss cycles 1007system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71873499 # number of overall MSHR miss cycles 1008system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6496975004 # number of overall MSHR miss cycles 1009system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19431970184 # number of overall MSHR miss cycles 1010system.cpu.l2cache.overall_mshr_miss_latency::total 26000818687 # number of overall MSHR miss cycles 1011system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for ReadReq accesses 1012system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.052042 # mshr miss rate for ReadReq accesses 1013system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.014841 # mshr miss rate for ReadReq accesses 1014system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1015system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1016system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.950000 # mshr miss rate for UpgradeReq accesses 1017system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.950000 # mshr miss rate for UpgradeReq accesses 1018system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadExReq accesses 1019system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadExReq accesses 1020system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for demand accesses 1021system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for demand accesses 1022system.cpu.l2cache.demand_mshr_miss_rate::total 0.013663 # mshr miss rate for demand accesses 1023system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for overall accesses 1024system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for overall accesses 1025system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1026system.cpu.l2cache.overall_mshr_miss_rate::total 1.240312 # mshr miss rate for overall accesses 1027system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72599.493939 # average ReadReq mshr miss latency 1028system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60446.457205 # average ReadReq mshr miss latency 1029system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60558.966382 # average ReadReq mshr miss latency 1030system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average HardPFReq mshr miss latency 1031system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 1998.554582 # average HardPFReq mshr miss latency 1032system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 7553.578947 # average UpgradeReq mshr miss latency 1033system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 7553.578947 # average UpgradeReq mshr miss latency 1034system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68331.189985 # average ReadExReq mshr miss latency 1035system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68331.189985 # average ReadExReq mshr miss latency 1036system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency 1037system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency 1038system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.427781 # average overall mshr miss latency 1039system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency 1040system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency 1041system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average overall mshr miss latency 1042system.cpu.l2cache.overall_avg_mshr_miss_latency::total 2644.695771 # average overall mshr miss latency 1043system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1044system.cpu.dcache.tags.replacements 2756164 # number of replacements 1045system.cpu.dcache.tags.tagsinuse 511.948880 # Cycle average of tags in use 1046system.cpu.dcache.tags.total_refs 414248795 # Total number of references to valid blocks. 1047system.cpu.dcache.tags.sampled_refs 2756676 # Sample count of references to valid blocks. 1048system.cpu.dcache.tags.avg_refs 150.271122 # Average number of references to valid blocks. 1049system.cpu.dcache.tags.warmup_cycle 207459500 # Cycle when the warmup percentage was hit. 1050system.cpu.dcache.tags.occ_blocks::cpu.data 511.948880 # Average occupied blocks per requestor 1051system.cpu.dcache.tags.occ_percent::cpu.data 0.999900 # Average percentage of cache occupancy 1052system.cpu.dcache.tags.occ_percent::total 0.999900 # Average percentage of cache occupancy | 718system.cpu.dcache.tags.replacements 2756166 # number of replacements 719system.cpu.dcache.tags.tagsinuse 511.936576 # Cycle average of tags in use 720system.cpu.dcache.tags.total_refs 414250087 # Total number of references to valid blocks. 721system.cpu.dcache.tags.sampled_refs 2756678 # Sample count of references to valid blocks. 722system.cpu.dcache.tags.avg_refs 150.271481 # Average number of references to valid blocks. 723system.cpu.dcache.tags.warmup_cycle 246939500 # Cycle when the warmup percentage was hit. 724system.cpu.dcache.tags.occ_blocks::cpu.data 511.936576 # Average occupied blocks per requestor 725system.cpu.dcache.tags.occ_percent::cpu.data 0.999876 # Average percentage of cache occupancy 726system.cpu.dcache.tags.occ_percent::total 0.999876 # Average percentage of cache occupancy |
| 1053system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 727system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1054system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 1055system.cpu.dcache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id 1056system.cpu.dcache.tags.age_task_id_blocks_1024::2 187 # Occupied blocks per task id | 728system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 729system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id 730system.cpu.dcache.tags.age_task_id_blocks_1024::2 189 # Occupied blocks per task id |
| 1057system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 1058system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 731system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 732system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1059system.cpu.dcache.tags.tag_accesses 839347154 # Number of tag accesses 1060system.cpu.dcache.tags.data_accesses 839347154 # Number of data accesses 1061system.cpu.dcache.ReadReq_hits::cpu.data 286297439 # number of ReadReq hits 1062system.cpu.dcache.ReadReq_hits::total 286297439 # number of ReadReq hits 1063system.cpu.dcache.WriteReq_hits::cpu.data 127936631 # number of WriteReq hits 1064system.cpu.dcache.WriteReq_hits::total 127936631 # number of WriteReq hits 1065system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits 1066system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits | 733system.cpu.dcache.tags.tag_accesses 839347788 # Number of tag accesses 734system.cpu.dcache.tags.data_accesses 839347788 # Number of data accesses 735system.cpu.dcache.ReadReq_hits::cpu.data 286297988 # number of ReadReq hits 736system.cpu.dcache.ReadReq_hits::total 286297988 # number of ReadReq hits 737system.cpu.dcache.WriteReq_hits::cpu.data 127937398 # number of WriteReq hits 738system.cpu.dcache.WriteReq_hits::total 127937398 # number of WriteReq hits 739system.cpu.dcache.SoftPFReq_hits::cpu.data 3156 # number of SoftPFReq hits 740system.cpu.dcache.SoftPFReq_hits::total 3156 # number of SoftPFReq hits |
| 1067system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits 1068system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits 1069system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 1070system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits | 741system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits 742system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits 743system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 744system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits |
| 1071system.cpu.dcache.demand_hits::cpu.data 414234070 # number of demand (read+write) hits 1072system.cpu.dcache.demand_hits::total 414234070 # number of demand (read+write) hits 1073system.cpu.dcache.overall_hits::cpu.data 414237227 # number of overall hits 1074system.cpu.dcache.overall_hits::total 414237227 # number of overall hits 1075system.cpu.dcache.ReadReq_misses::cpu.data 3031039 # number of ReadReq misses 1076system.cpu.dcache.ReadReq_misses::total 3031039 # number of ReadReq misses 1077system.cpu.dcache.WriteReq_misses::cpu.data 1014846 # number of WriteReq misses 1078system.cpu.dcache.WriteReq_misses::total 1014846 # number of WriteReq misses 1079system.cpu.dcache.SoftPFReq_misses::cpu.data 648 # number of SoftPFReq misses 1080system.cpu.dcache.SoftPFReq_misses::total 648 # number of SoftPFReq misses | 745system.cpu.dcache.demand_hits::cpu.data 414235386 # number of demand (read+write) hits 746system.cpu.dcache.demand_hits::total 414235386 # number of demand (read+write) hits 747system.cpu.dcache.overall_hits::cpu.data 414238542 # number of overall hits 748system.cpu.dcache.overall_hits::total 414238542 # number of overall hits 749system.cpu.dcache.ReadReq_misses::cpu.data 3030809 # number of ReadReq misses 750system.cpu.dcache.ReadReq_misses::total 3030809 # number of ReadReq misses 751system.cpu.dcache.WriteReq_misses::cpu.data 1014079 # number of WriteReq misses 752system.cpu.dcache.WriteReq_misses::total 1014079 # number of WriteReq misses 753system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses 754system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses |
| 1081system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 1082system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses | 755system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 756system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses |
| 1083system.cpu.dcache.demand_misses::cpu.data 4045885 # number of demand (read+write) misses 1084system.cpu.dcache.demand_misses::total 4045885 # number of demand (read+write) misses 1085system.cpu.dcache.overall_misses::cpu.data 4046533 # number of overall misses 1086system.cpu.dcache.overall_misses::total 4046533 # number of overall misses 1087system.cpu.dcache.ReadReq_miss_latency::cpu.data 33719933619 # number of ReadReq miss cycles 1088system.cpu.dcache.ReadReq_miss_latency::total 33719933619 # number of ReadReq miss cycles 1089system.cpu.dcache.WriteReq_miss_latency::cpu.data 9704111685 # number of WriteReq miss cycles 1090system.cpu.dcache.WriteReq_miss_latency::total 9704111685 # number of WriteReq miss cycles 1091system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 169500 # number of LoadLockedReq miss cycles 1092system.cpu.dcache.LoadLockedReq_miss_latency::total 169500 # number of LoadLockedReq miss cycles 1093system.cpu.dcache.demand_miss_latency::cpu.data 43424045304 # number of demand (read+write) miss cycles 1094system.cpu.dcache.demand_miss_latency::total 43424045304 # number of demand (read+write) miss cycles 1095system.cpu.dcache.overall_miss_latency::cpu.data 43424045304 # number of overall miss cycles 1096system.cpu.dcache.overall_miss_latency::total 43424045304 # number of overall miss cycles 1097system.cpu.dcache.ReadReq_accesses::cpu.data 289328478 # number of ReadReq accesses(hits+misses) 1098system.cpu.dcache.ReadReq_accesses::total 289328478 # number of ReadReq accesses(hits+misses) | 757system.cpu.dcache.demand_misses::cpu.data 4044888 # number of demand (read+write) misses 758system.cpu.dcache.demand_misses::total 4044888 # number of demand (read+write) misses 759system.cpu.dcache.overall_misses::cpu.data 4045534 # number of overall misses 760system.cpu.dcache.overall_misses::total 4045534 # number of overall misses 761system.cpu.dcache.ReadReq_miss_latency::cpu.data 33766010929 # number of ReadReq miss cycles 762system.cpu.dcache.ReadReq_miss_latency::total 33766010929 # number of ReadReq miss cycles 763system.cpu.dcache.WriteReq_miss_latency::cpu.data 9872401734 # number of WriteReq miss cycles 764system.cpu.dcache.WriteReq_miss_latency::total 9872401734 # number of WriteReq miss cycles 765system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 175500 # number of LoadLockedReq miss cycles 766system.cpu.dcache.LoadLockedReq_miss_latency::total 175500 # number of LoadLockedReq miss cycles 767system.cpu.dcache.demand_miss_latency::cpu.data 43638412663 # number of demand (read+write) miss cycles 768system.cpu.dcache.demand_miss_latency::total 43638412663 # number of demand (read+write) miss cycles 769system.cpu.dcache.overall_miss_latency::cpu.data 43638412663 # number of overall miss cycles 770system.cpu.dcache.overall_miss_latency::total 43638412663 # number of overall miss cycles 771system.cpu.dcache.ReadReq_accesses::cpu.data 289328797 # number of ReadReq accesses(hits+misses) 772system.cpu.dcache.ReadReq_accesses::total 289328797 # number of ReadReq accesses(hits+misses) |
| 1099system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 1100system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) | 773system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 774system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) |
| 1101system.cpu.dcache.SoftPFReq_accesses::cpu.data 3805 # number of SoftPFReq accesses(hits+misses) 1102system.cpu.dcache.SoftPFReq_accesses::total 3805 # number of SoftPFReq accesses(hits+misses) | 775system.cpu.dcache.SoftPFReq_accesses::cpu.data 3802 # number of SoftPFReq accesses(hits+misses) 776system.cpu.dcache.SoftPFReq_accesses::total 3802 # number of SoftPFReq accesses(hits+misses) |
| 1103system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) 1104system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) 1105system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 1106system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) | 777system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) 778system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) 779system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 780system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) |
| 1107system.cpu.dcache.demand_accesses::cpu.data 418279955 # number of demand (read+write) accesses 1108system.cpu.dcache.demand_accesses::total 418279955 # number of demand (read+write) accesses 1109system.cpu.dcache.overall_accesses::cpu.data 418283760 # number of overall (read+write) accesses 1110system.cpu.dcache.overall_accesses::total 418283760 # number of overall (read+write) accesses 1111system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010476 # miss rate for ReadReq accesses 1112system.cpu.dcache.ReadReq_miss_rate::total 0.010476 # miss rate for ReadReq accesses 1113system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007870 # miss rate for WriteReq accesses 1114system.cpu.dcache.WriteReq_miss_rate::total 0.007870 # miss rate for WriteReq accesses 1115system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170302 # miss rate for SoftPFReq accesses 1116system.cpu.dcache.SoftPFReq_miss_rate::total 0.170302 # miss rate for SoftPFReq accesses | 781system.cpu.dcache.demand_accesses::cpu.data 418280274 # number of demand (read+write) accesses 782system.cpu.dcache.demand_accesses::total 418280274 # number of demand (read+write) accesses 783system.cpu.dcache.overall_accesses::cpu.data 418284076 # number of overall (read+write) accesses 784system.cpu.dcache.overall_accesses::total 418284076 # number of overall (read+write) accesses 785system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010475 # miss rate for ReadReq accesses 786system.cpu.dcache.ReadReq_miss_rate::total 0.010475 # miss rate for ReadReq accesses 787system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007864 # miss rate for WriteReq accesses 788system.cpu.dcache.WriteReq_miss_rate::total 0.007864 # miss rate for WriteReq accesses 789system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169911 # miss rate for SoftPFReq accesses 790system.cpu.dcache.SoftPFReq_miss_rate::total 0.169911 # miss rate for SoftPFReq accesses |
| 1117system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 1118system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses | 791system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 792system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses |
| 1119system.cpu.dcache.demand_miss_rate::cpu.data 0.009673 # miss rate for demand accesses 1120system.cpu.dcache.demand_miss_rate::total 0.009673 # miss rate for demand accesses 1121system.cpu.dcache.overall_miss_rate::cpu.data 0.009674 # miss rate for overall accesses 1122system.cpu.dcache.overall_miss_rate::total 0.009674 # miss rate for overall accesses 1123system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11124.876196 # average ReadReq miss latency 1124system.cpu.dcache.ReadReq_avg_miss_latency::total 11124.876196 # average ReadReq miss latency 1125system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9562.151977 # average WriteReq miss latency 1126system.cpu.dcache.WriteReq_avg_miss_latency::total 9562.151977 # average WriteReq miss latency 1127system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56500 # average LoadLockedReq miss latency 1128system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56500 # average LoadLockedReq miss latency 1129system.cpu.dcache.demand_avg_miss_latency::cpu.data 10732.891643 # average overall miss latency 1130system.cpu.dcache.demand_avg_miss_latency::total 10732.891643 # average overall miss latency 1131system.cpu.dcache.overall_avg_miss_latency::cpu.data 10731.172909 # average overall miss latency 1132system.cpu.dcache.overall_avg_miss_latency::total 10731.172909 # average overall miss latency 1133system.cpu.dcache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked 1134system.cpu.dcache.blocked_cycles::no_targets 339239 # number of cycles access was blocked 1135system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 1136system.cpu.dcache.blocked::no_targets 5513 # number of cycles access was blocked 1137system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked 1138system.cpu.dcache.avg_blocked_cycles::no_targets 61.534373 # average number of cycles each access was blocked | 793system.cpu.dcache.demand_miss_rate::cpu.data 0.009670 # miss rate for demand accesses 794system.cpu.dcache.demand_miss_rate::total 0.009670 # miss rate for demand accesses 795system.cpu.dcache.overall_miss_rate::cpu.data 0.009672 # miss rate for overall accesses 796system.cpu.dcache.overall_miss_rate::total 0.009672 # miss rate for overall accesses 797system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11140.923407 # average ReadReq miss latency 798system.cpu.dcache.ReadReq_avg_miss_latency::total 11140.923407 # average ReadReq miss latency 799system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9735.337912 # average WriteReq miss latency 800system.cpu.dcache.WriteReq_avg_miss_latency::total 9735.337912 # average WriteReq miss latency 801system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58500 # average LoadLockedReq miss latency 802system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58500 # average LoadLockedReq miss latency 803system.cpu.dcache.demand_avg_miss_latency::cpu.data 10788.534235 # average overall miss latency 804system.cpu.dcache.demand_avg_miss_latency::total 10788.534235 # average overall miss latency 805system.cpu.dcache.overall_avg_miss_latency::cpu.data 10786.811497 # average overall miss latency 806system.cpu.dcache.overall_avg_miss_latency::total 10786.811497 # average overall miss latency 807system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 808system.cpu.dcache.blocked_cycles::no_targets 383706 # number of cycles access was blocked 809system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 810system.cpu.dcache.blocked::no_targets 5260 # number of cycles access was blocked 811system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 812system.cpu.dcache.avg_blocked_cycles::no_targets 72.947909 # average number of cycles each access was blocked |
| 1139system.cpu.dcache.fast_writes 0 # number of fast writes performed 1140system.cpu.dcache.cache_copies 0 # number of cache copies performed | 813system.cpu.dcache.fast_writes 0 # number of fast writes performed 814system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1141system.cpu.dcache.writebacks::writebacks 735005 # number of writebacks 1142system.cpu.dcache.writebacks::total 735005 # number of writebacks 1143system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995853 # number of ReadReq MSHR hits 1144system.cpu.dcache.ReadReq_mshr_hits::total 995853 # number of ReadReq MSHR hits 1145system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293979 # number of WriteReq MSHR hits 1146system.cpu.dcache.WriteReq_mshr_hits::total 293979 # number of WriteReq MSHR hits | 815system.cpu.dcache.writebacks::writebacks 735128 # number of writebacks 816system.cpu.dcache.writebacks::total 735128 # number of writebacks 817system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995619 # number of ReadReq MSHR hits 818system.cpu.dcache.ReadReq_mshr_hits::total 995619 # number of ReadReq MSHR hits 819system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293215 # number of WriteReq MSHR hits 820system.cpu.dcache.WriteReq_mshr_hits::total 293215 # number of WriteReq MSHR hits |
| 1147system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 1148system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits | 821system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 822system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits |
| 1149system.cpu.dcache.demand_mshr_hits::cpu.data 1289832 # number of demand (read+write) MSHR hits 1150system.cpu.dcache.demand_mshr_hits::total 1289832 # number of demand (read+write) MSHR hits 1151system.cpu.dcache.overall_mshr_hits::cpu.data 1289832 # number of overall MSHR hits 1152system.cpu.dcache.overall_mshr_hits::total 1289832 # number of overall MSHR hits 1153system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035186 # number of ReadReq MSHR misses 1154system.cpu.dcache.ReadReq_mshr_misses::total 2035186 # number of ReadReq MSHR misses 1155system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720867 # number of WriteReq MSHR misses 1156system.cpu.dcache.WriteReq_mshr_misses::total 720867 # number of WriteReq MSHR misses 1157system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 643 # number of SoftPFReq MSHR misses 1158system.cpu.dcache.SoftPFReq_mshr_misses::total 643 # number of SoftPFReq MSHR misses 1159system.cpu.dcache.demand_mshr_misses::cpu.data 2756053 # number of demand (read+write) MSHR misses 1160system.cpu.dcache.demand_mshr_misses::total 2756053 # number of demand (read+write) MSHR misses 1161system.cpu.dcache.overall_mshr_misses::cpu.data 2756696 # number of overall MSHR misses 1162system.cpu.dcache.overall_mshr_misses::total 2756696 # number of overall MSHR misses 1163system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20990186992 # number of ReadReq MSHR miss cycles 1164system.cpu.dcache.ReadReq_mshr_miss_latency::total 20990186992 # number of ReadReq MSHR miss cycles 1165system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5237168826 # number of WriteReq MSHR miss cycles 1166system.cpu.dcache.WriteReq_mshr_miss_latency::total 5237168826 # number of WriteReq MSHR miss cycles 1167system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5228000 # number of SoftPFReq MSHR miss cycles 1168system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5228000 # number of SoftPFReq MSHR miss cycles 1169system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26227355818 # number of demand (read+write) MSHR miss cycles 1170system.cpu.dcache.demand_mshr_miss_latency::total 26227355818 # number of demand (read+write) MSHR miss cycles 1171system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26232583818 # number of overall MSHR miss cycles 1172system.cpu.dcache.overall_mshr_miss_latency::total 26232583818 # number of overall MSHR miss cycles | 823system.cpu.dcache.demand_mshr_hits::cpu.data 1288834 # number of demand (read+write) MSHR hits 824system.cpu.dcache.demand_mshr_hits::total 1288834 # number of demand (read+write) MSHR hits 825system.cpu.dcache.overall_mshr_hits::cpu.data 1288834 # number of overall MSHR hits 826system.cpu.dcache.overall_mshr_hits::total 1288834 # number of overall MSHR hits 827system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035190 # number of ReadReq MSHR misses 828system.cpu.dcache.ReadReq_mshr_misses::total 2035190 # number of ReadReq MSHR misses 829system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses 830system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses 831system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses 832system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses 833system.cpu.dcache.demand_mshr_misses::cpu.data 2756054 # number of demand (read+write) MSHR misses 834system.cpu.dcache.demand_mshr_misses::total 2756054 # number of demand (read+write) MSHR misses 835system.cpu.dcache.overall_mshr_misses::cpu.data 2756695 # number of overall MSHR misses 836system.cpu.dcache.overall_mshr_misses::total 2756695 # number of overall MSHR misses 837system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21052594116 # number of ReadReq MSHR miss cycles 838system.cpu.dcache.ReadReq_mshr_miss_latency::total 21052594116 # number of ReadReq MSHR miss cycles 839system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5256752100 # number of WriteReq MSHR miss cycles 840system.cpu.dcache.WriteReq_mshr_miss_latency::total 5256752100 # number of WriteReq MSHR miss cycles 841system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5684476 # number of SoftPFReq MSHR miss cycles 842system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5684476 # number of SoftPFReq MSHR miss cycles 843system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26309346216 # number of demand (read+write) MSHR miss cycles 844system.cpu.dcache.demand_mshr_miss_latency::total 26309346216 # number of demand (read+write) MSHR miss cycles 845system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26315030692 # number of overall MSHR miss cycles 846system.cpu.dcache.overall_mshr_miss_latency::total 26315030692 # number of overall MSHR miss cycles |
| 1173system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses 1174system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses 1175system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses 1176system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses | 847system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses 848system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses 849system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses 850system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses |
| 1177system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168988 # mshr miss rate for SoftPFReq accesses 1178system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168988 # mshr miss rate for SoftPFReq accesses | 851system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168595 # mshr miss rate for SoftPFReq accesses 852system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168595 # mshr miss rate for SoftPFReq accesses |
| 1179system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses 1180system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses 1181system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses 1182system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses | 853system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses 854system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses 855system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses 856system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses |
| 1183system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10313.645530 # average ReadReq mshr miss latency 1184system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10313.645530 # average ReadReq mshr miss latency 1185system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7265.097204 # average WriteReq mshr miss latency 1186system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7265.097204 # average WriteReq mshr miss latency 1187system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8130.637636 # average SoftPFReq mshr miss latency 1188system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8130.637636 # average SoftPFReq mshr miss latency 1189system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9516.274113 # average overall mshr miss latency 1190system.cpu.dcache.demand_avg_mshr_miss_latency::total 9516.274113 # average overall mshr miss latency 1191system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9515.950913 # average overall mshr miss latency 1192system.cpu.dcache.overall_avg_mshr_miss_latency::total 9515.950913 # average overall mshr miss latency | 857system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10344.289288 # average ReadReq mshr miss latency 858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10344.289288 # average ReadReq mshr miss latency 859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7292.293831 # average WriteReq mshr miss latency 860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7292.293831 # average WriteReq mshr miss latency 861system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8868.137285 # average SoftPFReq mshr miss latency 862system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8868.137285 # average SoftPFReq mshr miss latency 863system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9546.019859 # average overall mshr miss latency 864system.cpu.dcache.demand_avg_mshr_miss_latency::total 9546.019859 # average overall mshr miss latency 865system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9545.862234 # average overall mshr miss latency 866system.cpu.dcache.overall_avg_mshr_miss_latency::total 9545.862234 # average overall mshr miss latency |
| 1193system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 867system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 868system.cpu.icache.tags.replacements 5169210 # number of replacements 869system.cpu.icache.tags.tagsinuse 510.721915 # Cycle average of tags in use 870system.cpu.icache.tags.total_refs 364899992 # Total number of references to valid blocks. 871system.cpu.icache.tags.sampled_refs 5169720 # Sample count of references to valid blocks. 872system.cpu.icache.tags.avg_refs 70.584092 # Average number of references to valid blocks. 873system.cpu.icache.tags.warmup_cycle 237857250 # Cycle when the warmup percentage was hit. 874system.cpu.icache.tags.occ_blocks::cpu.inst 510.721915 # Average occupied blocks per requestor 875system.cpu.icache.tags.occ_percent::cpu.inst 0.997504 # Average percentage of cache occupancy 876system.cpu.icache.tags.occ_percent::total 0.997504 # Average percentage of cache occupancy 877system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 878system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 879system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 880system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 881system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id 882system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 883system.cpu.icache.tags.tag_accesses 745313375 # Number of tag accesses 884system.cpu.icache.tags.data_accesses 745313375 # Number of data accesses 885system.cpu.icache.ReadReq_hits::cpu.inst 364900028 # number of ReadReq hits 886system.cpu.icache.ReadReq_hits::total 364900028 # number of ReadReq hits 887system.cpu.icache.demand_hits::cpu.inst 364900028 # number of demand (read+write) hits 888system.cpu.icache.demand_hits::total 364900028 # number of demand (read+write) hits 889system.cpu.icache.overall_hits::cpu.inst 364900028 # number of overall hits 890system.cpu.icache.overall_hits::total 364900028 # number of overall hits 891system.cpu.icache.ReadReq_misses::cpu.inst 5171791 # number of ReadReq misses 892system.cpu.icache.ReadReq_misses::total 5171791 # number of ReadReq misses 893system.cpu.icache.demand_misses::cpu.inst 5171791 # number of demand (read+write) misses 894system.cpu.icache.demand_misses::total 5171791 # number of demand (read+write) misses 895system.cpu.icache.overall_misses::cpu.inst 5171791 # number of overall misses 896system.cpu.icache.overall_misses::total 5171791 # number of overall misses 897system.cpu.icache.ReadReq_miss_latency::cpu.inst 41611685167 # number of ReadReq miss cycles 898system.cpu.icache.ReadReq_miss_latency::total 41611685167 # number of ReadReq miss cycles 899system.cpu.icache.demand_miss_latency::cpu.inst 41611685167 # number of demand (read+write) miss cycles 900system.cpu.icache.demand_miss_latency::total 41611685167 # number of demand (read+write) miss cycles 901system.cpu.icache.overall_miss_latency::cpu.inst 41611685167 # number of overall miss cycles 902system.cpu.icache.overall_miss_latency::total 41611685167 # number of overall miss cycles 903system.cpu.icache.ReadReq_accesses::cpu.inst 370071819 # number of ReadReq accesses(hits+misses) 904system.cpu.icache.ReadReq_accesses::total 370071819 # number of ReadReq accesses(hits+misses) 905system.cpu.icache.demand_accesses::cpu.inst 370071819 # number of demand (read+write) accesses 906system.cpu.icache.demand_accesses::total 370071819 # number of demand (read+write) accesses 907system.cpu.icache.overall_accesses::cpu.inst 370071819 # number of overall (read+write) accesses 908system.cpu.icache.overall_accesses::total 370071819 # number of overall (read+write) accesses 909system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses 910system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses 911system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses 912system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses 913system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses 914system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses 915system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8045.894578 # average ReadReq miss latency 916system.cpu.icache.ReadReq_avg_miss_latency::total 8045.894578 # average ReadReq miss latency 917system.cpu.icache.demand_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency 918system.cpu.icache.demand_avg_miss_latency::total 8045.894578 # average overall miss latency 919system.cpu.icache.overall_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency 920system.cpu.icache.overall_avg_miss_latency::total 8045.894578 # average overall miss latency 921system.cpu.icache.blocked_cycles::no_mshrs 67339 # number of cycles access was blocked 922system.cpu.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked 923system.cpu.icache.blocked::no_mshrs 2239 # number of cycles access was blocked 924system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked 925system.cpu.icache.avg_blocked_cycles::no_mshrs 30.075480 # average number of cycles each access was blocked 926system.cpu.icache.avg_blocked_cycles::no_targets 9.750000 # average number of cycles each access was blocked 927system.cpu.icache.fast_writes 0 # number of fast writes performed 928system.cpu.icache.cache_copies 0 # number of cache copies performed 929system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits 930system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits 931system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits 932system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits 933system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits 934system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits 935system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169737 # number of ReadReq MSHR misses 936system.cpu.icache.ReadReq_mshr_misses::total 5169737 # number of ReadReq MSHR misses 937system.cpu.icache.demand_mshr_misses::cpu.inst 5169737 # number of demand (read+write) MSHR misses 938system.cpu.icache.demand_mshr_misses::total 5169737 # number of demand (read+write) MSHR misses 939system.cpu.icache.overall_mshr_misses::cpu.inst 5169737 # number of overall MSHR misses 940system.cpu.icache.overall_mshr_misses::total 5169737 # number of overall MSHR misses 941system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33819004202 # number of ReadReq MSHR miss cycles 942system.cpu.icache.ReadReq_mshr_miss_latency::total 33819004202 # number of ReadReq MSHR miss cycles 943system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33819004202 # number of demand (read+write) MSHR miss cycles 944system.cpu.icache.demand_mshr_miss_latency::total 33819004202 # number of demand (read+write) MSHR miss cycles 945system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33819004202 # number of overall MSHR miss cycles 946system.cpu.icache.overall_mshr_miss_latency::total 33819004202 # number of overall MSHR miss cycles 947system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses 948system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses 949system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses 950system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses 951system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses 952system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses 953system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6541.726243 # average ReadReq mshr miss latency 954system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6541.726243 # average ReadReq mshr miss latency 955system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency 956system.cpu.icache.demand_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency 957system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency 958system.cpu.icache.overall_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency 959system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 960system.cpu.l2cache.prefetcher.num_hwpf_issued 1345350 # number of hwpf issued 961system.cpu.l2cache.prefetcher.pfIdentified 1355301 # number of prefetch candidates identified 962system.cpu.l2cache.prefetcher.pfBufferHit 8714 # number of redundant prefetches already in prefetch queue 963system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 964system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 965system.cpu.l2cache.prefetcher.pfSpanPage 4790331 # number of prefetches not generated due to page crossing 966system.cpu.l2cache.tags.replacements 298968 # number of replacements 967system.cpu.l2cache.tags.tagsinuse 16361.863198 # Cycle average of tags in use 968system.cpu.l2cache.tags.total_refs 7823723 # Total number of references to valid blocks. 969system.cpu.l2cache.tags.sampled_refs 315332 # Sample count of references to valid blocks. 970system.cpu.l2cache.tags.avg_refs 24.811066 # Average number of references to valid blocks. 971system.cpu.l2cache.tags.warmup_cycle 13372026000 # Cycle when the warmup percentage was hit. 972system.cpu.l2cache.tags.occ_blocks::writebacks 741.351492 # Average occupied blocks per requestor 973system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.669964 # Average occupied blocks per requestor 974system.cpu.l2cache.tags.occ_blocks::cpu.data 8767.936523 # Average occupied blocks per requestor 975system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6722.905220 # Average occupied blocks per requestor 976system.cpu.l2cache.tags.occ_percent::writebacks 0.045249 # Average percentage of cache occupancy 977system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007914 # Average percentage of cache occupancy 978system.cpu.l2cache.tags.occ_percent::cpu.data 0.535152 # Average percentage of cache occupancy 979system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410334 # Average percentage of cache occupancy 980system.cpu.l2cache.tags.occ_percent::total 0.998649 # Average percentage of cache occupancy 981system.cpu.l2cache.tags.occ_task_id_blocks::1022 6534 # Occupied blocks per task id 982system.cpu.l2cache.tags.occ_task_id_blocks::1024 9830 # Occupied blocks per task id 983system.cpu.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 984system.cpu.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1473 # Occupied blocks per task id 986system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4885 # Occupied blocks per task id 987system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 988system.cpu.l2cache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2092 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7253 # Occupied blocks per task id 992system.cpu.l2cache.tags.occ_task_id_percent::1022 0.398804 # Percentage of cache occupancy per task id 993system.cpu.l2cache.tags.occ_task_id_percent::1024 0.599976 # Percentage of cache occupancy per task id 994system.cpu.l2cache.tags.tag_accesses 139620886 # Number of tag accesses 995system.cpu.l2cache.tags.data_accesses 139620886 # Number of data accesses 996system.cpu.l2cache.ReadReq_hits::cpu.inst 5166160 # number of ReadReq hits 997system.cpu.l2cache.ReadReq_hits::cpu.data 1926359 # number of ReadReq hits 998system.cpu.l2cache.ReadReq_hits::total 7092519 # number of ReadReq hits 999system.cpu.l2cache.Writeback_hits::writebacks 735128 # number of Writeback hits 1000system.cpu.l2cache.Writeback_hits::total 735128 # number of Writeback hits 1001system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 1002system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 1003system.cpu.l2cache.ReadExReq_hits::cpu.data 717996 # number of ReadExReq hits 1004system.cpu.l2cache.ReadExReq_hits::total 717996 # number of ReadExReq hits 1005system.cpu.l2cache.demand_hits::cpu.inst 5166160 # number of demand (read+write) hits 1006system.cpu.l2cache.demand_hits::cpu.data 2644355 # number of demand (read+write) hits 1007system.cpu.l2cache.demand_hits::total 7810515 # number of demand (read+write) hits 1008system.cpu.l2cache.overall_hits::cpu.inst 5166160 # number of overall hits 1009system.cpu.l2cache.overall_hits::cpu.data 2644355 # number of overall hits 1010system.cpu.l2cache.overall_hits::total 7810515 # number of overall hits 1011system.cpu.l2cache.ReadReq_misses::cpu.inst 3561 # number of ReadReq misses 1012system.cpu.l2cache.ReadReq_misses::cpu.data 109472 # number of ReadReq misses 1013system.cpu.l2cache.ReadReq_misses::total 113033 # number of ReadReq misses 1014system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses 1015system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses 1016system.cpu.l2cache.ReadExReq_misses::cpu.data 2851 # number of ReadExReq misses 1017system.cpu.l2cache.ReadExReq_misses::total 2851 # number of ReadExReq misses 1018system.cpu.l2cache.demand_misses::cpu.inst 3561 # number of demand (read+write) misses 1019system.cpu.l2cache.demand_misses::cpu.data 112323 # number of demand (read+write) misses 1020system.cpu.l2cache.demand_misses::total 115884 # number of demand (read+write) misses 1021system.cpu.l2cache.overall_misses::cpu.inst 3561 # number of overall misses 1022system.cpu.l2cache.overall_misses::cpu.data 112323 # number of overall misses 1023system.cpu.l2cache.overall_misses::total 115884 # number of overall misses 1024system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 237049229 # number of ReadReq miss cycles 1025system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7458222067 # number of ReadReq miss cycles 1026system.cpu.l2cache.ReadReq_miss_latency::total 7695271296 # number of ReadReq miss cycles 1027system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 224011514 # number of ReadExReq miss cycles 1028system.cpu.l2cache.ReadExReq_miss_latency::total 224011514 # number of ReadExReq miss cycles 1029system.cpu.l2cache.demand_miss_latency::cpu.inst 237049229 # number of demand (read+write) miss cycles 1030system.cpu.l2cache.demand_miss_latency::cpu.data 7682233581 # number of demand (read+write) miss cycles 1031system.cpu.l2cache.demand_miss_latency::total 7919282810 # number of demand (read+write) miss cycles 1032system.cpu.l2cache.overall_miss_latency::cpu.inst 237049229 # number of overall miss cycles 1033system.cpu.l2cache.overall_miss_latency::cpu.data 7682233581 # number of overall miss cycles 1034system.cpu.l2cache.overall_miss_latency::total 7919282810 # number of overall miss cycles 1035system.cpu.l2cache.ReadReq_accesses::cpu.inst 5169721 # number of ReadReq accesses(hits+misses) 1036system.cpu.l2cache.ReadReq_accesses::cpu.data 2035831 # number of ReadReq accesses(hits+misses) 1037system.cpu.l2cache.ReadReq_accesses::total 7205552 # number of ReadReq accesses(hits+misses) 1038system.cpu.l2cache.Writeback_accesses::writebacks 735128 # number of Writeback accesses(hits+misses) 1039system.cpu.l2cache.Writeback_accesses::total 735128 # number of Writeback accesses(hits+misses) 1040system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 1041system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 1042system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) 1043system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) 1044system.cpu.l2cache.demand_accesses::cpu.inst 5169721 # number of demand (read+write) accesses 1045system.cpu.l2cache.demand_accesses::cpu.data 2756678 # number of demand (read+write) accesses 1046system.cpu.l2cache.demand_accesses::total 7926399 # number of demand (read+write) accesses 1047system.cpu.l2cache.overall_accesses::cpu.inst 5169721 # number of overall (read+write) accesses 1048system.cpu.l2cache.overall_accesses::cpu.data 2756678 # number of overall (read+write) accesses 1049system.cpu.l2cache.overall_accesses::total 7926399 # number of overall (read+write) accesses 1050system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses 1051system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053773 # miss rate for ReadReq accesses 1052system.cpu.l2cache.ReadReq_miss_rate::total 0.015687 # miss rate for ReadReq accesses 1053system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823529 # miss rate for UpgradeReq accesses 1054system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823529 # miss rate for UpgradeReq accesses 1055system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003955 # miss rate for ReadExReq accesses 1056system.cpu.l2cache.ReadExReq_miss_rate::total 0.003955 # miss rate for ReadExReq accesses 1057system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses 1058system.cpu.l2cache.demand_miss_rate::cpu.data 0.040746 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::total 0.014620 # miss rate for demand accesses 1060system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses 1061system.cpu.l2cache.overall_miss_rate::cpu.data 0.040746 # miss rate for overall accesses 1062system.cpu.l2cache.overall_miss_rate::total 0.014620 # miss rate for overall accesses 1063system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66568.163156 # average ReadReq miss latency 1064system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68129.038174 # average ReadReq miss latency 1065system.cpu.l2cache.ReadReq_avg_miss_latency::total 68079.864252 # average ReadReq miss latency 1066system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78572.961768 # average ReadExReq miss latency 1067system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78572.961768 # average ReadExReq miss latency 1068system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency 1069system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency 1070system.cpu.l2cache.demand_avg_miss_latency::total 68338.017414 # average overall miss latency 1071system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency 1072system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency 1073system.cpu.l2cache.overall_avg_miss_latency::total 68338.017414 # average overall miss latency 1074system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1075system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1076system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1077system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1078system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1079system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1080system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1081system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1082system.cpu.l2cache.writebacks::writebacks 66324 # number of writebacks 1083system.cpu.l2cache.writebacks::total 66324 # number of writebacks 1084system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 1085system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1342 # number of ReadReq MSHR hits 1086system.cpu.l2cache.ReadReq_mshr_hits::total 1353 # number of ReadReq MSHR hits 1087system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1474 # number of ReadExReq MSHR hits 1088system.cpu.l2cache.ReadExReq_mshr_hits::total 1474 # number of ReadExReq MSHR hits 1089system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 1090system.cpu.l2cache.demand_mshr_hits::cpu.data 2816 # number of demand (read+write) MSHR hits 1091system.cpu.l2cache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits 1092system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 1093system.cpu.l2cache.overall_mshr_hits::cpu.data 2816 # number of overall MSHR hits 1094system.cpu.l2cache.overall_mshr_hits::total 2827 # number of overall MSHR hits 1095system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3550 # number of ReadReq MSHR misses 1096system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108130 # number of ReadReq MSHR misses 1097system.cpu.l2cache.ReadReq_mshr_misses::total 111680 # number of ReadReq MSHR misses 1098system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202272 # number of HardPFReq MSHR misses 1099system.cpu.l2cache.HardPFReq_mshr_misses::total 202272 # number of HardPFReq MSHR misses 1100system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses 1101system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses 1102system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # number of ReadExReq MSHR misses 1103system.cpu.l2cache.ReadExReq_mshr_misses::total 1377 # number of ReadExReq MSHR misses 1104system.cpu.l2cache.demand_mshr_misses::cpu.inst 3550 # number of demand (read+write) MSHR misses 1105system.cpu.l2cache.demand_mshr_misses::cpu.data 109507 # number of demand (read+write) MSHR misses 1106system.cpu.l2cache.demand_mshr_misses::total 113057 # number of demand (read+write) MSHR misses 1107system.cpu.l2cache.overall_mshr_misses::cpu.inst 3550 # number of overall MSHR misses 1108system.cpu.l2cache.overall_mshr_misses::cpu.data 109507 # number of overall MSHR misses 1109system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202272 # number of overall MSHR misses 1110system.cpu.l2cache.overall_mshr_misses::total 315329 # number of overall MSHR misses 1111system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205967021 # number of ReadReq MSHR miss cycles 1112system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6469574626 # number of ReadReq MSHR miss cycles 1113system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6675541647 # number of ReadReq MSHR miss cycles 1114system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of HardPFReq MSHR miss cycles 1115system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18462254833 # number of HardPFReq MSHR miss cycles 1116system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 84014 # number of UpgradeReq MSHR miss cycles 1117system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 84014 # number of UpgradeReq MSHR miss cycles 1118system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126131000 # number of ReadExReq MSHR miss cycles 1119system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126131000 # number of ReadExReq MSHR miss cycles 1120system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205967021 # number of demand (read+write) MSHR miss cycles 1121system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6595705626 # number of demand (read+write) MSHR miss cycles 1122system.cpu.l2cache.demand_mshr_miss_latency::total 6801672647 # number of demand (read+write) MSHR miss cycles 1123system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205967021 # number of overall MSHR miss cycles 1124system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6595705626 # number of overall MSHR miss cycles 1125system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of overall MSHR miss cycles 1126system.cpu.l2cache.overall_mshr_miss_latency::total 25263927480 # number of overall MSHR miss cycles 1127system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for ReadReq accesses 1128system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053113 # mshr miss rate for ReadReq accesses 1129system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015499 # mshr miss rate for ReadReq accesses 1130system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1131system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1132system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823529 # mshr miss rate for UpgradeReq accesses 1133system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823529 # mshr miss rate for UpgradeReq accesses 1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses 1135system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses 1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for demand accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for demand accesses 1138system.cpu.l2cache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses 1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for overall accesses 1140system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for overall accesses 1141system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1142system.cpu.l2cache.overall_mshr_miss_rate::total 0.039782 # mshr miss rate for overall accesses 1143system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58018.879155 # average ReadReq mshr miss latency 1144system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59831.449422 # average ReadReq mshr miss latency 1145system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59773.832799 # average ReadReq mshr miss latency 1146system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average HardPFReq mshr miss latency 1147system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91274.397015 # average HardPFReq mshr miss latency 1148system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 1149system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 1150system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91598.402324 # average ReadExReq mshr miss latency 1151system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91598.402324 # average ReadExReq mshr miss latency 1152system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency 1153system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency 1154system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60161.446412 # average overall mshr miss latency 1155system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency 1156system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency 1157system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average overall mshr miss latency 1158system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80119.264261 # average overall mshr miss latency 1159system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1160system.cpu.toL2Bus.trans_dist::ReadReq 7205568 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::ReadResp 7205568 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::Writeback 735128 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::HardPFReq 316987 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution 1168system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339458 # Packet count per connected master and slave (bytes) 1169system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248518 # Packet count per connected master and slave (bytes) 1170system.cpu.toL2Bus.pkt_count::total 16587976 # Packet count per connected master and slave (bytes) 1171system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330862144 # Cumulative packet size per connected master and slave (bytes) 1172system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475584 # Cumulative packet size per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_size::total 554337728 # Cumulative packet size per connected master and slave (bytes) 1174system.cpu.toL2Bus.snoops 317003 # Total snoops (count) 1175system.cpu.toL2Bus.snoop_fanout::samples 8978547 # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::mean 5.035305 # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::stdev 0.184549 # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::5 8661560 96.47% 96.47% # Request fanout histogram 1185system.cpu.toL2Bus.snoop_fanout::6 316987 3.53% 100.00% # Request fanout histogram 1186system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1189system.cpu.toL2Bus.snoop_fanout::total 8978547 # Request fanout histogram 1190system.cpu.toL2Bus.reqLayer0.occupancy 5065908000 # Layer occupancy (ticks) 1191system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1192system.cpu.toL2Bus.respLayer0.occupancy 7755114990 # Layer occupancy (ticks) 1193system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 1194system.cpu.toL2Bus.respLayer1.occupancy 4143326908 # Layer occupancy (ticks) 1195system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 1196system.membus.trans_dist::ReadReq 313877 # Transaction distribution 1197system.membus.trans_dist::ReadResp 313877 # Transaction distribution 1198system.membus.trans_dist::Writeback 66324 # Transaction distribution 1199system.membus.trans_dist::UpgradeReq 14 # Transaction distribution 1200system.membus.trans_dist::UpgradeResp 14 # Transaction distribution 1201system.membus.trans_dist::ReadExReq 1377 # Transaction distribution 1202system.membus.trans_dist::ReadExResp 1377 # Transaction distribution 1203system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 696860 # Packet count per connected master and slave (bytes) 1204system.membus.pkt_count::total 696860 # Packet count per connected master and slave (bytes) 1205system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24420992 # Cumulative packet size per connected master and slave (bytes) 1206system.membus.pkt_size::total 24420992 # Cumulative packet size per connected master and slave (bytes) 1207system.membus.snoops 0 # Total snoops (count) 1208system.membus.snoop_fanout::samples 381592 # Request fanout histogram 1209system.membus.snoop_fanout::mean 0 # Request fanout histogram 1210system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1211system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1212system.membus.snoop_fanout::0 381592 100.00% 100.00% # Request fanout histogram 1213system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1214system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1215system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1216system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1217system.membus.snoop_fanout::total 381592 # Request fanout histogram 1218system.membus.reqLayer0.occupancy 993954700 # Layer occupancy (ticks) 1219system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 1220system.membus.respLayer1.occupancy 2896150900 # Layer occupancy (ticks) 1221system.membus.respLayer1.utilization 0.7 # Layer utilization (%) |
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| 1194 1195---------- End Simulation Statistics ---------- | 1222 1223---------- End Simulation Statistics ---------- |