| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.735495 # Number of seconds simulated 4sim_ticks 735495062500 # Number of ticks simulated 5final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 76677 # Simulator instruction rate (inst/s) 8host_op_rate 104424 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40737062 # Simulator tick rate (ticks/s) 10host_mem_usage 237976 # Number of bytes of host memory used 11host_seconds 18054.69 # Real time elapsed on the host |
| 12sim_insts 1384379503 # Number of instructions simulated 13sim_ops 1885334256 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 213952 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 94625728 # Number of bytes read from this memory 16system.physmem.bytes_read::total 94839680 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 213952 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 213952 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory 20system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1478527 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 1481870 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 290895 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 128655830 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 128946726 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 290895 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 290895 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 5751685 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 5751685 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 5751685 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 290895 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 128655830 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 134698411 # Total bandwidth to/from this memory (bytes/s) |
| 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 332 unchanged lines hidden (view full) --- 377system.cpu.icache.overall_miss_latency::total 322136500 # number of overall miss cycles 378system.cpu.icache.ReadReq_accesses::cpu.inst 414743940 # number of ReadReq accesses(hits+misses) 379system.cpu.icache.ReadReq_accesses::total 414743940 # number of ReadReq accesses(hits+misses) 380system.cpu.icache.demand_accesses::cpu.inst 414743940 # number of demand (read+write) accesses 381system.cpu.icache.demand_accesses::total 414743940 # number of demand (read+write) accesses 382system.cpu.icache.overall_accesses::cpu.inst 414743940 # number of overall (read+write) accesses 383system.cpu.icache.overall_accesses::total 414743940 # number of overall (read+write) accesses 384system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses |
| 385system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses |
| 386system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses |
| 387system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses |
| 388system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses |
| 389system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses |
| 390system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency |
| 391system.cpu.icache.ReadReq_avg_miss_latency::total 8807.319007 # average ReadReq miss latency |
| 392system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency |
| 393system.cpu.icache.demand_avg_miss_latency::total 8807.319007 # average overall miss latency |
| 394system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency |
| 395system.cpu.icache.overall_avg_miss_latency::total 8807.319007 # average overall miss latency |
| 396system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 400system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 401system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.cpu.icache.fast_writes 0 # number of fast writes performed 403system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 415system.cpu.icache.overall_mshr_misses::total 35723 # number of overall MSHR misses 416system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192601000 # number of ReadReq MSHR miss cycles 417system.cpu.icache.ReadReq_mshr_miss_latency::total 192601000 # number of ReadReq MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192601000 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::total 192601000 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192601000 # number of overall MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::total 192601000 # number of overall MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses |
| 423system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses |
| 424system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses |
| 425system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses |
| 426system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses |
| 427system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses |
| 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency |
| 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5391.512471 # average ReadReq mshr miss latency |
| 430system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency |
| 431system.cpu.icache.demand_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency |
| 432system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency |
| 433system.cpu.icache.overall_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency |
| 434system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 435system.cpu.dcache.replacements 1532415 # number of replacements 436system.cpu.dcache.tagsinuse 4094.914319 # Cycle average of tags in use 437system.cpu.dcache.total_refs 1032974400 # Total number of references to valid blocks. 438system.cpu.dcache.sampled_refs 1536511 # Sample count of references to valid blocks. 439system.cpu.dcache.avg_refs 672.285717 # Average number of references to valid blocks. 440system.cpu.dcache.warmup_cycle 290267000 # Cycle when the warmup percentage was hit. 441system.cpu.dcache.occ_blocks::cpu.data 4094.914319 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 481system.cpu.dcache.LoadLockedReq_accesses::total 13153 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.StoreCondReq_accesses::cpu.data 11766 # number of StoreCondReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::total 11766 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.demand_accesses::cpu.data 1036122172 # number of demand (read+write) accesses 485system.cpu.dcache.demand_accesses::total 1036122172 # number of demand (read+write) accesses 486system.cpu.dcache.overall_accesses::cpu.data 1036122172 # number of overall (read+write) accesses 487system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses 488system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003120 # miss rate for ReadReq accesses |
| 489system.cpu.dcache.ReadReq_miss_rate::total 0.003120 # miss rate for ReadReq accesses |
| 490system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses |
| 491system.cpu.dcache.WriteReq_miss_rate::total 0.002965 # miss rate for WriteReq accesses |
| 492system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses |
| 493system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000228 # miss rate for LoadLockedReq accesses |
| 494system.cpu.dcache.demand_miss_rate::cpu.data 0.003078 # miss rate for demand accesses |
| 495system.cpu.dcache.demand_miss_rate::total 0.003078 # miss rate for demand accesses |
| 496system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses |
| 497system.cpu.dcache.overall_miss_rate::total 0.003078 # miss rate for overall accesses |
| 498system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency |
| 499system.cpu.dcache.ReadReq_avg_miss_latency::total 33834.598445 # average ReadReq miss latency |
| 500system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency |
| 501system.cpu.dcache.WriteReq_avg_miss_latency::total 34793.690065 # average WriteReq miss latency |
| 502system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency |
| 503system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38166.666667 # average LoadLockedReq miss latency |
| 504system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency |
| 505system.cpu.dcache.demand_avg_miss_latency::total 34081.493121 # average overall miss latency |
| 506system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency |
| 507system.cpu.dcache.overall_avg_miss_latency::total 34081.493121 # average overall miss latency |
| 508system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 509system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked 510system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 512system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked 514system.cpu.dcache.fast_writes 0 # number of fast writes performed 515system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 537system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029877000 # number of ReadReq MSHR miss cycles 538system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502958500 # number of WriteReq MSHR miss cycles 539system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502958500 # number of WriteReq MSHR miss cycles 540system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52532835500 # number of demand (read+write) MSHR miss cycles 541system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 # number of demand (read+write) MSHR miss cycles 542system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52532835500 # number of overall MSHR miss cycles 543system.cpu.dcache.overall_mshr_miss_latency::total 52532835500 # number of overall MSHR miss cycles 544system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses |
| 545system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001928 # mshr miss rate for ReadReq accesses |
| 546system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses |
| 547system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses |
| 548system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses |
| 549system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses |
| 550system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses |
| 551system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses |
| 552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34178.105737 # average ReadReq mshr miss latency |
| 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34178.105737 # average ReadReq mshr miss latency |
| 554system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230.114990 # average WriteReq mshr miss latency |
| 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32230.114990 # average WriteReq mshr miss latency |
| 556system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency |
| 557system.cpu.dcache.demand_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency |
| 558system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency |
| 559system.cpu.dcache.overall_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency |
| 560system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 561system.cpu.l2cache.replacements 1480284 # number of replacements 562system.cpu.l2cache.tagsinuse 31973.508020 # Cycle average of tags in use 563system.cpu.l2cache.total_refs 87070 # Total number of references to valid blocks. 564system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks. 565system.cpu.l2cache.avg_refs 0.057548 # Average number of references to valid blocks. 566system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 567system.cpu.l2cache.occ_blocks::writebacks 2965.813236 # Average occupied blocks per requestor --- 54 unchanged lines hidden (view full) --- 622system.cpu.l2cache.demand_accesses::cpu.inst 30776 # number of demand (read+write) accesses 623system.cpu.l2cache.demand_accesses::cpu.data 1536511 # number of demand (read+write) accesses 624system.cpu.l2cache.demand_accesses::total 1567287 # number of demand (read+write) accesses 625system.cpu.l2cache.overall_accesses::cpu.inst 30776 # number of overall (read+write) accesses 626system.cpu.l2cache.overall_accesses::cpu.data 1536511 # number of overall (read+write) accesses 627system.cpu.l2cache.overall_accesses::total 1567287 # number of overall (read+write) accesses 628system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108786 # miss rate for ReadReq accesses 629system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964935 # miss rate for ReadReq accesses |
| 630system.cpu.l2cache.ReadReq_miss_rate::total 0.947305 # miss rate for ReadReq accesses |
| 631system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999394 # miss rate for UpgradeReq accesses |
| 632system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999394 # miss rate for UpgradeReq accesses |
| 633system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908791 # miss rate for ReadExReq accesses |
| 634system.cpu.l2cache.ReadExReq_miss_rate::total 0.908791 # miss rate for ReadExReq accesses |
| 635system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108786 # miss rate for demand accesses 636system.cpu.l2cache.demand_miss_rate::cpu.data 0.962278 # miss rate for demand accesses |
| 637system.cpu.l2cache.demand_miss_rate::total 0.945519 # miss rate for demand accesses |
| 638system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108786 # miss rate for overall accesses 639system.cpu.l2cache.overall_miss_rate::cpu.data 0.962278 # miss rate for overall accesses |
| 640system.cpu.l2cache.overall_miss_rate::total 0.945519 # miss rate for overall accesses |
| 641system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.972521 # average ReadReq miss latency 642system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34306.089470 # average ReadReq miss latency |
| 643system.cpu.l2cache.ReadReq_avg_miss_latency::total 34306.025346 # average ReadReq miss latency |
| 644system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.322034 # average ReadExReq miss latency |
| 645system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.322034 # average ReadExReq miss latency |
| 646system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency 647system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency |
| 648system.cpu.l2cache.demand_avg_miss_latency::total 34296.139278 # average overall miss latency |
| 649system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency 650system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency |
| 651system.cpu.l2cache.overall_avg_miss_latency::total 34296.139278 # average overall miss latency |
| 652system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 655system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 656system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 657system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.cpu.l2cache.fast_writes 0 # number of fast writes performed 659system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 31 unchanged lines hidden (view full) --- 691system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103877000 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931558500 # number of demand (read+write) MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_latency::total 46035435500 # number of demand (read+write) MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103877000 # number of overall MSHR miss cycles 695system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931558500 # number of overall MSHR miss cycles 696system.cpu.l2cache.overall_mshr_miss_latency::total 46035435500 # number of overall MSHR miss cycles 697system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964919 # mshr miss rate for ReadReq accesses |
| 699system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947286 # mshr miss rate for ReadReq accesses |
| 700system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999394 # mshr miss rate for UpgradeReq accesses |
| 701system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999394 # mshr miss rate for UpgradeReq accesses |
| 702system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908791 # mshr miss rate for ReadExReq accesses |
| 703system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908791 # mshr miss rate for ReadExReq accesses |
| 704system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for demand accesses 705system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses |
| 706system.cpu.l2cache.demand_mshr_miss_rate::total 0.945500 # mshr miss rate for demand accesses |
| 707system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses 708system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses |
| 709system.cpu.l2cache.overall_mshr_miss_rate::total 0.945500 # mshr miss rate for overall accesses |
| 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency 711system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency |
| 712system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31068.809993 # average ReadReq mshr miss latency |
| 713system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency |
| 714system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency |
| 715system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency |
| 716system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.680993 # average ReadExReq mshr miss latency |
| 717system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency 718system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency |
| 719system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency |
| 720system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency 721system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency |
| 722system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency |
| 723system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 724 725---------- End Simulation Statistics ---------- |