3,5c3,5
< sim_seconds 0.627778 # Number of seconds simulated
< sim_ticks 627777658000 # Number of ticks simulated
< final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.627439 # Number of seconds simulated
> sim_ticks 627439125000 # Number of ticks simulated
> final_tick 627439125000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 109787 # Simulator instruction rate (inst/s)
< host_op_rate 149515 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 49785649 # Simulator tick rate (ticks/s)
< host_mem_usage 262368 # Number of bytes of host memory used
< host_seconds 12609.61 # Real time elapsed on the host
---
> host_inst_rate 96597 # Simulator instruction rate (inst/s)
> host_op_rate 131552 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 43780556 # Simulator tick rate (ticks/s)
> host_mem_usage 260984 # Number of bytes of host memory used
> host_seconds 14331.46 # Real time elapsed on the host
14,18c14,18
< system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory
< system.physmem.bytes_read::total 30397824 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 30242368 # Number of bytes read from this memory
> system.physmem.bytes_read::total 30397376 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory
21,23c21,23
< system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 474966 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 472537 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 474959 # Number of read requests responded to by this memory
26,37c26,37
< system.physmem.bw_read::cpu.inst 246813 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 48174508 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 48421322 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 246813 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 246813 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 6738488 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 6738488 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 6738488 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 246813 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 48174508 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 474966 # Total number of read requests seen
---
> system.physmem.bw_read::cpu.inst 247049 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 48199685 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 48446733 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 247049 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 247049 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 6742123 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 6742123 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 6742123 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 247049 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 48199685 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 55188857 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 474959 # Total number of read requests seen
39,40c39,40
< system.physmem.cpureqs 545372 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 30397824 # Total number of bytes read from memory
---
> system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 30397376 # Total number of bytes read from memory
42c42
< system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize()
---
> system.physmem.bytesConsumedRd 30397376 # bytesRead derated as per pkt->getSize()
44,48c44,48
< system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 4308 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis
---
> system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q
> system.physmem.neitherReadNorWrite 4291 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 29712 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 29706 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 29691 # Track reads on a per bank basis
50c50
< system.physmem.perBankRdReqs::4 29687 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::4 29689 # Track reads on a per bank basis
52c52
< system.physmem.perBankRdReqs::6 29750 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::6 29747 # Track reads on a per bank basis
54,57c54,57
< system.physmem.perBankRdReqs::8 29637 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 29680 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 29627 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 29600 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::8 29640 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 29682 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 29629 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 29602 # Track reads on a per bank basis
59,61c59,61
< system.physmem.perBankRdReqs::13 29633 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 29689 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 29652 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::13 29628 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 29687 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 29649 # Track reads on a per bank basis
80c80
< system.physmem.totGap 627777588500 # Total gap between requests
---
> system.physmem.totGap 627439056500 # Total gap between requests
87c87
< system.physmem.readPktSize::6 474966 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 474959 # Categorize read packet sizes
95,100c95,100
< system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 405906 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 66678 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 2122 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
159,164c159,164
< system.physmem.totQLat 3182824500 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 21162788250 # Sum of mem lat for all requests
< system.physmem.totBusLat 2374030000 # Total cycles spent in databus access
< system.physmem.totBankLat 15605933750 # Total cycles spent in bank access
< system.physmem.avgQLat 6703.42 # Average queueing delay per request
< system.physmem.avgBankLat 32868.02 # Average bank access latency per request
---
> system.physmem.totQLat 3462811500 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 21441489000 # Sum of mem lat for all requests
> system.physmem.totBusLat 2374050000 # Total cycles spent in databus access
> system.physmem.totBankLat 15604627500 # Total cycles spent in bank access
> system.physmem.avgQLat 7293.05 # Average queueing delay per request
> system.physmem.avgBankLat 32864.99 # Average bank access latency per request
166,167c166,167
< system.physmem.avgMemAccLat 44571.44 # Average memory access latency
< system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s
---
> system.physmem.avgMemAccLat 45158.04 # Average memory access latency
> system.physmem.avgRdBW 48.45 # Average achieved read bandwidth in MB/s
169c169
< system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s
---
> system.physmem.avgConsumedRdBW 48.45 # Average consumed read bandwidth in MB/s
175,176c175,176
< system.physmem.readRowHits 143321 # Number of row buffer hits during reads
< system.physmem.writeRowHits 45521 # Number of row buffer hits during writes
---
> system.physmem.readRowHits 143341 # Number of row buffer hits during reads
> system.physmem.writeRowHits 45511 # Number of row buffer hits during writes
178,184c178,184
< system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes
< system.physmem.avgGap 1160264.94 # Average gap between requests
< system.cpu.branchPred.lookups 438315942 # Number of BP lookups
< system.cpu.branchPred.condPredicted 349727890 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 30635219 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 247833723 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 226959266 # Number of BTB hits
---
> system.physmem.writeRowHitRate 68.85 # Row buffer hit rate for writes
> system.physmem.avgGap 1159654.26 # Average gap between requests
> system.cpu.branchPred.lookups 440649573 # Number of BP lookups
> system.cpu.branchPred.condPredicted 353682166 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 30631043 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 252533039 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 230279415 # Number of BTB hits
186,188c186,188
< system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 2806740 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 91.187837 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 51764959 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 2806562 # Number of incorrect RAS predictions.
232c232
< system.cpu.numCycles 1255555317 # number of cpu cycles simulated
---
> system.cpu.numCycles 1254878251 # number of cpu cycles simulated
235,249c235,249
< system.cpu.fetch.icacheStallCycles 353470076 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 2285596018 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 438315942 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 279264180 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 600835401 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 132517239 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 333121635 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 10719821 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 1213961612 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.592462 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 354654463 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 2286055838 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 440649573 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 282044374 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 601927539 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 156613440 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 130193180 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 518 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 10572 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 335557697 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 11970074 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 1212716808 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.588686 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.181757 # Number of instructions fetched each cycle (Total)
251,259c251,259
< system.cpu.fetch.rateDist::0 613170569 50.51% 50.51% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 42771992 3.52% 54.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 71974346 5.93% 72.42% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 42167023 3.47% 75.89% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 30997748 2.55% 78.45% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 230060886 18.95% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 610833811 50.37% 50.37% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 43093126 3.55% 53.92% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 96161904 7.93% 61.85% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 57061464 4.71% 66.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 71748155 5.92% 72.47% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 43390011 3.58% 76.05% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 30893705 2.55% 78.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 32839857 2.71% 81.31% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 226694775 18.69% 100.00% # Number of instructions fetched each cycle (Total)
263,284c263,284
< system.cpu.fetch.rateDist::total 1213961612 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 402973570 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 105164432 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 561876513 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 16833922 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 127113175 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 44705454 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 3047243320 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 127113175 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 438520828 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 34437480 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 439400 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 541081761 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 72368968 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 2975054899 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 4810930 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 57090211 # Number of times rename has blocked due to LSQ full
---
> system.cpu.fetch.rateDist::total 1212716808 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.351149 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.821735 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 405646781 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 102637713 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 561793047 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 16722466 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 125916801 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 44665335 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 13931 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 3029413956 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 28108 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 125916801 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 441580002 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 34476908 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 437379 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 540507560 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 69798158 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 2946364126 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 4812832 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 54672934 # Number of times rename has blocked due to LSQ full
286,289c286,289
< system.cpu.rename.RenamedOperands 2946030115 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 14164064845 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 13593631976 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 570432869 # Number of floating rename lookups
---
> system.cpu.rename.RenamedOperands 2931066413 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 14023290204 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 13452684524 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 570605680 # Number of floating rename lookups
291,308c291,308
< system.cpu.rename.UndoneMaps 952890025 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 25236 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 195466614 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 973207403 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 490834559 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 40613980 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 2806590515 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 2437414876 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 13391013 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 908731819 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 2361150824 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 1213961612 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.007819 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.875089 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 937926323 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 22415 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 19926 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 179121288 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 970649993 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 487168712 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 36377618 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 40069949 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 2792240287 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 29328 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 2432835777 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 13263841 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 894381457 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 2312630775 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 7944 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 1212716808 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.006104 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle
310,318c310,318
< system.cpu.iq.issued_per_cycle::0 377942739 31.13% 31.13% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 183591536 15.12% 46.26% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 202672014 16.70% 62.95% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 169721523 13.98% 76.93% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 132842970 10.94% 87.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 93759245 7.72% 95.60% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 37926008 3.12% 98.72% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 12454026 1.03% 99.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 376728714 31.06% 31.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 183811265 15.16% 46.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 203907049 16.81% 63.04% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 169580498 13.98% 77.02% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 132860198 10.96% 87.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 92416507 7.62% 95.60% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 37964146 3.13% 98.73% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 12426731 1.02% 99.75% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 3021700 0.25% 100.00% # Number of insts issued each cycle
322c322
< system.cpu.iq.issued_per_cycle::total 1213961612 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1212716808 # Number of insts issued each cycle
324,325c324,325
< system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 716116 0.82% 0.82% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 24381 0.03% 0.85% # attempts to use FU when none available
353,354c353,354
< system.cpu.iq.fu_full::MemRead 55152382 62.89% 63.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 55122687 62.92% 63.76% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 31746374 36.24% 100.00% # attempts to use FU when none available
358,388c358,388
< system.cpu.iq.FU_type_0::IntAlu 1108357154 45.47% 45.47% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 5502588 0.23% 46.50% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 23405386 0.96% 47.46% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 838249094 34.39% 81.85% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 442425361 18.15% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1103971506 45.38% 45.38% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 11223452 0.46% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 5502427 0.23% 46.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 23409752 0.96% 47.37% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 838269607 34.46% 81.82% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 442207267 18.18% 100.00% # Type of FU issued
391,403c391,403
< system.cpu.iq.FU_type_0::total 2437414876 # Type of FU issued
< system.cpu.iq.rate 1.941304 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 87694306 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 6067362312 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 3632711697 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 2254358254 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 122514371 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 82707334 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 56439819 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 2461788341 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 63320841 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 84306513 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 2432835777 # Type of FU issued
> system.cpu.iq.rate 1.938703 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 87609558 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.036011 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 6056740662 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 3603968769 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 2248867979 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 122521099 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 82749412 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 56444030 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 2457121441 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 63323894 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 84335781 # Number of loads that had data forwarded from stores
405,408c405,408
< system.cpu.iew.lsq.thread0.squashedLoads 341820222 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 8583 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 1429956 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 213839262 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 339262812 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 8485 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 1431215 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 210173415 # Number of stores squashed
412c412
< system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked
414,422c414,422
< system.cpu.iew.iewSquashCycles 127113175 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 12638633 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1558332 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 2806632387 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 973207403 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 490834559 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 1554341 # Number of times the IQ has become full, causing a stall
---
> system.cpu.iew.iewSquashCycles 125916801 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 12646480 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1559895 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 2792282007 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 1384453 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 970649993 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 487168712 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 19342 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 1555909 # Number of times the IQ has become full, causing a stall
424,430c424,430
< system.cpu.iew.memOrderViolationEvents 1429956 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 32461974 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 33956380 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 2363518752 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 792548156 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.memOrderViolationEvents 1431215 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 32433063 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 1530059 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 33963122 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 2358070725 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 792574818 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 74765052 # Number of squashed instructions skipped in execute
432,440c432,440
< system.cpu.iew.exec_nop 12468 # number of nop insts executed
< system.cpu.iew.exec_refs 1216269086 # number of memory reference insts executed
< system.cpu.iew.exec_branches 322574286 # Number of branches executed
< system.cpu.iew.exec_stores 423720930 # Number of stores executed
< system.cpu.iew.exec_rate 1.882449 # Inst execution rate
< system.cpu.iew.wb_sent 2336489228 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 2310798073 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1347631579 # num instructions producing a value
< system.cpu.iew.wb_consumers 2523967689 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 12392 # number of nop insts executed
> system.cpu.iew.exec_refs 1216182478 # number of memory reference insts executed
> system.cpu.iew.exec_branches 319878188 # Number of branches executed
> system.cpu.iew.exec_stores 423607660 # Number of stores executed
> system.cpu.iew.exec_rate 1.879123 # Inst execution rate
> system.cpu.iew.wb_sent 2331089515 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 2305312009 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1347373640 # num instructions producing a value
> system.cpu.iew.wb_consumers 2522763992 # num instructions consuming a value
442,443c442,443
< system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.837080 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.534086 # average fanout of values written-back
445c445
< system.cpu.commit.commitSquashedInsts 921296175 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 906945779 # The number of squashed insts skipped by commit
447,450c447,450
< system.cpu.commit.branchMispredicts 30621418 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 1086848437 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.734682 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.398805 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 30617374 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 1086800007 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.734759 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.398832 # Number of insts commited each cycle
452,460c452,460
< system.cpu.commit.committed_per_cycle::0 446548721 41.09% 41.09% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 288590719 26.55% 67.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 95114953 8.75% 76.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 46461870 4.27% 87.13% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 22187798 2.04% 89.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 15847039 1.46% 90.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 10983692 1.01% 91.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 90884050 8.36% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 446471329 41.08% 41.08% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 288644992 26.56% 67.64% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 95109223 8.75% 76.39% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 70211025 6.46% 82.85% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 46444999 4.27% 87.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 22203598 2.04% 89.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 15846659 1.46% 90.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 10983551 1.01% 91.64% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 90884631 8.36% 100.00% # Number of insts commited each cycle
464c464
< system.cpu.commit.committed_per_cycle::total 1086848437 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 1086800007 # Number of insts commited each cycle
471c471
< system.cpu.commit.branches 299634395 # Number of branches committed
---
> system.cpu.commit.branches 298259106 # Number of branches committed
475c475
< system.cpu.commit.bw_lim_events 90884050 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 90884631 # number cycles where commit BW limit reached
477,480c477,480
< system.cpu.rob.rob_reads 3802578575 # The number of ROB reads
< system.cpu.rob.rob_writes 5740389473 # The number of ROB writes
< system.cpu.timesIdled 353174 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 41593705 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 3788179168 # The number of ROB reads
> system.cpu.rob.rob_writes 5710492063 # The number of ROB writes
> system.cpu.timesIdled 353297 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 42161443 # Total number of cycles that the CPU has spent unscheduled due to idling
484,492c484,492
< system.cpu.cpi 0.906950 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 11774707263 # number of integer regfile reads
< system.cpu.int_regfile_writes 2226782267 # number of integer regfile writes
< system.cpu.fp_regfile_reads 68797357 # number of floating regfile reads
< system.cpu.fp_regfile_writes 49551943 # number of floating regfile writes
< system.cpu.misc_regfile_reads 1364040345 # number of misc regfile reads
---
> system.cpu.cpi 0.906461 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.906461 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.103191 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.103191 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 11756795674 # number of integer regfile reads
> system.cpu.int_regfile_writes 2218922402 # number of integer regfile writes
> system.cpu.fp_regfile_reads 68796713 # number of floating regfile reads
> system.cpu.fp_regfile_writes 49556201 # number of floating regfile writes
> system.cpu.misc_regfile_reads 1363984791 # number of misc regfile reads
494,498c494,498
< system.cpu.icache.replacements 22740 # number of replacements
< system.cpu.icache.tagsinuse 1642.119596 # Cycle average of tags in use
< system.cpu.icache.total_refs 333085977 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 13639.884398 # Average number of references to valid blocks.
---
> system.cpu.icache.replacements 22806 # number of replacements
> system.cpu.icache.tagsinuse 1643.708828 # Cycle average of tags in use
> system.cpu.icache.total_refs 335522072 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 24489 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 13700.929887 # Average number of references to valid blocks.
500,539c500,539
< system.cpu.icache.occ_blocks::cpu.inst 1642.119596 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 333090004 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 333090004 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 333090004 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 333090004 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 333090004 # number of overall hits
< system.cpu.icache.overall_hits::total 333090004 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 31630 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 31630 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 31630 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 31630 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 31630 # number of overall misses
< system.cpu.icache.overall_misses::total 31630 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 481232999 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 481232999 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 481232999 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 481232999 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 481232999 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 481232999 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 333121634 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 333121634 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 333121634 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 333121634 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 333121634 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 333121634 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15214.448277 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 15214.448277 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 15214.448277 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 15214.448277 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked
---
> system.cpu.icache.occ_blocks::cpu.inst 1643.708828 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.802592 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.802592 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 335526084 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 335526084 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 335526084 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 335526084 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 335526084 # number of overall hits
> system.cpu.icache.overall_hits::total 335526084 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 31612 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 31612 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 31612 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 31612 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 31612 # number of overall misses
> system.cpu.icache.overall_misses::total 31612 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 479792499 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 479792499 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 479792499 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 479792499 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 479792499 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 479792499 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 335557696 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 335557696 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 335557696 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 335557696 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 335557696 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 335557696 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15177.543306 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 15177.543306 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 15177.543306 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 15177.543306 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 15177.543306 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 15177.543306 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 835 # number of cycles access was blocked
541c541
< system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked
543c543
< system.cpu.icache.avg_blocked_cycles::no_mshrs 32.692308 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 33.400000 # average number of cycles each access was blocked
547,564c547,564
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2899 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2899 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2899 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2899 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2899 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28731 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 28731 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 28731 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 28731 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 28731 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 28731 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386564499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 386564499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386564499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 386564499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386564499 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 386564499 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2827 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2827 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2827 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2827 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2827 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28785 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 28785 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 28785 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 28785 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 28785 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 28785 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386126499 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 386126499 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386126499 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 386126499 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386126499 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 386126499 # number of overall MSHR miss cycles
571,576c571,576
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13454.613449 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13454.613449 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13414.156644 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13414.156644 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13414.156644 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13414.156644 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13414.156644 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13414.156644 # average overall mshr miss latency
578,582c578,582
< system.cpu.l2cache.replacements 442184 # number of replacements
< system.cpu.l2cache.tagsinuse 32692.574562 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 1110053 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 474931 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 2.337293 # Average number of references to valid blocks.
---
> system.cpu.l2cache.replacements 442178 # number of replacements
> system.cpu.l2cache.tagsinuse 32692.553116 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 1110010 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 474925 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 2.337232 # Average number of references to valid blocks.
584,587c584,587
< system.cpu.l2cache.occ_blocks::writebacks 1286.532429 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 50.222145 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 31355.819987 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.039262 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::writebacks 1287.010485 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 50.235756 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 31355.306875 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.039276 # Average percentage of cache occupancy
589c589
< system.cpu.l2cache.occ_percent::cpu.data 0.956904 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_percent::cpu.data 0.956888 # Average percentage of cache occupancy
591,668c591,668
< system.cpu.l2cache.ReadReq_hits::cpu.inst 21996 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1058215 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1080211 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 96321 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 96321 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 6442 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 6442 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 21996 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1064657 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1086653 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 21996 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1064657 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1086653 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2425 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 408916 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 4308 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 4308 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 2425 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 472566 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 474991 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2425 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 472566 # number of overall misses
< system.cpu.l2cache.overall_misses::total 474991 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 133322500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783806000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 28917128500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174251000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3174251000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 133322500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 31958057000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 32091379500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 133322500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 31958057000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 32091379500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 24421 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1464706 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1489127 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 96321 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 96321 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4311 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 4311 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 24421 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1537223 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1561644 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 24421 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1537223 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1561644 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099300 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277524 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.274601 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999304 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999304 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911166 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.911166 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099300 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.307415 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.304161 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099300 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.307415 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.304161 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54978.350515 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.438607 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.549365 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.121075 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.121075 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 67562.079071 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 67562.079071 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 22064 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1058101 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1080165 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 96323 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 96323 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 22064 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1064542 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1086606 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 22064 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1064542 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1086606 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2426 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 406486 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 408912 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 4291 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 4291 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 66074 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 66074 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 2426 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 472560 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 474986 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2426 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 472560 # number of overall misses
> system.cpu.l2cache.overall_misses::total 474986 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132157500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29065267000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 29197424500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174202000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3174202000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 132157500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 32239469000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 32371626500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 132157500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 32239469000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32371626500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 24490 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1464587 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1489077 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 96323 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 96323 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4296 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 4296 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 72515 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 72515 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 24490 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1537102 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1561592 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 24490 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1537102 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1561592 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099061 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277543 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.274608 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.998836 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.998836 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911177 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.911177 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099061 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.307436 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.304168 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099061 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.307436 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.304168 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54475.474031 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71503.734446 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 71402.708896 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.106547 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.106547 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54475.474031 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68223.017183 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68152.801346 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54475.474031 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68223.017183 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68152.801346 # average overall miss latency
680,681c680,681
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
683,684c683,684
< system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
686,729c686,729
< system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2421 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406470 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 408891 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4308 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 4308 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2421 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 472545 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 474966 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2421 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 474966 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103134689 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729007693 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832142382 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43084308 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43084308 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357071286 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357071286 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103134689 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086078979 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26189213668 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103134689 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086078979 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26189213668 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277510 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274584 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999304 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999304 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.304145 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.304145 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.036762 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58378.251022 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58284.829898 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2422 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406463 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 408885 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4291 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 4291 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66074 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 66074 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2422 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 472537 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 474959 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2422 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 472537 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 474959 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101956685 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24008915183 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24110871868 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42914291 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42914291 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357034286 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357034286 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101956685 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26365949469 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26467906154 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101956685 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26365949469 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26467906154 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098898 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277527 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274590 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998836 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.998836 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911177 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911177 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098898 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307421 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.304151 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098898 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307421 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.304151 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42096.071429 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59067.898389 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58967.367030 # average ReadReq mshr miss latency
732,739c732,739
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.664185 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.664185 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.644096 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.644096 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42096.071429 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55796.582001 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55726.717788 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42096.071429 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55796.582001 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55726.717788 # average overall mshr miss latency
741,745c741,745
< system.cpu.dcache.replacements 1533127 # number of replacements
< system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use
< system.cpu.dcache.total_refs 969988245 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 631.000346 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 1533005 # number of replacements
> system.cpu.dcache.tagsinuse 4094.655355 # Cycle average of tags in use
> system.cpu.dcache.total_refs 969956043 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1537101 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 631.029479 # Average number of references to valid blocks.
747c747
< system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor
---
> system.cpu.dcache.occ_blocks::cpu.data 4094.655355 # Average occupied blocks per requestor
750,753c750,753
< system.cpu.dcache.ReadReq_hits::cpu.data 693861536 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 693861536 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 276093810 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 276093810 # number of WriteReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 693829407 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 693829407 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 276093791 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 276093791 # number of WriteReq hits
758,765c758,765
< system.cpu.dcache.demand_hits::cpu.data 969955346 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 969955346 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 969955346 # number of overall hits
< system.cpu.dcache.overall_hits::total 969955346 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1953541 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 841868 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 841868 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 969923198 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 969923198 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 969923198 # number of overall hits
> system.cpu.dcache.overall_hits::total 969923198 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1953276 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1953276 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 841887 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 841887 # number of WriteReq misses
768,783c768,783
< system.cpu.dcache.demand_misses::cpu.data 2795409 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2795409 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2795409 # number of overall misses
< system.cpu.dcache.overall_misses::total 2795409 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 66484216000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 66484216000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 39427025969 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 39427025969 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 105911241969 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 105911241969 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 105911241969 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 105911241969 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 695815077 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 695815077 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 2795163 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2795163 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2795163 # number of overall misses
> system.cpu.dcache.overall_misses::total 2795163 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 66762023500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 66762023500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 39426392469 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 39426392469 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 106188415969 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 106188415969 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 106188415969 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 106188415969 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 695782683 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 695782683 # number of ReadReq accesses(hits+misses)
790,795c790,795
< system.cpu.dcache.demand_accesses::cpu.data 972750755 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 972750755 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 972750755 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 972750755 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 972718361 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 972718361 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 972718361 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 972718361 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
804,813c804,813
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34032.669906 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34032.669906 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46832.788476 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 46832.788476 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 37887.565637 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 37887.565637 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34179.513545 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34179.513545 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46830.979061 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 46830.979061 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 37990.062107 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 37990.062107 # average overall miss latency
815c815
< system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 726 # number of cycles access was blocked
817c817
< system.cpu.dcache.blocked::no_targets 90 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
819c819
< system.cpu.dcache.avg_blocked_cycles::no_targets 8.300000 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 8.157303 # average number of cycles each access was blocked
822,827c822,827
< system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks
< system.cpu.dcache.writebacks::total 96321 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765041 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 765041 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 96323 # number of writebacks
> system.cpu.dcache.writebacks::total 96323 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488688 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 488688 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765077 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 765077 # number of WriteReq MSHR hits
830,849c830,849
< system.cpu.dcache.demand_mshr_hits::cpu.data 1253875 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1253875 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1253875 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1253875 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76827 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 76827 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1541534 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1541534 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1541534 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1541534 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831573000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831573000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409419500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409419500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240992500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 44240992500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240992500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 44240992500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 1253765 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1253765 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1253765 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1253765 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464588 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1464588 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76810 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 76810 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1541398 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1541398 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1541398 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1541398 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41111704000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 41111704000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3408970500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3408970500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44520674500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 44520674500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44520674500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 44520674500 # number of overall MSHR miss cycles
858,865c858,865
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.956279 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.956279 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44377.881474 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44377.881474 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28070.490814 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28070.490814 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44381.857831 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44381.857831 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency