7,11c7,11
< host_inst_rate 118271 # Simulator instruction rate (inst/s)
< host_op_rate 161069 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 53384157 # Simulator tick rate (ticks/s)
< host_mem_usage 298364 # Number of bytes of host memory used
< host_seconds 11705.11 # Real time elapsed on the host
---
> host_inst_rate 53257 # Simulator instruction rate (inst/s)
> host_op_rate 72528 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 24038469 # Simulator tick rate (ticks/s)
> host_mem_usage 255596 # Number of bytes of host memory used
> host_seconds 25994.48 # Real time elapsed on the host
80c80
< system.physmem.totGap 624867513500 # Total gap between requests
---
> system.physmem.totGap 624867514500 # Total gap between requests
174,175c174,175
< system.physmem.totQLat 3316258619 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 18090208619 # Sum of mem lat for all requests
---
> system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests
181c181
< system.physmem.avgMemAccLat 38098.45 # Average memory access latency
---
> system.physmem.avgMemAccLat 38098.44 # Average memory access latency
249c249
< system.cpu.fetch.icacheStallCycles 354123352 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss
255,256c255,256
< system.cpu.fetch.BlockedCycles 133000859 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
259,261c259,261
< system.cpu.fetch.CacheLines 333825475 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 10767149 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 1215073364 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total)
265c265
< system.cpu.fetch.rateDist::0 614410423 50.57% 50.57% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total)
277c277
< system.cpu.fetch.rateDist::total 1215073364 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total)
281c281
< system.cpu.decode.BlockedCycles 105461627 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked
293,295c293,295
< system.cpu.rename.RunCycles 540789818 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 71593101 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 2966286071 # Number of instructions processed by rename
---
> system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename
299,301c299,301
< system.cpu.rename.RenamedOperands 2940514356 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 14121260893 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 13550785312 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups
304c304
< system.cpu.rename.UndoneMaps 947360714 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing
319c319
< system.cpu.iq.issued_per_cycle::samples 1215073364 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle
323c323
< system.cpu.iq.issued_per_cycle::0 379121475 31.20% 31.20% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle
335c335
< system.cpu.iq.issued_per_cycle::total 1215073364 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle
408c408
< system.cpu.iq.int_inst_queue_reads 6066277406 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads
431c431
< system.cpu.iew.iewDispSquashedInsts 1409393 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch
493c493
< system.cpu.idleCycles 34661808 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling
522,539c522,539
< system.cpu.icache.ReadReq_misses::cpu.inst 30836 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 30836 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 30836 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 30836 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 30836 # number of overall misses
< system.cpu.icache.overall_misses::total 30836 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 469688998 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 469688998 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 469688998 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 469688998 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 469688998 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 469688998 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 333825473 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 333825473 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 333825473 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 333825473 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 333825473 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 333825473 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses
> system.cpu.icache.overall_misses::total 30837 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses
546,551c546,551
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15231.839344 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 15231.839344 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 15231.839344 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 15231.839344 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15233.615397 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 15233.615397 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 15233.615397 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 15233.615397 # average overall miss latency
560,565c560,565
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2272 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2272 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2272 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2272 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2272 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2272 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2273 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2273 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2273 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2273 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2273 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2273 # number of overall MSHR hits
572,577c572,577
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379117998 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 379117998 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379117998 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 379117998 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379117998 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 379117998 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379116998 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 379116998 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379116998 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 379116998 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379116998 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 379116998 # number of overall MSHR miss cycles
584,589c584,589
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.580801 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.580801 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.545792 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.545792 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
591,716d590
< system.cpu.dcache.replacements 1532987 # number of replacements
< system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
< system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
< system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
< system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
< system.cpu.dcache.writebacks::total 96322 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
758,759c632,633
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128014500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837930500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128013500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837931500 # number of ReadReq miss cycles
761,763c635,637
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242870000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3242870000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 128014500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242869000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3242869000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 128013500 # number of demand (read+write) miss cycles
765,766c639,640
< system.cpu.l2cache.demand_miss_latency::total 29208815000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 128014500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 29208814000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 128013500 # number of overall miss cycles
768c642
< system.cpu.l2cache.overall_miss_latency::total 29208815000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 29208814000 # number of overall miss cycles
797,798c671,672
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.906289 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.351956 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.495273 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.354416 # average ReadReq miss latency
800,802c674,676
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.365560 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.365560 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.350425 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.350425 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
804,805c678,679
< system.cpu.l2cache.demand_avg_miss_latency::total 61492.501021 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 61492.498916 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
807c681
< system.cpu.l2cache.overall_avg_miss_latency::total 61492.501021 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 61492.498916 # average overall miss latency
841,842c715,716
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693796850 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791091662 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693797350 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791092162 # number of ReadReq MSHR miss cycles
845,846c719,720
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390499504 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390499504 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390498504 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390498504 # number of ReadExReq MSHR miss cycles
848,849c722,723
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084296354 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23181591166 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084295854 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23181590666 # number of demand (read+write) MSHR miss cycles
851,852c725,726
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084296354 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23181591166 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084295854 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 23181590666 # number of overall MSHR miss cycles
867,868c741,742
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.131845 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.396826 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.133075 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.398048 # average ReadReq mshr miss latency
871,872c745,746
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.124981 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.124981 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.109847 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.109847 # average ReadExReq mshr miss latency
874,875c748,749
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
877,878c751,752
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
879a754,879
> system.cpu.dcache.replacements 1532987 # number of replacements
> system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
> system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
> system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
> system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369162000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 67369162000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954940470 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 39954940470 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 107324102470 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 107324102470 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 107324102470 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 107324102470 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.508124 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.989278 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.989278 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 38495.249960 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 38495.249960 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
> system.cpu.dcache.writebacks::total 96322 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884240500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884240500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478487500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478487500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< host_inst_rate 118271 # Simulator instruction rate (inst/s)
< host_op_rate 161069 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 53384157 # Simulator tick rate (ticks/s)
< host_mem_usage 298364 # Number of bytes of host memory used
< host_seconds 11705.11 # Real time elapsed on the host
---
> host_inst_rate 53257 # Simulator instruction rate (inst/s)
> host_op_rate 72528 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 24038469 # Simulator tick rate (ticks/s)
> host_mem_usage 255596 # Number of bytes of host memory used
> host_seconds 25994.48 # Real time elapsed on the host
80c80
< system.physmem.totGap 624867513500 # Total gap between requests
---
> system.physmem.totGap 624867514500 # Total gap between requests
174,175c174,175
< system.physmem.totQLat 3316258619 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 18090208619 # Sum of mem lat for all requests
---
> system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests
181c181
< system.physmem.avgMemAccLat 38098.45 # Average memory access latency
---
> system.physmem.avgMemAccLat 38098.44 # Average memory access latency
249c249
< system.cpu.fetch.icacheStallCycles 354123352 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss
255,256c255,256
< system.cpu.fetch.BlockedCycles 133000859 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
259,261c259,261
< system.cpu.fetch.CacheLines 333825475 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 10767149 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 1215073364 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total)
265c265
< system.cpu.fetch.rateDist::0 614410423 50.57% 50.57% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total)
277c277
< system.cpu.fetch.rateDist::total 1215073364 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total)
281c281
< system.cpu.decode.BlockedCycles 105461627 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked
293,295c293,295
< system.cpu.rename.RunCycles 540789818 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 71593101 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 2966286071 # Number of instructions processed by rename
---
> system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename
299,301c299,301
< system.cpu.rename.RenamedOperands 2940514356 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 14121260893 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 13550785312 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups
304c304
< system.cpu.rename.UndoneMaps 947360714 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing
319c319
< system.cpu.iq.issued_per_cycle::samples 1215073364 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle
323c323
< system.cpu.iq.issued_per_cycle::0 379121475 31.20% 31.20% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle
335c335
< system.cpu.iq.issued_per_cycle::total 1215073364 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle
408c408
< system.cpu.iq.int_inst_queue_reads 6066277406 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads
431c431
< system.cpu.iew.iewDispSquashedInsts 1409393 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch
493c493
< system.cpu.idleCycles 34661808 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling
522,539c522,539
< system.cpu.icache.ReadReq_misses::cpu.inst 30836 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 30836 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 30836 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 30836 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 30836 # number of overall misses
< system.cpu.icache.overall_misses::total 30836 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 469688998 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 469688998 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 469688998 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 469688998 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 469688998 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 469688998 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 333825473 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 333825473 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 333825473 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 333825473 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 333825473 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 333825473 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses
> system.cpu.icache.overall_misses::total 30837 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses
546,551c546,551
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15231.839344 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 15231.839344 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 15231.839344 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 15231.839344 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15233.615397 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 15233.615397 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 15233.615397 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 15233.615397 # average overall miss latency
560,565c560,565
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2272 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 2272 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 2272 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 2272 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 2272 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 2272 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2273 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 2273 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 2273 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 2273 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 2273 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 2273 # number of overall MSHR hits
572,577c572,577
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379117998 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 379117998 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379117998 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 379117998 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379117998 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 379117998 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379116998 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 379116998 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379116998 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 379116998 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379116998 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 379116998 # number of overall MSHR miss cycles
584,589c584,589
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.580801 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.580801 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.545792 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.545792 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
591,716d590
< system.cpu.dcache.replacements 1532987 # number of replacements
< system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
< system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
< system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
< system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
< system.cpu.dcache.writebacks::total 96322 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
758,759c632,633
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128014500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837930500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128013500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837931500 # number of ReadReq miss cycles
761,763c635,637
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242870000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3242870000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 128014500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242869000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3242869000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 128013500 # number of demand (read+write) miss cycles
765,766c639,640
< system.cpu.l2cache.demand_miss_latency::total 29208815000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 128014500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 29208814000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 128013500 # number of overall miss cycles
768c642
< system.cpu.l2cache.overall_miss_latency::total 29208815000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 29208814000 # number of overall miss cycles
797,798c671,672
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.906289 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.351956 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.495273 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.354416 # average ReadReq miss latency
800,802c674,676
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.365560 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.365560 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.350425 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.350425 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
804,805c678,679
< system.cpu.l2cache.demand_avg_miss_latency::total 61492.501021 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 61492.498916 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
807c681
< system.cpu.l2cache.overall_avg_miss_latency::total 61492.501021 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 61492.498916 # average overall miss latency
841,842c715,716
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693796850 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791091662 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693797350 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791092162 # number of ReadReq MSHR miss cycles
845,846c719,720
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390499504 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390499504 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390498504 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390498504 # number of ReadExReq MSHR miss cycles
848,849c722,723
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084296354 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23181591166 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084295854 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23181590666 # number of demand (read+write) MSHR miss cycles
851,852c725,726
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084296354 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23181591166 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084295854 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 23181590666 # number of overall MSHR miss cycles
867,868c741,742
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.131845 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.396826 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.133075 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.398048 # average ReadReq mshr miss latency
871,872c745,746
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.124981 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.124981 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.109847 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.109847 # average ReadExReq mshr miss latency
874,875c748,749
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
877,878c751,752
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
879a754,879
> system.cpu.dcache.replacements 1532987 # number of replacements
> system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
> system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
> system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
> system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369162000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 67369162000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954940470 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 39954940470 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 107324102470 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 107324102470 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 107324102470 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 107324102470 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.508124 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.989278 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.989278 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 38495.249960 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 38495.249960 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
> system.cpu.dcache.writebacks::total 96322 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884240500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884240500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478487500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478487500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate