7,11c7,11
< host_inst_rate 70506 # Simulator instruction rate (inst/s)
< host_op_rate 96019 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 37458496 # Simulator tick rate (ticks/s)
< host_mem_usage 237496 # Number of bytes of host memory used
< host_seconds 19634.93 # Real time elapsed on the host
---
> host_inst_rate 76677 # Simulator instruction rate (inst/s)
> host_op_rate 104424 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 40737062 # Simulator tick rate (ticks/s)
> host_mem_usage 237976 # Number of bytes of host memory used
> host_seconds 18054.69 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 94839680 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 4230336 # Number of bytes written to this memory
< system.physmem.num_reads 1481870 # Number of read requests responded to by this memory
< system.physmem.num_writes 66099 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 128946726 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 290895 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 5751685 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 134698411 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 213952 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 94625728 # Number of bytes read from this memory
> system.physmem.bytes_read::total 94839680 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 213952 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 213952 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory
> system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3343 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1478527 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1481870 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 290895 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 128655830 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 128946726 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 290895 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 290895 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 5751685 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 5751685 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 5751685 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 290895 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 128655830 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 134698411 # Total bandwidth to/from this memory (bytes/s)
371a385
> system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses
372a387
> system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses
373a389
> system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses
374a391
> system.cpu.icache.ReadReq_avg_miss_latency::total 8807.319007 # average ReadReq miss latency
375a393
> system.cpu.icache.demand_avg_miss_latency::total 8807.319007 # average overall miss latency
376a395
> system.cpu.icache.overall_avg_miss_latency::total 8807.319007 # average overall miss latency
403a423
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
404a425
> system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
405a427
> system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
406a429
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5391.512471 # average ReadReq mshr miss latency
407a431
> system.cpu.icache.demand_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency
408a433
> system.cpu.icache.overall_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency
463a489
> system.cpu.dcache.ReadReq_miss_rate::total 0.003120 # miss rate for ReadReq accesses
464a491
> system.cpu.dcache.WriteReq_miss_rate::total 0.002965 # miss rate for WriteReq accesses
465a493
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000228 # miss rate for LoadLockedReq accesses
466a495
> system.cpu.dcache.demand_miss_rate::total 0.003078 # miss rate for demand accesses
467a497
> system.cpu.dcache.overall_miss_rate::total 0.003078 # miss rate for overall accesses
468a499
> system.cpu.dcache.ReadReq_avg_miss_latency::total 33834.598445 # average ReadReq miss latency
469a501
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34793.690065 # average WriteReq miss latency
470a503
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38166.666667 # average LoadLockedReq miss latency
471a505
> system.cpu.dcache.demand_avg_miss_latency::total 34081.493121 # average overall miss latency
472a507
> system.cpu.dcache.overall_avg_miss_latency::total 34081.493121 # average overall miss latency
509a545
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001928 # mshr miss rate for ReadReq accesses
510a547
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses
511a549
> system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses
512a551
> system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses
513a553
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34178.105737 # average ReadReq mshr miss latency
514a555
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32230.114990 # average WriteReq mshr miss latency
515a557
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency
516a559
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency
586a630
> system.cpu.l2cache.ReadReq_miss_rate::total 0.947305 # miss rate for ReadReq accesses
587a632
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999394 # miss rate for UpgradeReq accesses
588a634
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.908791 # miss rate for ReadExReq accesses
590a637
> system.cpu.l2cache.demand_miss_rate::total 0.945519 # miss rate for demand accesses
592a640
> system.cpu.l2cache.overall_miss_rate::total 0.945519 # miss rate for overall accesses
594a643
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34306.025346 # average ReadReq miss latency
595a645
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.322034 # average ReadExReq miss latency
597a648
> system.cpu.l2cache.demand_avg_miss_latency::total 34296.139278 # average overall miss latency
599a651
> system.cpu.l2cache.overall_avg_miss_latency::total 34296.139278 # average overall miss latency
646a699
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947286 # mshr miss rate for ReadReq accesses
647a701
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999394 # mshr miss rate for UpgradeReq accesses
648a703
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908791 # mshr miss rate for ReadExReq accesses
650a706
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.945500 # mshr miss rate for demand accesses
652a709
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.945500 # mshr miss rate for overall accesses
654a712
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31068.809993 # average ReadReq mshr miss latency
655a714
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
656a716
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.680993 # average ReadExReq mshr miss latency
658a719
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency
660a722
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency
< host_inst_rate 70506 # Simulator instruction rate (inst/s)
< host_op_rate 96019 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 37458496 # Simulator tick rate (ticks/s)
< host_mem_usage 237496 # Number of bytes of host memory used
< host_seconds 19634.93 # Real time elapsed on the host
---
> host_inst_rate 76677 # Simulator instruction rate (inst/s)
> host_op_rate 104424 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 40737062 # Simulator tick rate (ticks/s)
> host_mem_usage 237976 # Number of bytes of host memory used
> host_seconds 18054.69 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 94839680 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 4230336 # Number of bytes written to this memory
< system.physmem.num_reads 1481870 # Number of read requests responded to by this memory
< system.physmem.num_writes 66099 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 128946726 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 290895 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 5751685 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 134698411 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 213952 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 94625728 # Number of bytes read from this memory
> system.physmem.bytes_read::total 94839680 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 213952 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 213952 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory
> system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3343 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1478527 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1481870 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 290895 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 128655830 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 128946726 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 290895 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 290895 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 5751685 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 5751685 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 5751685 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 290895 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 128655830 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 134698411 # Total bandwidth to/from this memory (bytes/s)
371a385
> system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses
372a387
> system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses
373a389
> system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses
374a391
> system.cpu.icache.ReadReq_avg_miss_latency::total 8807.319007 # average ReadReq miss latency
375a393
> system.cpu.icache.demand_avg_miss_latency::total 8807.319007 # average overall miss latency
376a395
> system.cpu.icache.overall_avg_miss_latency::total 8807.319007 # average overall miss latency
403a423
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
404a425
> system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
405a427
> system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
406a429
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5391.512471 # average ReadReq mshr miss latency
407a431
> system.cpu.icache.demand_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency
408a433
> system.cpu.icache.overall_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency
463a489
> system.cpu.dcache.ReadReq_miss_rate::total 0.003120 # miss rate for ReadReq accesses
464a491
> system.cpu.dcache.WriteReq_miss_rate::total 0.002965 # miss rate for WriteReq accesses
465a493
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000228 # miss rate for LoadLockedReq accesses
466a495
> system.cpu.dcache.demand_miss_rate::total 0.003078 # miss rate for demand accesses
467a497
> system.cpu.dcache.overall_miss_rate::total 0.003078 # miss rate for overall accesses
468a499
> system.cpu.dcache.ReadReq_avg_miss_latency::total 33834.598445 # average ReadReq miss latency
469a501
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34793.690065 # average WriteReq miss latency
470a503
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38166.666667 # average LoadLockedReq miss latency
471a505
> system.cpu.dcache.demand_avg_miss_latency::total 34081.493121 # average overall miss latency
472a507
> system.cpu.dcache.overall_avg_miss_latency::total 34081.493121 # average overall miss latency
509a545
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001928 # mshr miss rate for ReadReq accesses
510a547
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses
511a549
> system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses
512a551
> system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses
513a553
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34178.105737 # average ReadReq mshr miss latency
514a555
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32230.114990 # average WriteReq mshr miss latency
515a557
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency
516a559
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency
586a630
> system.cpu.l2cache.ReadReq_miss_rate::total 0.947305 # miss rate for ReadReq accesses
587a632
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999394 # miss rate for UpgradeReq accesses
588a634
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.908791 # miss rate for ReadExReq accesses
590a637
> system.cpu.l2cache.demand_miss_rate::total 0.945519 # miss rate for demand accesses
592a640
> system.cpu.l2cache.overall_miss_rate::total 0.945519 # miss rate for overall accesses
594a643
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34306.025346 # average ReadReq miss latency
595a645
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.322034 # average ReadExReq miss latency
597a648
> system.cpu.l2cache.demand_avg_miss_latency::total 34296.139278 # average overall miss latency
599a651
> system.cpu.l2cache.overall_avg_miss_latency::total 34296.139278 # average overall miss latency
646a699
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947286 # mshr miss rate for ReadReq accesses
647a701
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999394 # mshr miss rate for UpgradeReq accesses
648a703
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908791 # mshr miss rate for ReadExReq accesses
650a706
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.945500 # mshr miss rate for demand accesses
652a709
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.945500 # mshr miss rate for overall accesses
654a712
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31068.809993 # average ReadReq mshr miss latency
655a714
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
656a716
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.680993 # average ReadExReq mshr miss latency
658a719
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency
660a722
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency