3,5c3,5
< sim_seconds 0.339013 # Number of seconds simulated
< sim_ticks 339012932000 # Number of ticks simulated
< final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.338999 # Number of seconds simulated
> sim_ticks 338998876000 # Number of ticks simulated
> final_tick 338998876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 218277 # Simulator instruction rate (inst/s)
< host_op_rate 268728 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 115505586 # Simulator tick rate (ticks/s)
< host_mem_usage 277356 # Number of bytes of host memory used
< host_seconds 2935.04 # Real time elapsed on the host
---
> host_inst_rate 210128 # Simulator instruction rate (inst/s)
> host_op_rate 258696 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 111189218 # Simulator tick rate (ticks/s)
> host_mem_usage 277020 # Number of bytes of host memory used
> host_seconds 3048.85 # Real time elapsed on the host
16,54c16,54
< system.physmem.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 269632 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 48043328 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 12965504 # Number of bytes read from this memory
< system.physmem.bytes_read::total 61278464 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 269632 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 269632 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4245696 # Number of bytes written to this memory
< system.physmem.bytes_written::total 4245696 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 4213 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 750677 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 202586 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 957476 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 66339 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 66339 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 795344 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 141715325 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 38244866 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 180755535 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 795344 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 795344 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 12523699 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 12523699 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 12523699 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 795344 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 141715325 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 38244866 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 193279235 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 957477 # Number of read requests accepted
< system.physmem.writeReqs 66339 # Number of write requests accepted
< system.physmem.readBursts 957477 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 66339 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 61258752 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 19776 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4240576 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 61278528 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 4245696 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 309 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 54 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 268928 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 48012032 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 12961152 # Number of bytes read from this memory
> system.physmem.bytes_read::total 61242112 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 268928 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 268928 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4244288 # Number of bytes written to this memory
> system.physmem.bytes_written::total 4244288 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 4202 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 750188 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 202518 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 956908 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 66317 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 66317 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 793301 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 141628883 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 38233613 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 180655797 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 793301 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 793301 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 12520065 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 12520065 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 12520065 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 793301 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 141628883 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 38233613 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 193175862 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 956909 # Number of read requests accepted
> system.physmem.writeReqs 66317 # Number of write requests accepted
> system.physmem.readBursts 956909 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 66317 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 61223936 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4238080 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 61242176 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 4244288 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 65 # Number of DRAM write bursts merged with an existing one
56,72c56,72
< system.physmem.perBankRdBursts::0 19910 # Per bank write bursts
< system.physmem.perBankRdBursts::1 19533 # Per bank write bursts
< system.physmem.perBankRdBursts::2 657271 # Per bank write bursts
< system.physmem.perBankRdBursts::3 20982 # Per bank write bursts
< system.physmem.perBankRdBursts::4 19710 # Per bank write bursts
< system.physmem.perBankRdBursts::5 21143 # Per bank write bursts
< system.physmem.perBankRdBursts::6 19634 # Per bank write bursts
< system.physmem.perBankRdBursts::7 20055 # Per bank write bursts
< system.physmem.perBankRdBursts::8 19495 # Per bank write bursts
< system.physmem.perBankRdBursts::9 20079 # Per bank write bursts
< system.physmem.perBankRdBursts::10 19428 # Per bank write bursts
< system.physmem.perBankRdBursts::11 19728 # Per bank write bursts
< system.physmem.perBankRdBursts::12 19649 # Per bank write bursts
< system.physmem.perBankRdBursts::13 21208 # Per bank write bursts
< system.physmem.perBankRdBursts::14 19490 # Per bank write bursts
< system.physmem.perBankRdBursts::15 19853 # Per bank write bursts
< system.physmem.perBankWrBursts::0 4286 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 19928 # Per bank write bursts
> system.physmem.perBankRdBursts::1 19580 # Per bank write bursts
> system.physmem.perBankRdBursts::2 657267 # Per bank write bursts
> system.physmem.perBankRdBursts::3 20958 # Per bank write bursts
> system.physmem.perBankRdBursts::4 19729 # Per bank write bursts
> system.physmem.perBankRdBursts::5 20737 # Per bank write bursts
> system.physmem.perBankRdBursts::6 19560 # Per bank write bursts
> system.physmem.perBankRdBursts::7 19988 # Per bank write bursts
> system.physmem.perBankRdBursts::8 19522 # Per bank write bursts
> system.physmem.perBankRdBursts::9 20089 # Per bank write bursts
> system.physmem.perBankRdBursts::10 19525 # Per bank write bursts
> system.physmem.perBankRdBursts::11 19708 # Per bank write bursts
> system.physmem.perBankRdBursts::12 19661 # Per bank write bursts
> system.physmem.perBankRdBursts::13 21032 # Per bank write bursts
> system.physmem.perBankRdBursts::14 19553 # Per bank write bursts
> system.physmem.perBankRdBursts::15 19787 # Per bank write bursts
> system.physmem.perBankWrBursts::0 4255 # Per bank write bursts
74,78c74,78
< system.physmem.perBankWrBursts::2 4145 # Per bank write bursts
< system.physmem.perBankWrBursts::3 4153 # Per bank write bursts
< system.physmem.perBankWrBursts::4 4249 # Per bank write bursts
< system.physmem.perBankWrBursts::5 4230 # Per bank write bursts
< system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 4143 # Per bank write bursts
> system.physmem.perBankWrBursts::3 4152 # Per bank write bursts
> system.physmem.perBankWrBursts::4 4244 # Per bank write bursts
> system.physmem.perBankWrBursts::5 4226 # Per bank write bursts
> system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
82c82
< system.physmem.perBankWrBursts::10 4094 # Per bank write bursts
---
> system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
84,85c84,85
< system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
< system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 4097 # Per bank write bursts
> system.physmem.perBankWrBursts::13 4095 # Per bank write bursts
87c87
< system.physmem.perBankWrBursts::15 4149 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 4152 # Per bank write bursts
90c90
< system.physmem.totGap 339012921500 # Total gap between requests
---
> system.physmem.totGap 338998865500 # Total gap between requests
97c97
< system.physmem.readPktSize::6 957477 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 956909 # Read request sizes (log2)
104,119c104,119
< system.physmem.writePktSize::6 66339 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 764538 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 120546 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 15621 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 6697 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 6433 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 7720 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 9109 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 10145 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 6841 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 3643 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 2525 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1571 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1107 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 66317 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 764114 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 120431 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 15489 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 6466 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 7783 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 9162 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 10166 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 6863 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 3709 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 2433 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1574 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1088 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 644 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
152,192c152,192
< system.physmem.wrQLenPdf::15 537 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 883 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 1456 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 2089 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 2622 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 3068 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 3545 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4065 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 4483 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 4939 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5348 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5856 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4797 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4234 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4114 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 74 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 66 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 67 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 52 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 41 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 43 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 28 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 13 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 553 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 600 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 931 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 1459 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 2107 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 2610 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 3064 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 3520 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 4015 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4546 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 4994 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5464 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5885 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5988 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4751 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4208 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4080 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 88 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 64 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 54 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 51 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 36 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 23 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see
194c194
< system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
201,260c201,256
< system.physmem.bytesPerActivate::samples 195212 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 335.517735 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 192.597798 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 355.506182 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 64341 32.96% 32.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 60661 31.07% 64.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 15753 8.07% 72.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3211 1.64% 73.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3578 1.83% 75.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2458 1.26% 76.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2478 1.27% 78.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 34211 17.53% 95.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8521 4.36% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 195212 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 3994 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 204.692539 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 35.349556 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2360.542955 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 3971 99.42% 99.42% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::4096-8191 10 0.25% 99.67% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::8192-12287 5 0.13% 99.80% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::12288-16383 1 0.03% 99.82% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.85% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.87% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::28672-32767 1 0.03% 99.90% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.92% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::69632-73727 1 0.03% 99.97% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::98304-102399 1 0.03% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 3994 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 3994 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.589634 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.506417 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.926291 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3368 84.33% 84.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 17 0.43% 84.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 396 9.91% 94.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 46 1.15% 95.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 24 0.60% 96.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 17 0.43% 96.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 21 0.53% 97.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 18 0.45% 97.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 15 0.38% 98.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 17 0.43% 98.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 13 0.33% 98.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 10 0.25% 99.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28 7 0.18% 99.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::29 8 0.20% 99.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30 8 0.20% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32 4 0.10% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::33 1 0.03% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34 1 0.03% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::35 1 0.03% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::37 1 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::39 1 0.03% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 3994 # Writes before turning the bus around for reads
< system.physmem.totQLat 27473404757 # Total ticks spent queuing
< system.physmem.totMemAccLat 45420304757 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 4785840000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 28702.80 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 195260 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 335.246789 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 192.210032 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 355.737014 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 64653 33.11% 33.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 60691 31.08% 64.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 15519 7.95% 72.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3195 1.64% 73.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3493 1.79% 75.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2388 1.22% 76.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2513 1.29% 78.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 34304 17.57% 95.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8504 4.36% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 195260 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 3991 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 173.742922 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 35.179059 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 1709.732000 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-4095 3971 99.50% 99.50% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.72% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::8192-12287 3 0.08% 99.80% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::12288-16383 3 0.08% 99.87% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.90% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.92% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.95% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::73728-77823 1 0.03% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 3991 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 3991 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.592333 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.512127 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.873555 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3350 83.94% 83.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 21 0.53% 84.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 395 9.90% 94.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 55 1.38% 95.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 24 0.60% 96.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 19 0.48% 96.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 17 0.43% 97.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 26 0.65% 97.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 20 0.50% 98.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 16 0.40% 98.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 9 0.23% 99.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 11 0.28% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28 7 0.18% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::29 5 0.13% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::30 4 0.10% 99.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::31 6 0.15% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32 1 0.03% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::33 3 0.08% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::34 2 0.05% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 3991 # Writes before turning the bus around for reads
> system.physmem.totQLat 27417238749 # Total ticks spent queuing
> system.physmem.totMemAccLat 45353938749 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 4783120000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 28660.41 # Average queueing delay per DRAM burst
262,265c258,261
< system.physmem.avgMemAccLat 47452.80 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 180.70 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 12.51 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 180.76 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 47410.41 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 180.60 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 180.66 # Average system read bandwidth in MiByte/s
272,322c268,318
< system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing
< system.physmem.readRowHits 805066 # Number of row buffer hits during reads
< system.physmem.writeRowHits 23137 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 84.11 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 34.91 # Row buffer hit rate for writes
< system.physmem.avgGap 331126.81 # Average gap between requests
< system.physmem.pageHitRate 80.92 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 894020820 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 475164360 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 5699412180 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 174541140 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 27331811520.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 14462317590 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 674820000 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 138340924320 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 704060640 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 673701120.000000 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 189477322380 # Total energy per rank (pJ)
< system.physmem_0.averagePower 558.908824 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 305437641889 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 528629764 # Time in different power states
< system.physmem_0.memoryStateTime::REF 11569144000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 223118500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 1833570381 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 21477516347 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 303380953008 # Time in different power states
< system.physmem_1.actEnergy 499878540 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 265665180 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1134760200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 171330840 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 25420895760.000004 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 7011060990 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1362065280 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 70491607590 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 31027049280 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 25487678070 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 162872491950 # Total energy per rank (pJ)
< system.physmem_1.averagePower 480.431501 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 320089357075 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 2604072271 # Time in different power states
< system.physmem_1.memoryStateTime::REF 10809446000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 84703185250 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 80799625521 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 5510033904 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 154586569054 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 174656775 # Number of BP lookups
< system.cpu.branchPred.condPredicted 119110803 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 4015685 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 96721345 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 67754534 # Number of BTB hits
---
> system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing
> system.physmem.readRowHits 804753 # Number of row buffer hits during reads
> system.physmem.writeRowHits 22823 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 84.12 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 34.45 # Row buffer hit rate for writes
> system.physmem.avgGap 331304.00 # Average gap between requests
> system.physmem.pageHitRate 80.91 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 893206860 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 474750705 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 5695906440 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 174321900 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 27330582240.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 14459296590 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 677245920 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 138340780680 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 698740320 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 673162065.000000 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 189465949500 # Total energy per rank (pJ)
> system.physmem_0.averagePower 558.898453 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 305423895331 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 532417778 # Time in different power states
> system.physmem_0.memoryStateTime::REF 11568510000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 220427000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 1819753036 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 21474052891 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 303383715295 # Time in different power states
> system.physmem_1.actEnergy 500999520 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 266260995 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1134381780 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 171346500 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 25447939920.000004 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 7069016310 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1362680640 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 70550856240 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 31070458080 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 25392894210 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 162967325295 # Total energy per rank (pJ)
> system.physmem_1.averagePower 480.731167 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 319946801176 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 2603762514 # Time in different power states
> system.physmem_1.memoryStateTime::REF 10820898000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 84317463250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 80912710040 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 5627391560 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 154716650636 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 174659469 # Number of BP lookups
> system.cpu.branchPred.condPredicted 119114964 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 4015677 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 96720579 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 67753891 # Number of BTB hits
324,330c320,326
< system.cpu.branchPred.BTBHitPct 70.051274 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 18785121 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1299599 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 16716580 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 16702336 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 14244 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 1279516 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 70.051164 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 18782444 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 16716760 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 16702354 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 14406 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 1279517 # Number of mispredicted indirect branches.
332c328
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
362c358
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
392c388
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
422c418
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
453,454c449,450
< system.cpu.pwrStateResidencyTicks::ON 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 678025865 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 677997753 # number of cpu cycles simulated
457,463c453,459
< system.cpu.fetch.icacheStallCycles 34354212 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 824273790 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 174656775 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 103241991 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 639159762 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 8068079 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 2457 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.icacheStallCycles 35007390 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 824275552 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 174659469 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 103238689 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 638483488 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 3174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
465,470c461,466
< system.cpu.fetch.IcacheWaitRetryStallCycles 3206 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 247740942 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 12520 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 677553693 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.500365 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.263651 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 3169 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 247736654 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 13165 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 677531262 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.500399 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.263726 # Number of instructions fetched each cycle (Total)
472,475c468,471
< system.cpu.fetch.rateDist::0 215486043 31.80% 31.80% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 148340760 21.89% 53.70% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 72943473 10.77% 64.46% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 240783417 35.54% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 215511441 31.81% 31.81% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 148279019 21.89% 53.69% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 72933920 10.76% 64.46% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 240806882 35.54% 100.00% # Number of instructions fetched each cycle (Total)
479,505c475,501
< system.cpu.fetch.rateDist::total 677553693 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.257596 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.215697 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 75112537 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 258679606 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 277758053 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 61982472 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 4021025 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 20810112 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 13117 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 924576668 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 11804380 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 4021025 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 118056358 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 157938220 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 213059 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 294555904 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 102769127 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 906541450 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 6890856 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 27990855 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2220094 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 49338949 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 500517 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 980921468 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 4318014727 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1001837715 # Number of integer rename lookups
---
> system.cpu.fetch.rateDist::total 677531262 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.257611 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.215750 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 75755548 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 258011846 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 277771746 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 61971111 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 4021011 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 20808683 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 13107 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 924572936 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 11806711 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 4021011 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 118697379 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 157348847 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 212785 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 295131252 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 102119988 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 906539563 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 6891328 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 27972681 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 2218640 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 49279009 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 483149 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 980928941 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 4318000809 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1001835244 # Number of integer rename lookups
508,525c504,521
< system.cpu.rename.UndoneMaps 106143238 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 6855 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 6838 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 138815476 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 271882151 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 160587217 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 6164479 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 12153288 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 899827421 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 860030622 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 9216880 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 111115045 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 244388609 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 677553693 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.269317 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.101593 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 106150711 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 6840 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 138234074 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 271880895 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 160585540 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 6163609 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 12157039 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 899825913 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 12585 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 860027802 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 9216351 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 111113540 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 244391790 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 677531262 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.269355 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.103879 # Number of insts issued each cycle
527,532c523,528
< system.cpu.iq.issued_per_cycle::0 214894884 31.72% 31.72% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 182407403 26.92% 58.64% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 175555467 25.91% 84.55% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 92273782 13.62% 98.17% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 12419846 1.83% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 215443123 31.80% 31.80% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 182412778 26.92% 58.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 173833847 25.66% 84.38% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 93421038 13.79% 98.17% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 12418164 1.83% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 2312 0.00% 100.00% # Number of insts issued each cycle
539c535
< system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 677531262 # Number of insts issued each cycle
541,542c537,538
< system.cpu.iq.fu_full::IntAlu 66603323 23.99% 23.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 18142 0.01% 24.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 66604023 24.00% 24.00% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 18144 0.01% 24.00% # attempts to use FU when none available
572,575c568,571
< system.cpu.iq.fu_full::MemRead 133475448 48.09% 72.32% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 66440411 23.94% 96.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 5100435 1.84% 98.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemWrite 5300037 1.91% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 132902314 47.88% 72.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 66436214 23.93% 96.05% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 5673709 2.04% 98.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemWrite 5298999 1.91% 100.00% # attempts to use FU when none available
579,580c575,576
< system.cpu.iq.FU_type_0::IntAlu 413090046 48.03% 48.03% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5187659 0.60% 48.64% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 413088657 48.03% 48.03% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5187663 0.60% 48.64% # Type of FU issued
604c600
< system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCvt 2550152 0.30% 49.38% # Type of FU issued
606c602
< system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 11478195 1.33% 50.71% # Type of FU issued
610,612c606,608
< system.cpu.iq.FU_type_0::MemRead 259646740 30.19% 80.90% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 153401509 17.84% 98.74% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemRead 7019167 0.82% 99.55% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 259646328 30.19% 80.90% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 153400482 17.84% 98.74% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemRead 7019166 0.82% 99.55% # Type of FU issued
616,628c612,624
< system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued
< system.cpu.iq.rate 1.268433 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 277574685 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.322750 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 2622330507 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 62075995 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 1101050958 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 36554349 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 860027802 # Type of FU issued
> system.cpu.iq.rate 1.268482 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 277570292 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.322746 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 2621725269 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 980329256 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 820080739 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 62648240 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 30641595 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 24878674 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 1100471505 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 37126589 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 13986954 # Number of loads that had data forwarded from stores
630,633c626,629
< system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 120 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 18827 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 31606721 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 19639957 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 122 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 18816 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 31605044 # Number of stores squashed
636,637c632,633
< system.cpu.iew.lsq.thread0.rescheduledLoads 1918912 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 17820 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 1918903 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 17949 # Number of times an access to memory failed due to the cache being blocked
639,642c635,638
< system.cpu.iew.iewSquashCycles 4021025 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 10591534 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 6199 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 899849877 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 4021011 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 10591594 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 7946 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 899848641 # Number of instructions dispatched to IQ
644,655c640,651
< system.cpu.iew.iewDispLoadInsts 271882151 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 160587217 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 967 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 18827 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3295145 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3289956 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 6585101 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 850175089 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 263374398 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 9855533 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 271880895 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 160585540 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 6845 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 5082 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 18816 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 3295133 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3290188 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 6585321 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 850172394 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 263373871 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 9855408 # Number of squashed instructions skipped in execute
657,668c653,664
< system.cpu.iew.exec_nop 9874 # number of nop insts executed
< system.cpu.iew.exec_refs 416064413 # number of memory reference insts executed
< system.cpu.iew.exec_branches 143381564 # Number of branches executed
< system.cpu.iew.exec_stores 152690015 # Number of stores executed
< system.cpu.iew.exec_rate 1.253898 # Inst execution rate
< system.cpu.iew.wb_sent 846298256 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 844962326 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 487342605 # num instructions producing a value
< system.cpu.iew.wb_consumers 808106527 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.246210 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.603067 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 103169288 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 10143 # number of nop insts executed
> system.cpu.iew.exec_refs 416062863 # number of memory reference insts executed
> system.cpu.iew.exec_branches 143380865 # Number of branches executed
> system.cpu.iew.exec_stores 152688992 # Number of stores executed
> system.cpu.iew.exec_rate 1.253946 # Inst execution rate
> system.cpu.iew.wb_sent 846295545 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 844959413 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 486195731 # num instructions producing a value
> system.cpu.iew.wb_consumers 804663900 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.246257 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.604222 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 103166103 # The number of squashed insts skipped by commit
670,673c666,669
< system.cpu.commit.branchMispredicts 4002671 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 662973012 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.189687 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.047483 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 4002664 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 662950558 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.189727 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.047510 # Number of insts commited each cycle
675,683c671,679
< system.cpu.commit.committed_per_cycle::0 372633677 56.21% 56.21% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 137240232 20.70% 76.91% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 51341106 7.74% 84.65% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 28220443 4.26% 88.91% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 14381462 2.17% 91.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 14774618 2.23% 93.31% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 7871678 1.19% 94.49% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 6561077 0.99% 95.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 29948719 4.52% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 372609039 56.20% 56.20% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 137243840 20.70% 76.91% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 51342182 7.74% 84.65% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 28218977 4.26% 88.91% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 14379686 2.17% 91.08% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 14774384 2.23% 93.31% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 7871744 1.19% 94.49% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 6561841 0.99% 95.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 29948865 4.52% 100.00% # Number of insts commited each cycle
687c683
< system.cpu.commit.committed_per_cycle::total 662973012 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 662950558 # Number of insts commited each cycle
737,741c733,737
< system.cpu.commit.bw_lim_events 29948719 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 1524914900 # The number of ROB reads
< system.cpu.rob.rob_writes 1798382781 # The number of ROB writes
< system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 472172 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 29948865 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 1524889115 # The number of ROB reads
> system.cpu.rob.rob_writes 1798376442 # The number of ROB writes
> system.cpu.timesIdled 10544 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 466491 # Total number of cycles that the CPU has spent unscheduled due to idling
744,754c740,750
< system.cpu.cpi 1.058342 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.058342 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.944874 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.944874 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 868463326 # number of integer regfile reads
< system.cpu.int_regfile_writes 500698648 # number of integer regfile writes
< system.cpu.fp_regfile_reads 30616063 # number of floating regfile reads
< system.cpu.fp_regfile_writes 22959490 # number of floating regfile writes
< system.cpu.cc_regfile_reads 3322389826 # number of cc regfile reads
< system.cpu.cc_regfile_writes 369207773 # number of cc regfile writes
< system.cpu.misc_regfile_reads 606833337 # number of misc regfile reads
---
> system.cpu.cpi 1.058298 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.058298 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.944914 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.944914 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 868460616 # number of integer regfile reads
> system.cpu.int_regfile_writes 500698081 # number of integer regfile writes
> system.cpu.fp_regfile_reads 30616065 # number of floating regfile reads
> system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes
> system.cpu.cc_regfile_reads 3322380162 # number of cc regfile reads
> system.cpu.cc_regfile_writes 369206587 # number of cc regfile writes
> system.cpu.misc_regfile_reads 606831817 # number of misc regfile reads
756,763c752,759
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 2756453 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.911144 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 371050846 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 2756965 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 134.586709 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 285699000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.911144 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 2756456 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.910987 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 371049565 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2756968 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 134.586098 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 285993000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.910987 # Average occupied blocks per requestor
768,769c764,765
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id
772,778c768,774
< system.cpu.dcache.tags.tag_accesses 751747893 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 751747893 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 243127355 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 243127355 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 127907428 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 127907428 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 751745414 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 751745414 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 243126159 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 243126159 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 127907378 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 127907378 # number of WriteReq hits
785,792c781,788
< system.cpu.dcache.demand_hits::cpu.data 371034783 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 371034783 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 371037940 # number of overall hits
< system.cpu.dcache.overall_hits::total 371037940 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2401348 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2401348 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1044049 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1044049 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 371033537 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 371033537 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 371036694 # number of overall hits
> system.cpu.dcache.overall_hits::total 371036694 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2401303 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2401303 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1044099 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1044099 # number of WriteReq misses
797,804c793,800
< system.cpu.dcache.demand_misses::cpu.data 3445397 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3445397 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3446044 # number of overall misses
< system.cpu.dcache.overall_misses::total 3446044 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 80462385500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 80462385500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10017236850 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10017236850 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 3445402 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3445402 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3446049 # number of overall misses
> system.cpu.dcache.overall_misses::total 3446049 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 80431299000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 80431299000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9946595850 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9946595850 # number of WriteReq miss cycles
807,812c803,808
< system.cpu.dcache.demand_miss_latency::cpu.data 90479622350 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 90479622350 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 90479622350 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 90479622350 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 245528703 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 245528703 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 90377894850 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 90377894850 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 90377894850 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 90377894850 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 245527462 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 245527462 # number of ReadReq accesses(hits+misses)
821,824c817,820
< system.cpu.dcache.demand_accesses::cpu.data 374480180 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 374480180 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 374483984 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 374483984 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 374478939 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 374478939 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 374482743 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 374482743 # number of overall (read+write) accesses
827,828c823,824
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008096 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.008096 # miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008097 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.008097 # miss rate for WriteReq accesses
833,834c829,830
< system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.009201 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.009201 # miss rate for demand accesses
837,840c833,836
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33507.174096 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 33507.174096 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9594.604133 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 9594.604133 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33494.856334 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 33494.856334 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9526.487287 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 9526.487287 # average WriteReq miss latency
843,858c839,854
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 26261.015015 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26261.015015 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 26256.084470 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 26256.084470 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 71 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 355259 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 4691 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 75.732040 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 2756453 # number of writebacks
< system.cpu.dcache.writebacks::total 2756453 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365871 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 365871 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323013 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 323013 # number of WriteReq MSHR hits
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 26231.451323 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26231.451323 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 26226.526335 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 26226.526335 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 336970 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 4742 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 71.060734 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 2756456 # number of writebacks
> system.cpu.dcache.writebacks::total 2756456 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365826 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 365826 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323069 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 323069 # number of WriteReq MSHR hits
861,864c857,860
< system.cpu.dcache.demand_mshr_hits::cpu.data 688884 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 688884 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 688884 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 688884 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 688895 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 688895 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 688895 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 688895 # number of overall MSHR hits
867,868c863,864
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721036 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 721036 # number of WriteReq MSHR misses
---
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721030 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 721030 # number of WriteReq MSHR misses
871,884c867,880
< system.cpu.dcache.demand_mshr_misses::cpu.data 2756513 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2756513 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2757155 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2757155 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75218139500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 75218139500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959023850 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959023850 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5957500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5957500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81177163350 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 81177163350 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81183120850 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 81183120850 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75180323500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 75180323500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5949856850 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5949856850 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5764000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5764000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81130180350 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 81130180350 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81135944350 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 81135944350 # number of overall MSHR miss cycles
887,888c883,884
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses
895,914c891,910
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36953.568869 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36953.568869 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8264.530273 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8264.530273 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9279.595016 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9279.595016 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29449.222024 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 29449.222024 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29444.525553 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 29444.525553 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1979522 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.550232 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 245757624 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 124.118006 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 275112500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.550232 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.997168 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.997168 # Average percentage of cache occupancy
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36934.990422 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36934.990422 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8251.885289 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8251.885289 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8978.193146 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8978.193146 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29432.241728 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 29432.241728 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29427.479019 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 29427.479019 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1980154 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.083769 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 245752724 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1980664 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 124.075928 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 275035500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.083769 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.998210 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy
917c913
< system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id
919,920c915
< system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::4 334 # Occupied blocks per task id
922,963c917,958
< system.cpu.icache.tags.tag_accesses 497462038 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 497462038 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 245757684 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 245757684 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 245757684 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 245757684 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 245757684 # number of overall hits
< system.cpu.icache.overall_hits::total 245757684 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1983224 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1983224 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1983224 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1983224 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1983224 # number of overall misses
< system.cpu.icache.overall_misses::total 1983224 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 16215368926 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 16215368926 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 16215368926 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 16215368926 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 16215368926 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 16215368926 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 247740908 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 247740908 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 247740908 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 247740908 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 247740908 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 247740908 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.266991 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 8176.266991 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 8176.266991 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 8176.266991 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 83168 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 761 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 2904 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 497454087 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 497454087 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 245752746 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 245752746 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 245752746 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 245752746 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 245752746 # number of overall hits
> system.cpu.icache.overall_hits::total 245752746 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1983875 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1983875 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1983875 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1983875 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1983875 # number of overall misses
> system.cpu.icache.overall_misses::total 1983875 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 16221042426 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 16221042426 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 16221042426 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 16221042426 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 16221042426 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 16221042426 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 247736621 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 247736621 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 247736621 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 247736621 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 247736621 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 247736621 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008008 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.008008 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.008008 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.008008 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.008008 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.008008 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.443791 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 8176.443791 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 8176.443791 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 8176.443791 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 85075 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 747 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 2929 # number of cycles access was blocked
965,1002c960,997
< system.cpu.icache.avg_blocked_cycles::no_mshrs 28.639118 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 108.714286 # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks
< system.cpu.icache.writebacks::total 1979522 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3000 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 3000 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 3000 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 3000 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 3000 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 3000 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980224 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1980224 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1980224 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1980224 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1980224 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1980224 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15180539440 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 15180539440 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15180539440 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 15180539440 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15180539440 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 15180539440 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.071838 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.071838 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 1350153 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 1355017 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 4256 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 29.045749 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 106.714286 # average number of cycles each access was blocked
> system.cpu.icache.writebacks::writebacks 1980154 # number of writebacks
> system.cpu.icache.writebacks::total 1980154 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3028 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 3028 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 3028 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 3028 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 3028 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 3028 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980847 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1980847 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1980847 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1980847 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1980847 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1980847 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15183658439 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 15183658439 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15183658439 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 15183658439 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15183658439 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 15183658439 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007996 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.007996 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.007996 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7665.235346 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7665.235346 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 1350785 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 1355219 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 3879 # number of redundant prefetches already in prefetch queue
1005,1011c1000,1006
< system.cpu.l2cache.prefetcher.pfSpanPage 4789879 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 297323 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 16097.800949 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3937547 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 313525 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.558957 # Average number of references to valid blocks.
---
> system.cpu.l2cache.prefetcher.pfSpanPage 4789973 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 297120 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 16096.917401 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3841839 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 313315 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 12.261906 # Average number of references to valid blocks.
1013,1019c1008,1014
< system.cpu.l2cache.tags.occ_blocks::writebacks 15677.943381 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 419.857568 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.956906 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025626 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.982532 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 424 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15778 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 15676.222250 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.695151 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.956801 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025677 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.982478 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 430 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id
1021,1023c1016,1018
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 273 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 263 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id
1025,1085c1020,1080
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3670 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10056 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025879 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963013 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 145579085 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 145579085 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 735952 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 735952 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 3357075 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 3357075 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 718660 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 718660 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975820 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1975820 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1285803 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 1285803 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 1975820 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 2004463 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3980283 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 1975820 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 2004463 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3980283 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 190 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 190 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 2186 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 2186 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4215 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 4215 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750316 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 750316 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 4215 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 752502 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 756717 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 4215 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 752502 # number of overall misses
< system.cpu.l2cache.overall_misses::total 756717 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 197785000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 197785000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351484000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 351484000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63803558500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 63803558500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 351484000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 64001343500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 64352827500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 351484000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 64001343500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 64352827500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 735952 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 735952 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 3357075 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 3357075 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 190 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980035 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1980035 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3686 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10031 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.026245 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 145605931 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 145605931 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 735798 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 735798 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 3358223 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 3358223 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 718689 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 718689 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976463 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1976463 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286254 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 1286254 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 1976463 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 2004943 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3981406 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 1976463 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 2004943 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3981406 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 181 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 181 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 2160 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 2160 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4204 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 4204 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749865 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 749865 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 4204 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 752025 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 756229 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 4204 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 752025 # number of overall misses
> system.cpu.l2cache.overall_misses::total 756229 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 187813000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 187813000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 349759500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 349759500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63761970000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 63761970000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 349759500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 63949783000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 64299542500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 349759500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 63949783000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 64299542500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 735798 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 735798 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 3358223 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 3358223 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 181 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 181 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980667 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1980667 # number of ReadCleanReq accesses(hits+misses)
1088,1093c1083,1088
< system.cpu.l2cache.demand_accesses::cpu.inst 1980035 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 2756965 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 4737000 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1980035 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 2756965 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 4737000 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1980667 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2756968 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 4737635 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1980667 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2756968 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 4737635 # number of overall (read+write) accesses
1096,1119c1091,1114
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003033 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.003033 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002129 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002129 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368503 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368503 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002129 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.272946 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.159746 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002129 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.272946 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.159746 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90478.042086 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90478.042086 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83388.849348 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83388.849348 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85035.583008 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85035.583008 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 85042.132660 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 85042.132660 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002996 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.002996 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002123 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002123 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368282 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368282 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002123 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.272772 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.159622 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002123 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.272772 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.159622 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86950.462963 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86950.462963 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83196.836346 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83196.836346 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85031.265628 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85031.265628 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 85026.549498 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 85026.549498 # average overall miss latency
1126,1130c1121,1125
< system.cpu.l2cache.unused_prefetches 3567 # number of HardPF blocks evicted w/o reference
< system.cpu.l2cache.writebacks::writebacks 66339 # number of writebacks
< system.cpu.l2cache.writebacks::total 66339 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 799 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 799 # number of ReadExReq MSHR hits
---
> system.cpu.l2cache.unused_prefetches 3549 # number of HardPF blocks evicted w/o reference
> system.cpu.l2cache.writebacks::writebacks 66317 # number of writebacks
> system.cpu.l2cache.writebacks::total 66317 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 785 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 785 # number of ReadExReq MSHR hits
1133,1134c1128,1129
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1026 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1026 # number of ReadSharedReq MSHR hits
---
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1052 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1052 # number of ReadSharedReq MSHR hits
1136,1137c1131,1132
< system.cpu.l2cache.demand_mshr_hits::cpu.data 1825 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 1826 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 1837 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 1838 # number of demand (read+write) MSHR hits
1139,1174c1134,1169
< system.cpu.l2cache.overall_mshr_hits::cpu.data 1825 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 1826 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202675 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 202675 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 190 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 190 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4214 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4214 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 749290 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749290 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 4214 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 750677 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 754891 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 4214 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 750677 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202675 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 957566 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20310287954 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2871000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2871000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 146425000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 146425000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 326144500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 326144500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59240775500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59240775500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 326144500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59387200500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 59713345000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 326144500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59387200500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 80023632954 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 1837 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 1838 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202613 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 202613 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 181 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 181 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1375 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 1375 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4203 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4203 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748813 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748813 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 4203 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 750188 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 754391 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 4203 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 750188 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202613 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 957004 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20275662144 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2881000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2881000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 136635500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 136635500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 324486000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 324486000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59198284500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59198284500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 324486000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59334920000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 59659406000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 324486000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59334920000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 79935068144 # number of overall MSHR miss cycles
1179,1189c1174,1184
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002128 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367999 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367999 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.159361 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002122 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367765 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367765 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.159234 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for overall accesses
1191,1213c1186,1208
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.202146 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100211.116092 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15110.526316 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15110.526316 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 105569.574621 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 105569.574621 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77395.467489 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77395.467489 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79062.546544 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79062.546544 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79101.943194 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83569.835347 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 9473354 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736191 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 89 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 88 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.202000 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100070.884613 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15917.127072 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15917.127072 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99371.272727 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99371.272727 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77203.426124 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77203.426124 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79056.165558 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79056.165558 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79082.870819 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83526.367856 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 9474606 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736642 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1215,1225c1210,1220
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 4016341 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 802291 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 4000023 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 230984 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 255300 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 190 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 190 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980224 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 4016964 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 802115 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 4000812 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 230803 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 255056 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 181 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 181 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980847 # Transaction distribution
1227,1237c1222,1232
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939779 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270763 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 14210542 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858752 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 606270272 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 552812 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 4257792 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 5290002 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.121634 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.326863 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5941666 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270754 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 14212420 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253492416 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859136 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 606351552 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 552356 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 4255808 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 5290172 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.121625 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.326853 # Request fanout histogram
1239,1240c1234,1235
< system.cpu.toL2Bus.snoop_fanout::0 4646559 87.84% 87.84% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 643442 12.16% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 4646755 87.84% 87.84% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 643416 12.16% 100.00% # Request fanout histogram
1245,1246c1240,1241
< system.cpu.toL2Bus.snoop_fanout::total 5290002 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 9472652000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 5290172 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 9473913000 # Layer occupancy (ticks)
1248c1243
< system.cpu.toL2Bus.respLayer0.occupancy 2970335495 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2971268997 # Layer occupancy (ticks)
1250c1245
< system.cpu.toL2Bus.respLayer1.occupancy 4135554975 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 4135554476 # Layer occupancy (ticks)
1252,1253c1247,1248
< system.membus.snoop_filter.tot_requests 1254990 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 940467 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.snoop_filter.tot_requests 1254210 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 939897 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1258,1269c1253,1264
< system.membus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 956088 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 66339 # Transaction distribution
< system.membus.trans_dist::CleanEvict 230984 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 190 # Transaction distribution
< system.membus.trans_dist::ReadExReq 1387 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1387 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 956090 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2212465 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 2212465 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65524096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 65524096 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 955532 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 66317 # Transaction distribution
> system.membus.trans_dist::CleanEvict 230803 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 181 # Transaction distribution
> system.membus.trans_dist::ReadExReq 1375 # Transaction distribution
> system.membus.trans_dist::ReadExResp 1375 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 955534 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211117 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 2211117 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65486336 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 65486336 # Cumulative packet size per connected master and slave (bytes)
1272c1267
< system.membus.snoop_fanout::samples 957667 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 957090 # Request fanout histogram
1276c1271
< system.membus.snoop_fanout::0 957667 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 957090 100.00% 100.00% # Request fanout histogram
1281,1282c1276,1277
< system.membus.snoop_fanout::total 957667 # Request fanout histogram
< system.membus.reqLayer0.occupancy 1758860478 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 957090 # Request fanout histogram
> system.membus.reqLayer0.occupancy 1757256327 # Layer occupancy (ticks)
1284c1279
< system.membus.respLayer1.occupancy 5031633569 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 5028523066 # Layer occupancy (ticks)