3,5c3,5
< sim_seconds 0.326731 # Number of seconds simulated
< sim_ticks 326731324000 # Number of ticks simulated
< final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.327896 # Number of seconds simulated
> sim_ticks 327895638000 # Number of ticks simulated
> final_tick 327895638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 165193 # Simulator instruction rate (inst/s)
< host_op_rate 203374 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 84248396 # Simulator tick rate (ticks/s)
< host_mem_usage 272920 # Number of bytes of host memory used
< host_seconds 3878.19 # Real time elapsed on the host
---
> host_inst_rate 125299 # Simulator instruction rate (inst/s)
> host_op_rate 154259 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 64130088 # Simulator tick rate (ticks/s)
> host_mem_usage 277300 # Number of bytes of host memory used
> host_seconds 5112.98 # Real time elapsed on the host
16,54c16,54
< system.physmem.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory
< system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory
< system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 953240 # Number of read requests accepted
< system.physmem.writeReqs 66334 # Number of write requests accepted
< system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue
< system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 266368 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 48003200 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 12980224 # Number of bytes read from this memory
> system.physmem.bytes_read::total 61249792 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 266368 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 266368 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4244096 # Number of bytes written to this memory
> system.physmem.bytes_written::total 4244096 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 4162 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 750050 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 202816 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 957028 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 66314 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 66314 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 812356 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 146397800 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 39586449 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 186796605 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 812356 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 812356 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 12943435 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 12943435 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 12943435 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 812356 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 146397800 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 39586449 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 199740040 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 957029 # Number of read requests accepted
> system.physmem.writeReqs 66314 # Number of write requests accepted
> system.physmem.readBursts 957029 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 66314 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 61231232 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4237440 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 61249856 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 4244096 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 72 # Number of DRAM write bursts merged with an existing one
56,77c56,77
< system.physmem.perBankRdBursts::0 19685 # Per bank write bursts
< system.physmem.perBankRdBursts::1 19287 # Per bank write bursts
< system.physmem.perBankRdBursts::2 657567 # Per bank write bursts
< system.physmem.perBankRdBursts::3 20052 # Per bank write bursts
< system.physmem.perBankRdBursts::4 19480 # Per bank write bursts
< system.physmem.perBankRdBursts::5 20770 # Per bank write bursts
< system.physmem.perBankRdBursts::6 19386 # Per bank write bursts
< system.physmem.perBankRdBursts::7 19760 # Per bank write bursts
< system.physmem.perBankRdBursts::8 19321 # Per bank write bursts
< system.physmem.perBankRdBursts::9 19768 # Per bank write bursts
< system.physmem.perBankRdBursts::10 19303 # Per bank write bursts
< system.physmem.perBankRdBursts::11 19444 # Per bank write bursts
< system.physmem.perBankRdBursts::12 19433 # Per bank write bursts
< system.physmem.perBankRdBursts::13 20871 # Per bank write bursts
< system.physmem.perBankRdBursts::14 19269 # Per bank write bursts
< system.physmem.perBankRdBursts::15 19527 # Per bank write bursts
< system.physmem.perBankWrBursts::0 4288 # Per bank write bursts
< system.physmem.perBankWrBursts::1 4110 # Per bank write bursts
< system.physmem.perBankWrBursts::2 4140 # Per bank write bursts
< system.physmem.perBankWrBursts::3 4154 # Per bank write bursts
< system.physmem.perBankWrBursts::4 4242 # Per bank write bursts
< system.physmem.perBankWrBursts::5 4232 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 19913 # Per bank write bursts
> system.physmem.perBankRdBursts::1 19609 # Per bank write bursts
> system.physmem.perBankRdBursts::2 657177 # Per bank write bursts
> system.physmem.perBankRdBursts::3 20974 # Per bank write bursts
> system.physmem.perBankRdBursts::4 19738 # Per bank write bursts
> system.physmem.perBankRdBursts::5 20841 # Per bank write bursts
> system.physmem.perBankRdBursts::6 19544 # Per bank write bursts
> system.physmem.perBankRdBursts::7 20056 # Per bank write bursts
> system.physmem.perBankRdBursts::8 19527 # Per bank write bursts
> system.physmem.perBankRdBursts::9 20071 # Per bank write bursts
> system.physmem.perBankRdBursts::10 19467 # Per bank write bursts
> system.physmem.perBankRdBursts::11 19786 # Per bank write bursts
> system.physmem.perBankRdBursts::12 19618 # Per bank write bursts
> system.physmem.perBankRdBursts::13 21115 # Per bank write bursts
> system.physmem.perBankRdBursts::14 19501 # Per bank write bursts
> system.physmem.perBankRdBursts::15 19801 # Per bank write bursts
> system.physmem.perBankWrBursts::0 4241 # Per bank write bursts
> system.physmem.perBankWrBursts::1 4104 # Per bank write bursts
> system.physmem.perBankWrBursts::2 4141 # Per bank write bursts
> system.physmem.perBankWrBursts::3 4151 # Per bank write bursts
> system.physmem.perBankWrBursts::4 4245 # Per bank write bursts
> system.physmem.perBankWrBursts::5 4233 # Per bank write bursts
80c80
< system.physmem.perBankWrBursts::8 4095 # Per bank write bursts
---
> system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
82c82
< system.physmem.perBankWrBursts::10 4095 # Per bank write bursts
---
> system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
85c85
< system.physmem.perBankWrBursts::13 4095 # Per bank write bursts
---
> system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
87c87
< system.physmem.perBankWrBursts::15 4146 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 4151 # Per bank write bursts
90c90
< system.physmem.totGap 326731313500 # Total gap between requests
---
> system.physmem.totGap 327895627500 # Total gap between requests
97c97
< system.physmem.readPktSize::6 953240 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 957029 # Read request sizes (log2)
104,118c104,118
< system.physmem.writePktSize::6 66334 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 66314 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 765529 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 120932 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 14410 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 6427 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 7705 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 8957 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 9890 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 6812 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 3724 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 2470 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1588 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1057 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 621 # What read queue length does an incoming req see
152,193c152,193
< system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 852 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 1419 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 2097 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 2585 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 3077 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 3558 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 4078 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4529 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5085 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5480 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5966 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6331 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5957 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4447 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4057 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 98 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 96 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 82 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 68 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 45 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 38 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 25 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 2 # What write queue length does an incoming req see
201,252c201,258
< system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads
< system.physmem.totQLat 12733277648 # Total ticks spent queuing
< system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 194181 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 337.148207 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 191.280987 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 364.158297 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 64676 33.31% 33.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 60636 31.23% 64.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 15729 8.10% 72.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3217 1.66% 74.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3574 1.84% 76.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2317 1.19% 77.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2364 1.22% 78.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 21831 11.24% 89.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 19837 10.22% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 194181 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 3990 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 177.226065 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 34.842577 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 1813.556545 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-4095 3969 99.47% 99.47% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.70% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::8192-12287 4 0.10% 99.80% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::12288-16383 2 0.05% 99.85% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.87% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.90% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::28672-32767 2 0.05% 99.95% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::86016-90111 1 0.03% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 3990 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 3990 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.593985 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.513577 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.886226 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3332 83.51% 83.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 5 0.13% 83.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 452 11.33% 94.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 50 1.25% 96.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 19 0.48% 96.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 17 0.43% 97.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 10 0.25% 97.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 19 0.48% 97.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 12 0.30% 98.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 15 0.38% 98.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 16 0.40% 98.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 15 0.38% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28 9 0.23% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::29 5 0.13% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::30 4 0.10% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::31 3 0.08% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32 1 0.03% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::33 1 0.03% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::34 3 0.08% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::35 1 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::37 1 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 3990 # Writes before turning the bus around for reads
> system.physmem.totQLat 12587538724 # Total ticks spent queuing
> system.physmem.totMemAccLat 30526376224 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 4783690000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 13156.72 # Average queueing delay per DRAM burst
254,258c260,264
< system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 31906.72 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 186.74 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 12.92 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 186.80 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 12.94 # Average system write bandwidth in MiByte/s
264,281c270,287
< system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing
< system.physmem.readRowHits 805882 # Number of row buffer hits during reads
< system.physmem.writeRowHits 26140 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes
< system.physmem.avgGap 320458.66 # Average gap between requests
< system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ)
< system.physmem_0.averagePower 771.975754 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states
< system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states
---
> system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing
> system.physmem.readRowHits 805843 # Number of row buffer hits during reads
> system.physmem.writeRowHits 22921 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 84.23 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 34.60 # Row buffer hit rate for writes
> system.physmem.avgGap 320416.15 # Average gap between requests
> system.physmem.pageHitRate 81.01 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 934317720 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 509796375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 6223237800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 216334800 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 220944760020 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 2925699000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 253170624435 # Total energy per rank (pJ)
> system.physmem_0.averagePower 772.109253 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 3595093339 # Time in different power states
> system.physmem_0.memoryStateTime::REF 10949120000 # Time in different power states
283c289
< system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 313351421161 # Time in different power states
285,295c291,301
< system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ)
< system.physmem_1.averagePower 704.579541 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states
< system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states
---
> system.physmem_1.actEnergy 533690640 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 291200250 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1239209400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 88116969465 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 119441319000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 231251573475 # Total energy per rank (pJ)
> system.physmem_1.averagePower 705.261391 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 198129163855 # Time in different power states
> system.physmem_1.memoryStateTime::REF 10949120000 # Time in different power states
297c303
< system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 118816573145 # Time in different power states
299,304c305,310
< system.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 174663372 # Number of BP lookups
< system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits
---
> system.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 174659739 # Number of BP lookups
> system.cpu.branchPred.condPredicted 119113225 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 4015668 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 96720974 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 67755362 # Number of BTB hits
306,307c312,313
< system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 70.052398 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 18785155 # Number of times the RAS was used to get a target.
309,312c315,318
< system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectLookups 16716286 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 16701799 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 14487 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 1279501 # Number of mispredicted indirect branches.
314c320
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
344c350
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
374c380
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
404c410
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
435,436c441,442
< system.cpu.pwrStateResidencyTicks::ON 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 653462649 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 655791277 # number of cpu cycles simulated
439,445c445,451
< system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.icacheStallCycles 34353189 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 824276690 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 174659739 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 103242316 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 616975428 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 2182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
447,452c453,458
< system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 3170 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 247740649 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 12515 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 655368010 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.551156 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.253828 # Number of instructions fetched each cycle (Total)
454,457c460,463
< system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 193301276 29.50% 29.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 148337850 22.63% 52.13% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 72946568 11.13% 63.26% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 240782316 36.74% 100.00% # Number of instructions fetched each cycle (Total)
461,488c467,494
< system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 4317999600 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 655368010 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.266334 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.256919 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 75112130 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 236493276 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 277761287 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 61980307 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 4021010 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 20809608 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 13112 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 924575224 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 11804312 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 4021010 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 118055519 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 135785787 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 212608 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 294557237 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 102735849 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 906541412 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 6891100 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 27959034 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 2218150 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 49337765 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 468731 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 980926815 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 4318009248 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1001835221 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 34457086 # Number of floating rename lookups
490,507c496,513
< system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 244402361 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 106148585 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 6844 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 6835 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 138814111 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 271882035 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 160585921 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 6159068 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 12159693 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 899827224 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 12580 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 860029296 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 9216848 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 111114846 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 244387313 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 655368010 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.312285 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.094624 # Number of insts issued each cycle
509,513c515,519
< system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 192710599 29.40% 29.40% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 182406257 27.83% 57.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 175554116 26.79% 84.02% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 92275656 14.08% 98.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 12419071 1.89% 100.00% # Number of insts issued each cycle
521c527
< system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 655368010 # Number of insts issued each cycle
523c529
< system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 66605310 24.62% 24.62% # attempts to use FU when none available
552,553c558,559
< system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 134121363 49.58% 74.45% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 69112589 25.55% 100.00% # attempts to use FU when none available
557,558c563,564
< system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 413090005 48.03% 48.03% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5187656 0.60% 48.64% # Type of FU issued
580c586
< system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCvt 2550150 0.30% 49.38% # Type of FU issued
582c588
< system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 11478194 1.33% 50.71% # Type of FU issued
586,587c592,593
< system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 266665504 31.01% 81.72% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 157232585 18.28% 100.00% # Type of FU issued
590,602c596,608
< system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued
< system.cpu.iq.rate 1.316105 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 860029296 # Type of FU issued
> system.cpu.iq.rate 1.311438 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 270494293 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.314518 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 2597595667 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 980331886 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 820082893 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 57542076 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 24878673 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 1098503163 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 32020426 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 13986768 # Number of loads that had data forwarded from stores
604c610
< system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 19641097 # Number of loads squashed
606,607c612,613
< system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.memOrderViolation 18820 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 31605425 # Number of stores squashed
611c617
< system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 17201 # Number of times an access to memory failed due to the cache being blocked
613,616c619,622
< system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 4021010 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 10590461 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 6281 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 899849934 # Number of instructions dispatched to IQ
618,629c624,635
< system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 271882035 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 160585921 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 6840 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 959 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 3423 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 18820 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 3295129 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3290187 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 6585316 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 850173752 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 263373804 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 9855544 # Number of squashed instructions skipped in execute
631,642c637,648
< system.cpu.iew.exec_nop 10252 # number of nop insts executed
< system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed
< system.cpu.iew.exec_branches 143379422 # Number of branches executed
< system.cpu.iew.exec_stores 152688943 # Number of stores executed
< system.cpu.iew.exec_rate 1.301023 # Inst execution rate
< system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 487338276 # num instructions producing a value
< system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 10130 # number of nop insts executed
> system.cpu.iew.exec_refs 416063188 # number of memory reference insts executed
> system.cpu.iew.exec_branches 143381327 # Number of branches executed
> system.cpu.iew.exec_stores 152689384 # Number of stores executed
> system.cpu.iew.exec_rate 1.296409 # Inst execution rate
> system.cpu.iew.wb_sent 846297655 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 844961566 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 487343298 # num instructions producing a value
> system.cpu.iew.wb_consumers 808106626 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.288461 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.603068 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 103169122 # The number of squashed insts skipped by commit
644,647c650,653
< system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 4002654 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 640787345 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.230876 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.070419 # Number of insts commited each cycle
649,657c655,663
< system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 350447626 54.69% 54.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 137241088 21.42% 76.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 51341072 8.01% 84.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 28220230 4.40% 88.52% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 14380949 2.24% 90.77% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 14774505 2.31% 93.07% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 7871971 1.23% 94.30% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 6561231 1.02% 95.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 29948673 4.67% 100.00% # Number of insts commited each cycle
661c667
< system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 640787345 # Number of insts commited each cycle
707,711c713,717
< system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 1500478116 # The number of ROB reads
< system.cpu.rob.rob_writes 1798380886 # The number of ROB writes
< system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 29948673 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 1502729113 # The number of ROB reads
> system.cpu.rob.rob_writes 1798382436 # The number of ROB writes
> system.cpu.timesIdled 10485 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 423267 # Total number of cycles that the CPU has spent unscheduled due to idling
714,724c720,730
< system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 868460109 # number of integer regfile reads
< system.cpu.int_regfile_writes 500697086 # number of integer regfile writes
< system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads
< system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes
< system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads
< system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes
< system.cpu.misc_regfile_reads 606830951 # number of misc regfile reads
---
> system.cpu.cpi 1.023635 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.023635 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.976910 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.976910 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 868461212 # number of integer regfile reads
> system.cpu.int_regfile_writes 500699124 # number of integer regfile writes
> system.cpu.fp_regfile_reads 30616064 # number of floating regfile reads
> system.cpu.fp_regfile_writes 22959493 # number of floating regfile writes
> system.cpu.cc_regfile_reads 3322386264 # number of cc regfile reads
> system.cpu.cc_regfile_writes 369207629 # number of cc regfile writes
> system.cpu.misc_regfile_reads 606832888 # number of misc regfile reads
726,735c732,741
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 2756452 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 2756458 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.912011 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 371050492 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2756970 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 134.586336 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 274880000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.912011 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999828 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999828 # Average percentage of cache occupancy
738,739c744,745
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id
742,748c748,754
< system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 751746846 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 751746846 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 243126867 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 243126867 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 127907624 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 127907624 # number of WriteReq hits
755,762c761,768
< system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits
< system.cpu.dcache.overall_hits::total 371035352 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 371034491 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 371034491 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 371037648 # number of overall hits
> system.cpu.dcache.overall_hits::total 371037648 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2401310 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2401310 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1043853 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1043853 # number of WriteReq misses
767,782c773,788
< system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses
< system.cpu.dcache.overall_misses::total 3447085 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 3445163 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3445163 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3445810 # number of overall misses
> system.cpu.dcache.overall_misses::total 3445810 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 69278020000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 69278020000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9882341350 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9882341350 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 168500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 168500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 79160361350 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 79160361350 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 79160361350 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 79160361350 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 245528177 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 245528177 # number of ReadReq accesses(hits+misses)
791,798c797,804
< system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 374479654 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 374479654 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 374483458 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 374483458 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses
803,816c809,822
< system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28850.094324 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 28850.094324 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9467.177227 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 9467.177227 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56166.666667 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56166.666667 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 22977.247042 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 22977.247042 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 22972.932736 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 22972.932736 # average overall miss latency
818c824
< system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 322646 # number of cycles access was blocked
820c826
< system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_targets 4628 # number of cycles access was blocked
822,828c828,834
< system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks
< system.cpu.dcache.writebacks::total 2756452 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 69.716076 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 2756458 # number of writebacks
> system.cpu.dcache.writebacks::total 2756458 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365828 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 365828 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322833 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 322833 # number of WriteReq MSHR hits
831,838c837,844
< system.cpu.dcache.demand_mshr_hits::cpu.data 689931 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 689931 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 689931 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 689931 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035475 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 2035475 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721032 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 721032 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 688661 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 688661 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 688661 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 688661 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035482 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 2035482 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721020 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 721020 # number of WriteReq MSHR misses
841,854c847,860
< system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63009195000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 63009195000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5955069850 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5955069850 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5660000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5660000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 68964264850 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 68964264850 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 68969924850 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 68969924850 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 2756502 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2756502 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2757144 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2757144 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64102936000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 64102936000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5940509850 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5940509850 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5561000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5561000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 70043445850 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 70043445850 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 70049006850 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 70049006850 # number of overall MSHR miss cycles
865,884c871,890
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1979880 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31492.755033 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31492.755033 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8239.036157 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8239.036157 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8661.993769 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8661.993769 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25410.264839 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25410.264839 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25406.365010 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 25406.365010 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1979522 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.874726 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 245757404 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 124.117895 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 264413500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.874726 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.997802 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy
887c893
< system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
889c895
< system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id
891,932c897,938
< system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits
< system.cpu.icache.overall_hits::total 245759426 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1983591 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1983591 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1983591 # number of overall misses
< system.cpu.icache.overall_misses::total 1983591 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 16128682925 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 16128682925 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 16128682925 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 16128682925 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 16128682925 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 16128682925 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 247743017 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 247743017 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 247743017 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 247743017 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 247743017 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 247743017 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008007 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.008007 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.008007 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.008007 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.008007 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.008007 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8131.052684 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 8131.052684 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 8131.052684 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 497461440 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 497461440 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 245757408 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 245757408 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 245757408 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 245757408 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 245757408 # number of overall hits
> system.cpu.icache.overall_hits::total 245757408 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1983209 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1983209 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1983209 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1983209 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1983209 # number of overall misses
> system.cpu.icache.overall_misses::total 1983209 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 16177953926 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 16177953926 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 16177953926 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 16177953926 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 16177953926 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 16177953926 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 247740617 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 247740617 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 247740617 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 247740617 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 247740617 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 247740617 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8157.462943 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 8157.462943 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 8157.462943 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 8157.462943 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 75964 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 122 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 2856 # number of cycles access was blocked
934,971c940,977
< system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks
< system.cpu.icache.writebacks::total 1979880 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980577 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1980577 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1980577 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1980577 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1980577 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1980577 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15098139938 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 15098139938 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15098139938 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 15098139938 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15098139938 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 15098139938 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007994 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.007994 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 26.598039 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 24.400000 # average number of cycles each access was blocked
> system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks
> system.cpu.icache.writebacks::total 1979522 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3001 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 3001 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 3001 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 3001 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 3001 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 3001 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980208 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1980208 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1980208 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1980208 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1980208 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1980208 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15149087440 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 15149087440 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15149087440 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 15149087440 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15149087440 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 15149087440 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7650.250600 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7650.250600 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7650.250600 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 7650.250600 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7650.250600 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 7650.250600 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 1350340 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 1355050 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 4121 # number of redundant prefetches already in prefetch queue
974,1062c980,1068
< system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 301370 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 317734 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 22.730041 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 44242160500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 9843.702780 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6506.729901 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.600812 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397139 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.997951 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 6334 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 10030 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1704 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4420 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 3356496 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 718501 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 718501 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976843 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1976843 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1287256 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 1287256 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 1976843 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 2005757 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3982600 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 1976843 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 2005757 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3982600 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 185 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 185 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 2346 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 2346 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3550 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 3550 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 748861 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 748861 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 3550 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 751207 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 754757 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3550 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 751207 # number of overall misses
< system.cpu.l2cache.overall_misses::total 754757 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195074000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 195074000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261372000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 261372000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 51585571000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 51585571000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 261372000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 51780645000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 52042017000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 261372000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 51780645000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 52042017000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 736314 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 736314 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 3356496 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 3356496 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 185 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 185 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980393 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1980393 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036117 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 2036117 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1980393 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 2756964 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 4737357 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1980393 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 2756964 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 4737357 # number of overall (read+write) accesses
---
> system.cpu.l2cache.prefetcher.pfSpanPage 4790102 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 297234 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 16098.063865 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3815891 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 313429 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 12.174658 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 15670.505298 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 427.558566 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.956452 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.026096 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.982548 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 418 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15777 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1577 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3842 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9849 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025513 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962952 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 145585225 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 145585225 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 735545 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 735545 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 3357840 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 3357840 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 718742 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 718742 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975871 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1975871 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286733 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 1286733 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 1975871 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 2005475 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3981346 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 1975871 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 2005475 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3981346 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 174 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 174 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 2104 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 2104 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4164 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 4164 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749391 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 749391 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 4164 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 751495 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 755659 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 4164 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 751495 # number of overall misses
> system.cpu.l2cache.overall_misses::total 755659 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 179065000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 179065000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 319741500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 319741500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 52681851500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 52681851500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 319741500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 52860916500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 53180658000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 319741500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 52860916500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 53180658000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 735545 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 735545 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 3357840 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 3357840 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 174 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 174 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980035 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1980035 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036124 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 2036124 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1980035 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2756970 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 4737005 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1980035 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2756970 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 4737005 # number of overall (read+write) accesses
1065,1088c1071,1094
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003255 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.003255 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.001793 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.001793 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.367789 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.367789 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.001793 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.272476 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.159320 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.001793 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.272476 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.159320 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83151.747656 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83151.747656 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73625.915493 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73625.915493 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68885.375257 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68885.375257 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68952.016344 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002919 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.002919 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002103 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002103 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368048 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368048 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002103 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.272580 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.159523 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002103 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.272580 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.159523 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85106.939163 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85106.939163 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76787.103746 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76787.103746 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70299.551903 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70299.551903 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76787.103746 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70376.529625 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76787.103746 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70376.529625 # average overall miss latency
1095,1099c1101,1105
< system.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference
< system.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks
< system.cpu.l2cache.writebacks::total 66334 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 963 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 963 # number of ReadExReq MSHR hits
---
> system.cpu.l2cache.unused_prefetches 3678 # number of HardPF blocks evicted w/o reference
> system.cpu.l2cache.writebacks::writebacks 66314 # number of writebacks
> system.cpu.l2cache.writebacks::total 66314 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 742 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 742 # number of ReadExReq MSHR hits
1102,1103c1108,1109
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 903 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 903 # number of ReadSharedReq MSHR hits
---
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 703 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 703 # number of ReadSharedReq MSHR hits
1105,1106c1111,1112
< system.cpu.l2cache.demand_mshr_hits::cpu.data 1866 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 1867 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 1445 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 1446 # number of demand (read+write) MSHR hits
1108,1143c1114,1149
< system.cpu.l2cache.overall_mshr_hits::cpu.data 1866 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 1867 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200438 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 200438 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 185 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 185 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1383 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 1383 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3549 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3549 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 747958 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 747958 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3549 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 749341 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 752890 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3549 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 749341 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200438 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 953328 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16667426112 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2605000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2605000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 137246500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 137246500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240029500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240029500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 47054888500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 47054888500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240029500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47192135000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 47432164500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240029500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47192135000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 64099590612 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 1445 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 1446 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202914 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 202914 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 174 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 174 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1362 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 1362 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4163 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4163 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748688 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748688 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 4163 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 750050 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 754213 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 4163 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 750050 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202914 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 957127 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16536801285 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16536801285 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2630000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2630000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133214500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133214500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 294714000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 294714000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 48154340500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 48154340500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 294714000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 48287555000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 48582269000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294714000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48287555000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16536801285 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 65119070285 # number of overall MSHR miss cycles
1148,1158c1154,1164
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002102 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367703 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367703 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.159217 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for overall accesses
1160,1206c1166,1212
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 1296784 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 4257152 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.202053 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 81496.600949 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15114.942529 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15114.942529 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97808.002937 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97808.002937 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70793.658419 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70793.658419 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64318.301482 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64318.301482 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64414.520832 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68035.976715 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 9473332 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736180 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 642769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 4016330 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 801859 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 4000435 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 230920 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 258553 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980208 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036124 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939763 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270746 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 14210509 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859392 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 606270912 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 555960 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 4255168 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 5293139 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.121491 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.326697 # Request fanout histogram
1208,1210c1214,1216
< system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 4650072 87.85% 87.85% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 643066 12.15% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
1214,1215c1220,1221
< system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 5293139 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 9472646000 # Layer occupancy (ticks)
1217c1223
< system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2970310996 # Layer occupancy (ticks)
1219c1225
< system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 4135552978 # Layer occupancy (ticks)
1221,1232c1227,1244
< system.membus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 951856 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution
< system.membus.trans_dist::CleanEvict 227102 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 185 # Transaction distribution
< system.membus.trans_dist::ReadExReq 1383 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1383 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 1254437 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 940010 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 955666 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 66314 # Transaction distribution
> system.membus.trans_dist::CleanEvict 230920 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 174 # Transaction distribution
> system.membus.trans_dist::ReadExReq 1362 # Transaction distribution
> system.membus.trans_dist::ReadExResp 1362 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 955667 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211465 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 2211465 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65493888 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 65493888 # Cumulative packet size per connected master and slave (bytes)
1235c1247
< system.membus.snoop_fanout::samples 1246861 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 957203 # Request fanout histogram
1239c1251
< system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 957203 100.00% 100.00% # Request fanout histogram
1244,1245c1256,1257
< system.membus.snoop_fanout::total 1246861 # Request fanout histogram
< system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 957203 # Request fanout histogram
> system.membus.reqLayer0.occupancy 1755655982 # Layer occupancy (ticks)
1247c1259
< system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 5035261795 # Layer occupancy (ticks)