4,5c4,5
< sim_ticks 409388341000 # Number of ticks simulated
< final_tick 409388341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 409388416000 # Number of ticks simulated
> final_tick 409388416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 75979 # Simulator instruction rate (inst/s)
< host_op_rate 93540 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 48552243 # Simulator tick rate (ticks/s)
< host_mem_usage 312124 # Number of bytes of host memory used
< host_seconds 8431.91 # Real time elapsed on the host
---
> host_inst_rate 93306 # Simulator instruction rate (inst/s)
> host_op_rate 114872 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 59624294 # Simulator tick rate (ticks/s)
> host_mem_usage 320320 # Number of bytes of host memory used
> host_seconds 6866.13 # Real time elapsed on the host
16c16
< system.physmem.bytes_read::cpu.inst 226496 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 226560 # Number of bytes read from this memory
19,21c19,21
< system.physmem.bytes_read::total 20189120 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::total 20189184 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 226560 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 226560 # Number of instructions bytes read from this memory
24c24
< system.physmem.num_reads::cpu.inst 3539 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 3540 # Number of read requests responded to by this memory
27c27
< system.physmem.num_reads::total 315455 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::total 315456 # Number of read requests responded to by this memory
30,43c30,43
< system.physmem.bw_read::cpu.inst 553255 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 17157303 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 31604769 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 49315327 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 553255 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 553255 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 10371297 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 10371297 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 10371297 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 553255 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 17157303 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 31604769 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 59686624 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 315455 # Number of read requests accepted
---
> system.physmem.bw_read::cpu.inst 553411 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 17157300 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 31604763 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 49315475 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 553411 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 553411 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 10371295 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 10371295 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 10371295 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 553411 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 17157300 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 31604763 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 59686769 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 315456 # Number of read requests accepted
45c45
< system.physmem.readBursts 315455 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 315456 # Number of DRAM read bursts, including those serviced by the write queue
47c47
< system.physmem.bytesReadDRAM 20169536 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 20169600 # Total number of bytes read from DRAM
50c50
< system.physmem.bytesReadSys 20189120 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 20189184 # Total read bytes from the system interface side
54c54
< system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write
70c70
< system.physmem.perBankRdBursts::15 19977 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 19978 # Per bank write bursts
89c89
< system.physmem.totGap 409388286500 # Total gap between requests
---
> system.physmem.totGap 409388361500 # Total gap between requests
96c96
< system.physmem.readPktSize::6 315455 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 315456 # Read request sizes (log2)
104c104
< system.physmem.rdQLenPdf::0 122393 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 122394 # What read queue length does an incoming req see
200,203c200,203
< system.physmem.bytesPerActivate::samples 136711 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 178.525503 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 128.653130 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 198.190580 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 136710 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 178.527277 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 128.653997 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 198.191580 # Bytes accessed per row activation
205,206c205,206
< system.physmem.bytesPerActivate::128-255 57416 42.00% 81.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 14736 10.78% 92.37% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::128-255 57414 42.00% 81.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 14737 10.78% 92.37% # Bytes accessed per row activation
213c213
< system.physmem.bytesPerActivate::total 136711 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::total 136710 # Bytes accessed per row activation
251,254c251,254
< system.physmem.totQLat 9474891317 # Total ticks spent queuing
< system.physmem.totMemAccLat 15383935067 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1575745000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 30064.80 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 9474850817 # Total ticks spent queuing
> system.physmem.totMemAccLat 15383913317 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1575750000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 30064.58 # Average queueing delay per DRAM burst
256c256
< system.physmem.avgMemAccLat 48814.80 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 48814.58 # Average memory access latency per DRAM burst
267c267
< system.physmem.readRowHits 218193 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 218195 # Number of row buffer hits during reads
269c269
< system.physmem.readRowHitRate 69.23 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 69.24 # Row buffer hit rate for reads
271c271
< system.physmem.avgGap 1072266.90 # Average gap between requests
---
> system.physmem.avgGap 1072264.29 # Average gap between requests
282c282
< system.physmem_0.memoryStateTime::IDLE 267357168520 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 267357262270 # Time in different power states
287,288c287,288
< system.physmem_1.actEnergy 514715040 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 280846500 # Energy for precharge commands per rank (pJ)
---
> system.physmem_1.actEnergy 514722600 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 280850625 # Energy for precharge commands per rank (pJ)
294,296c294,296
< system.physmem_1.totalEnergy 286420773645 # Total energy per rank (pJ)
< system.physmem_1.averagePower 699.635490 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 267598080337 # Time in different power states
---
> system.physmem_1.totalEnergy 286420785330 # Total energy per rank (pJ)
> system.physmem_1.averagePower 699.635519 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 267597865087 # Time in different power states
301,302c301,302
< system.cpu.branchPred.lookups 233960254 # Number of BP lookups
< system.cpu.branchPred.condPredicted 161822373 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 233960267 # Number of BP lookups
> system.cpu.branchPred.condPredicted 161822378 # Number of conditional branches predicted
304,305c304,305
< system.cpu.branchPred.BTBLookups 121575796 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 108259792 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 121575807 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 108259798 # Number of BTB hits
307c307
< system.cpu.branchPred.BTBHitPct 89.047159 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 89.047156 # BTB Hit Percentage
428c428
< system.cpu.numCycles 818776683 # number of cpu cycles simulated
---
> system.cpu.numCycles 818776833 # number of cpu cycles simulated
431,435c431,435
< system.cpu.fetch.icacheStallCycles 84080283 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 1200690611 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 233960254 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 133296622 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 718833631 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.icacheStallCycles 84080281 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 1200690651 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 233960267 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 133296628 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 718834157 # Number of cycles fetch has run and was not squashing or blocked
437c437
< system.cpu.fetch.MiscStallCycles 2156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.MiscStallCycles 2157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
439,443c439,443
< system.cpu.fetch.IcacheWaitRetryStallCycles 3279 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 370702181 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 652815 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 818451212 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.833527 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 3294 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 370702196 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 652814 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 818451752 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.833525 # Number of instructions fetched each cycle (Total)
446,449c446,449
< system.cpu.fetch.rateDist::0 136785734 16.71% 16.71% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 223134622 27.26% 43.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 98075130 11.98% 55.96% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 360455726 44.04% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 136786252 16.71% 16.71% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 223134631 27.26% 43.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 98075133 11.98% 55.96% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 360455736 44.04% 100.00% # Number of instructions fetched each cycle (Total)
453c453
< system.cpu.fetch.rateDist::total 818451212 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 818451752 # Number of instructions fetched each cycle (Total)
455,459c455,459
< system.cpu.fetch.rate 1.466445 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 119992571 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 159648210 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 484662538 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 38629741 # Number of cycles decode is unblocking
---
> system.cpu.fetch.rate 1.466444 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 119992574 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 159648734 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 484662553 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 38629739 # Number of cycles decode is unblocking
461c461
< system.cpu.decode.BranchResolved 25181026 # Number of times decode resolved a branch
---
> system.cpu.decode.BranchResolved 25181029 # Number of times decode resolved a branch
463,464c463,464
< system.cpu.decode.DecodedInsts 1248127712 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 39967189 # Number of squashed instructions handled by decode
---
> system.cpu.decode.DecodedInsts 1248127732 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 39967182 # Number of squashed instructions handled by decode
466,467c466,467
< system.cpu.rename.IdleCycles 177000170 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 78888622 # Number of cycles rename is blocking
---
> system.cpu.rename.IdleCycles 177000175 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 78889127 # Number of cycles rename is blocking
469,472c469,472
< system.cpu.rename.RunCycles 464955823 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 81877741 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1190635480 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 25549977 # Number of squashed instructions processed by rename
---
> system.cpu.rename.RunCycles 464955834 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 81877760 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1190635501 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 25549976 # Number of squashed instructions processed by rename
476,479c476,479
< system.cpu.rename.SQFullEvents 1694220 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 1225376851 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 5812387634 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1358166964 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 1694237 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 1225376861 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 5812387733 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1358166990 # Number of integer rename lookups
482c482
< system.cpu.rename.UndoneMaps 350598621 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 350598631 # Number of HB maps that are undone due to squashing
485,487c485,487
< system.cpu.rename.skidInsts 108139964 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 366113107 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 236095924 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 108139973 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 366113111 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 236095933 # Number of stores inserted to the mem dependence unit.
490c490
< system.cpu.iq.iqInstsAdded 1168545112 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 1168545131 # Number of instructions added to the IQ (excludes non-spec)
492,495c492,495
< system.cpu.iq.iqInstsIssued 1017136895 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 18518107 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 379832511 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 1032101117 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 1017136914 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 18518110 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 379832530 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 1032101126 # Number of squashed operands that are examined and possibly removed from graph
497,498c497,498
< system.cpu.iq.issued_per_cycle::samples 818451212 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.242758 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 818451752 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.242757 # Number of insts issued each cycle
501,505c501,505
< system.cpu.iq.issued_per_cycle::0 260801504 31.87% 31.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 227738074 27.83% 59.69% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 216482418 26.45% 86.14% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 97282888 11.89% 98.03% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 16146319 1.97% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 260802028 31.87% 31.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 227738086 27.83% 59.69% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 216482422 26.45% 86.14% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 97282889 11.89% 98.03% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 16146318 1.97% 100.00% # Number of insts issued each cycle
513c513
< system.cpu.iq.issued_per_cycle::total 818451212 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 818451752 # Number of insts issued each cycle
544,545c544,545
< system.cpu.iq.fu_full::MemRead 155540663 46.10% 65.42% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 116678902 34.58% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 155540667 46.10% 65.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 116678907 34.58% 100.00% # attempts to use FU when none available
549c549
< system.cpu.iq.FU_type_0::IntAlu 456370981 44.87% 44.87% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 456370990 44.87% 44.87% # Type of FU issued
578,579c578,579
< system.cpu.iq.FU_type_0::MemRead 322128329 31.67% 78.80% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 215587412 21.20% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 322128333 31.67% 78.80% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 215587418 21.20% 100.00% # Type of FU issued
582c582
< system.cpu.iq.FU_type_0::total 1017136895 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 1017136914 # Type of FU issued
584c584
< system.cpu.iq.fu_busy_cnt 337386313 # FU busy when requested
---
> system.cpu.iq.fu_busy_cnt 337386322 # FU busy when requested
586,588c586,588
< system.cpu.iq.int_inst_queue_reads 3146752380 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 1504842501 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 934271178 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 3146752970 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 1504842539 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 934271199 # Number of integer instruction queue wakeup accesses
592c592
< system.cpu.iq.int_alu_accesses 1320712858 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 1320712886 # Number of integer alu accesses
596c596
< system.cpu.iew.lsq.thread0.squashedLoads 113872169 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 113872173 # Number of loads squashed
599c599
< system.cpu.iew.lsq.thread0.squashedStores 107115428 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 107115437 # Number of stores squashed
606c606
< system.cpu.iew.iewBlockCycles 35325435 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 35325436 # Number of cycles IEW is blocking
608c608
< system.cpu.iew.iewDispatchedInsts 1168563023 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 1168563042 # Number of instructions dispatched to IQ
610,611c610,611
< system.cpu.iew.iewDispLoadInsts 366113107 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 236095924 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 366113111 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 236095933 # Number of dispatched store instructions
619,621c619,621
< system.cpu.iew.iewExecutedInsts 974751162 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 303297617 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 42385733 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 974751184 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 303297622 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 42385730 # Number of squashed instructions skipped in execute
624,626c624,626
< system.cpu.iew.exec_refs 497765227 # number of memory reference insts executed
< system.cpu.iew.exec_branches 150613464 # Number of branches executed
< system.cpu.iew.exec_stores 194467610 # Number of stores executed
---
> system.cpu.iew.exec_refs 497765238 # number of memory reference insts executed
> system.cpu.iew.exec_branches 150613469 # Number of branches executed
> system.cpu.iew.exec_stores 194467616 # Number of stores executed
628,631c628,631
< system.cpu.iew.wb_sent 963723916 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 960423621 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 536680580 # num instructions producing a value
< system.cpu.iew.wb_consumers 893282190 # num instructions consuming a value
---
> system.cpu.iew.wb_sent 963723937 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 960423642 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 536680583 # num instructions producing a value
> system.cpu.iew.wb_consumers 893282195 # num instructions consuming a value
636c636
< system.cpu.commit.commitSquashedInsts 357407190 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 357407209 # The number of squashed insts skipped by commit
639,641c639,641
< system.cpu.commit.committed_per_cycle::samples 767630958 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.027486 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.786865 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 767631497 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.027485 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.786864 # Number of insts commited each cycle
643,644c643,644
< system.cpu.commit.committed_per_cycle::0 430922921 56.14% 56.14% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 172477665 22.47% 78.61% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 430923455 56.14% 56.14% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 172477669 22.47% 78.61% # Number of insts commited each cycle
646c646
< system.cpu.commit.committed_per_cycle::3 31624091 4.12% 92.31% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::3 31624094 4.12% 92.31% # Number of insts commited each cycle
648c648
< system.cpu.commit.committed_per_cycle::5 14250533 1.86% 95.28% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::5 14250532 1.86% 95.28% # Number of insts commited each cycle
651c651
< system.cpu.commit.committed_per_cycle::8 22360346 2.91% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::8 22360345 2.91% 100.00% # Number of insts commited each cycle
655c655
< system.cpu.commit.committed_per_cycle::total 767630958 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 767631497 # Number of insts commited each cycle
701,705c701,705
< system.cpu.commit.bw_lim_events 22360346 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 1891399121 # The number of ROB reads
< system.cpu.rob.rob_writes 2343098694 # The number of ROB writes
< system.cpu.timesIdled 647342 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 325471 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 22360345 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 1891399680 # The number of ROB reads
> system.cpu.rob.rob_writes 2343098733 # The number of ROB writes
> system.cpu.timesIdled 647345 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 325081 # Total number of cycles that the CPU has spent unscheduled due to idling
712,713c712,713
< system.cpu.int_regfile_reads 995806500 # number of integer regfile reads
< system.cpu.int_regfile_writes 567906149 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 995806519 # number of integer regfile reads
> system.cpu.int_regfile_writes 567906159 # number of integer regfile writes
716,718c716,718
< system.cpu.cc_regfile_reads 3794435390 # number of cc regfile reads
< system.cpu.cc_regfile_writes 384898944 # number of cc regfile writes
< system.cpu.misc_regfile_reads 715817585 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 3794435468 # number of cc regfile reads
> system.cpu.cc_regfile_writes 384898950 # number of cc regfile writes
> system.cpu.misc_regfile_reads 715817595 # number of misc regfile reads
722c722
< system.cpu.dcache.tags.total_refs 414226707 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 414226712 # Total number of references to valid blocks.
724c724
< system.cpu.dcache.tags.avg_refs 150.262019 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 150.262021 # Average number of references to valid blocks.
735,738c735,738
< system.cpu.dcache.tags.tag_accesses 839343974 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 839343974 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 286295255 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 286295255 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 839343984 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 839343984 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 286295259 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 286295259 # number of ReadReq hits
747,752c747,752
< system.cpu.dcache.demand_hits::cpu.data 414211960 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 414211960 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 414215134 # number of overall hits
< system.cpu.dcache.overall_hits::total 414215134 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 3031607 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 3031607 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 414211964 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 414211964 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 414215138 # number of overall hits
> system.cpu.dcache.overall_hits::total 414215138 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 3031608 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 3031608 # number of ReadReq misses
759,766c759,766
< system.cpu.dcache.demand_misses::cpu.data 4066379 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4066379 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4067026 # number of overall misses
< system.cpu.dcache.overall_misses::total 4067026 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 35304231919 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 35304231919 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981686625 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9981686625 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 4066380 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4066380 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4067027 # number of overall misses
> system.cpu.dcache.overall_misses::total 4067027 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 35305181420 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 35305181420 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981703626 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9981703626 # number of WriteReq miss cycles
769,774c769,774
< system.cpu.dcache.demand_miss_latency::cpu.data 45285918544 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 45285918544 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 45285918544 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 45285918544 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 289326862 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 289326862 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 45286885046 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 45286885046 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 45286885046 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 45286885046 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 289326867 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 289326867 # number of ReadReq accesses(hits+misses)
783,786c783,786
< system.cpu.dcache.demand_accesses::cpu.data 418278339 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 418278339 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 418282160 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 418282160 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 418278344 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 418278344 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 418282165 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 418282165 # number of overall (read+write) accesses
799,802c799,802
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.385407 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.385407 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.266641 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.266641 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.694767 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.694767 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.283071 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.283071 # average WriteReq miss latency
805,808c805,808
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.669392 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 11136.669392 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 11134.897722 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 11134.897722 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.904334 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 11136.904334 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 11135.132628 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 11135.132628 # average overall miss latency
819,820c819,820
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996398 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 996398 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996399 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 996399 # number of ReadReq MSHR hits
825,828c825,828
< system.cpu.dcache.demand_mshr_hits::cpu.data 1310305 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1310305 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1310305 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1310305 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 1310306 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1310306 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1310306 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1310306 # number of overall MSHR hits
839,842c839,842
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23117834450 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 23117834450 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596502782 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596502782 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23118028700 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 23118028700 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596519781 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596519781 # number of WriteReq MSHR miss cycles
845,848c845,848
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714337232 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 28714337232 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720107235 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 28720107235 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714548481 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 28714548481 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720318484 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28720318484 # number of overall MSHR miss cycles
859,862c859,862
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11358.948614 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11358.948614 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.593436 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.593436 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11359.044059 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11359.044059 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.617017 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.617017 # average WriteReq mshr miss latency
865,868c865,868
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.565406 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.565406 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.235920 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.235920 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.642054 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.642054 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.312551 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.312551 # average overall mshr miss latency
870c870
< system.cpu.icache.tags.replacements 5169973 # number of replacements
---
> system.cpu.icache.tags.replacements 5169974 # number of replacements
872,874c872,874
< system.cpu.icache.tags.total_refs 365527993 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 5170483 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 70.695135 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 365528009 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 5170484 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 70.695124 # Average number of references to valid blocks.
880c880
< system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
883c883
< system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id
885,910c885,910
< system.cpu.icache.tags.tag_accesses 746574800 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 746574800 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 365528016 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 365528016 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 365528016 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 365528016 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 365528016 # number of overall hits
< system.cpu.icache.overall_hits::total 365528016 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 5174133 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 5174133 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 5174133 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 5174133 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 5174133 # number of overall misses
< system.cpu.icache.overall_misses::total 5174133 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647669446 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 41647669446 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 41647669446 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 41647669446 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 41647669446 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 41647669446 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 370702149 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 370702149 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 370702149 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 370702149 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 370702149 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 370702149 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 746574831 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 746574831 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 365528032 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 365528032 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 365528032 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 365528032 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 365528032 # number of overall hits
> system.cpu.icache.overall_hits::total 365528032 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 5174132 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 5174132 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 5174132 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 5174132 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 5174132 # number of overall misses
> system.cpu.icache.overall_misses::total 5174132 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647443196 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 41647443196 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 41647443196 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 41647443196 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 41647443196 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 41647443196 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 370702164 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 370702164 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 370702164 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 370702164 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 370702164 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 370702164 # number of overall (read+write) accesses
917,923c917,923
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.207364 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 8049.207364 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.207364 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 8049.207364 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.207364 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 8049.207364 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 75182 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.165193 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 8049.165193 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 8049.165193 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 8049.165193 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 75254 # number of cycles access was blocked
927c927
< system.cpu.icache.avg_blocked_cycles::no_mshrs 24.019808 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 24.042812 # average number of cycles each access was blocked
931,948c931,948
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3630 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 3630 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 3630 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 3630 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 3630 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 3630 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170503 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 5170503 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 5170503 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 5170503 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 5170503 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 5170503 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431563436 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 36431563436 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431563436 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 36431563436 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431563436 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 36431563436 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3628 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 3628 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 3628 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 3628 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 3628 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 3628 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170504 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 5170504 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 5170504 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 5170504 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 5170504 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 5170504 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431387686 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 36431387686 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431387686 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 36431387686 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431387686 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 36431387686 # number of overall MSHR miss cycles
955,960c955,960
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.038545 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.038545 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.038545 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.038545 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.038545 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.038545 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.003192 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.003192 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency
968c968
< system.cpu.l2cache.tags.replacements 299164 # number of replacements
---
> system.cpu.l2cache.tags.replacements 299165 # number of replacements
971,972c971,972
< system.cpu.l2cache.tags.sampled_refs 315528 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.799086 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 315529 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 24.799007 # Average number of references to valid blocks.
974,977c974,977
< system.cpu.l2cache.tags.occ_blocks::writebacks 743.987058 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512594 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582471 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474196 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 743.986923 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512620 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582614 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474164 # Average occupied blocks per requestor
983,984c983,984
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 6518 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 9846 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 6520 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 9844 # Occupied blocks per task id
986,987c986,987
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 171 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1451 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1454 # Occupied blocks per task id
989c989
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
991,997c991,997
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2089 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7268 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.397827 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.600952 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 139642343 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 139642343 # Number of data accesses
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2085 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7271 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.397949 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.600830 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 139642360 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 139642360 # Number of data accesses
1003,1004d1002
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
1013c1011
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3553 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3554 # number of ReadReq misses
1015,1017c1013,1015
< system.cpu.l2cache.ReadReq_misses::total 113192 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 113193 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses
1020c1018
< system.cpu.l2cache.demand_misses::cpu.inst 3553 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 3554 # number of demand (read+write) misses
1022,1023c1020,1021
< system.cpu.l2cache.demand_misses::total 116050 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3553 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 116051 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3554 # number of overall misses
1025,1028c1023,1028
< system.cpu.l2cache.overall_misses::total 116050 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 261165964 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8561744931 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 8822910895 # number of ReadReq miss cycles
---
> system.cpu.l2cache.overall_misses::total 116051 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260989714 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8561938681 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 8822928395 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles
1031,1037c1031,1037
< system.cpu.l2cache.demand_miss_latency::cpu.inst 261165964 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8766968630 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 9028134594 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 261165964 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8766968630 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 9028134594 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170485 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 260989714 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8767162380 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 9028152094 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 260989714 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8767162380 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 9028152094 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170486 # number of ReadReq accesses(hits+misses)
1039c1039
< system.cpu.l2cache.ReadReq_accesses::total 7206335 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 7206336 # number of ReadReq accesses(hits+misses)
1046c1046
< system.cpu.l2cache.demand_accesses::cpu.inst 5170485 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 5170486 # number of demand (read+write) accesses
1048,1049c1048,1049
< system.cpu.l2cache.demand_accesses::total 7927181 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 5170485 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 7927182 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 5170486 # number of overall (read+write) accesses
1051c1051
< system.cpu.l2cache.overall_accesses::total 7927181 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 7927182 # number of overall (read+write) accesses
1055,1056c1055,1056
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1065,1067c1065,1069
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73505.759640 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78090.323069 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 77946.417547 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73435.485087 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.090232 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 77945.883535 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1236.789474 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1236.789474 # average UpgradeReq miss latency
1070,1075c1072,1077
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77795.214080 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77795.214080 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77794.694522 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77794.694522 # average overall miss latency
1097c1099
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3539 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3540 # number of ReadReq MSHR misses
1099c1101
< system.cpu.l2cache.ReadReq_mshr_misses::total 111891 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 111892 # number of ReadReq MSHR misses
1102,1103c1104,1105
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses
1106c1108
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3539 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3540 # number of demand (read+write) MSHR misses
1108,1109c1110,1111
< system.cpu.l2cache.demand_mshr_misses::total 113289 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3539 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 113290 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3540 # number of overall MSHR misses
1112,1115c1114,1117
< system.cpu.l2cache.overall_mshr_misses::total 315531 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230067036 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7609571000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7839638036 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::total 315532 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 229882786 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7609765250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7839648036 # number of ReadReq MSHR miss cycles
1118,1119c1120,1121
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 248018 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 248018 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 262019 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 262019 # number of UpgradeReq MSHR miss cycles
1122,1126c1124,1128
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230067036 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723581508 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 7953648544 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230067036 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723581508 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229882786 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723775758 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 7953658544 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229882786 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723775758 # number of overall MSHR miss cycles
1128,1129c1130,1131
< system.cpu.l2cache.overall_mshr_miss_latency::total 25032478193 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 25032488193 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for ReadReq accesses
1134,1135c1136,1137
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1138c1140
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for demand accesses
1141c1143
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for overall accesses
1145,1147c1147,1149
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65009.052275 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70230.092661 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.956395 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64938.640113 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70231.885429 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.419583 # average ReadReq mshr miss latency
1150,1151c1152,1153
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13778.777778 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13778.777778 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13790.473684 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13790.473684 # average UpgradeReq mshr miss latency
1154,1158c1156,1160
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.715074 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.183635 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency
1160c1162
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.449525 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.229787 # average overall mshr miss latency
1162,1163c1164,1165
< system.cpu.toL2Bus.trans_dist::ReadReq 7206353 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 7206352 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 7206354 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 7206353 # Transaction distribution
1170c1172
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340987 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340989 # Packet count per connected master and slave (bytes)
1172,1173c1174,1175
< system.cpu.toL2Bus.pkt_count::total 16590090 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330910976 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 16590092 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330911040 # Cumulative packet size per connected master and slave (bytes)
1175c1177
< system.cpu.toL2Bus.pkt_size::total 554422592 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 554422656 # Cumulative packet size per connected master and slave (bytes)
1177,1178c1179,1180
< system.cpu.toL2Bus.snoop_fanout::samples 8911778 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 3.027928 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 8911779 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.027928 # Request fanout histogram
1182,1185c1184,1185
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 8662891 97.21% 97.21% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 248887 2.79% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 8662892 97.21% 97.21% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 248887 2.79% 100.00% # Request fanout histogram
1187,1190c1187,1190
< system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 8911778 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 5067118500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 8911779 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 5067119000 # Layer occupancy (ticks)
1192c1192
< system.cpu.toL2Bus.respLayer0.occupancy 7756291499 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 7756292749 # Layer occupancy (ticks)
1194c1194
< system.cpu.toL2Bus.respLayer1.occupancy 4138722865 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 4138723116 # Layer occupancy (ticks)
1196,1197c1196,1197
< system.membus.trans_dist::ReadReq 314057 # Transaction distribution
< system.membus.trans_dist::ReadResp 314057 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 314058 # Transaction distribution
> system.membus.trans_dist::ReadResp 314058 # Transaction distribution
1199,1200c1199,1200
< system.membus.trans_dist::UpgradeReq 18 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 18 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 19 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 19 # Transaction distribution
1203,1206c1203,1206
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697288 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 697288 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435008 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 24435008 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697292 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 697292 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435072 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 24435072 # Cumulative packet size per connected master and slave (bytes)
1208c1208
< system.membus.snoop_fanout::samples 381815 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 381817 # Request fanout histogram
1212c1212
< system.membus.snoop_fanout::0 381815 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 381817 100.00% 100.00% # Request fanout histogram
1217,1218c1217,1218
< system.membus.snoop_fanout::total 381815 # Request fanout histogram
< system.membus.reqLayer0.occupancy 746604866 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 381817 # Request fanout histogram
> system.membus.reqLayer0.occupancy 746606366 # Layer occupancy (ticks)
1220c1220
< system.membus.respLayer1.occupancy 1648190996 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1648197495 # Layer occupancy (ticks)